180 lines
5.3 KiB
C
180 lines
5.3 KiB
C
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/*
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* Copyright (c) 1995. FirePower Systems, Inc.
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* (Do Not Distribute without permission)
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*
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* $RCSfile: fpcpu.h $
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* $Revision: 1.8 $
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* $Date: 1996/05/14 02:32:23 $
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* $Locker: $
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*
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*/
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#ifndef FPCPU_h
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#define FPCPU_h
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//
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// These defines setup access to the power pc chip itself. Reliance upon the
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// defines will isolate code from power pc chip variations and ease migration
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// to new cpus
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//
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//
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// Since the documentation refers to the bit positions of the cpu fields in
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// IBM relative format, handle the conversion of IBM bit position to shift
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// arguments
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//
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#define WORD(x) (( 1 ) << ( 31 - x ))
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/*
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************************************************************************
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**
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** Machine State Register
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**
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************************************************************************
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*/
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//
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// pull a bit out of the MSR: this is based on IBM bit ordering as shown in
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// the powerpc books ( 0 == MSB )
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//
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// #define MSR(x) ( ( HalpReadMsr() >> ( 31 - x ) ) & 0x01 )
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#define MSR(x) ( ( __builtin_get_msr() >> ( 31 - x ) ) & 0x01 )
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#define POW 13 // Power Management Enable
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#define TGPR 14 // Temporary GPR remapping
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#define ILE 15 // Exception Little-endian mode
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#define EE 16 // External interrupt enable
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#define PR 17 // Privilege Level
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#define FP 18 // Floating Point Enable
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#define ME 19 // Machine Check Enable
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#define FE0 20 // Floating Point Exception mode 0
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#define SE 21 // single step trace enable
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#define BE 22 // Branch Trace Enable
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#define FE1 23 // floating point exception mode 1
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#define IP 25 // Exception Prefix ( exception vector is 0xff... ?
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#define IR 26 // Instruction Address Translation
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#define DR 27 // Data Address Translation
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#define RI 30 // Recoverable Exception
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#define LE 31 // Endian bit (little or big )
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//
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// setup Flags to go along with the MSR bits
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//
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#define ENABLE_PWR_MGMT WORD( POW )
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#define ENABLE_GPR_REMAP WORD( TGPR )
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#define EXCEPTION_LE WORD( ILE )
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#define ENABLE_EXTERNAL_INTS WORD( EE )
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#define EXEC_AT_USER_LEVEL WORD( PR )
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#define FLOAT_PT_AVAIL WORD( FP )
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#define ENABLE_MACHINE_CHK WORD( ME )
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#define FLOAT_EXCPT_MODE0 WORD( FE0 )
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#define ENABLE_SGL_STP_TRCE WORD( SE )
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#define ENABLE_BRNCH_TRCE WORD( BE )
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#define FLOAT_EXCPT_MODE1 WORD( FE1 )
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#define EXCPT_PREFX_0xFFF WORD( IP )
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#define ENABLE_INSTR_TRANS WORD( IR )
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#define ENABLE_DATA_TRANS WORD( DR )
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#define EXCPTION_IS_RECOVBL WORD( RI )
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#define RUN_LITTLE_ENDIAN WORD( LE )
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/*
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************************************************************************
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**
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** Processor Version Register
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**
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************************************************************************
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*/
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#define CPU_VERSION ( ( ( HalpReadProcessorRev ) & 0xffff0000 ) >> 16 )
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#define CPU_REVISION ( ( ( HalpReadProcessorRev ) & 0x0000ffff ) )
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/*
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************************************************************************
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**
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** Block Address Translation registers
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**
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************************************************************************
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*/
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//
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// Here are defines for the UPPER 32 bit bat register:
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//
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#define PAGE_INDEX_BITS 0xfffe0000
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#define BLK_EFF_PI(x) ( x & PAGE_INDEX_BITS )
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#define A_128K_BLOCK_SIZE 0x00000000
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#define A_256K_BLOCK_SIZE 0x00000004
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#define A_512K_BLOCK_SIZE 0x0000000c
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#define A_1MEG_BLOCK_SIZE 0x0000001c
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#define A_2MEG_BLOCK_SIZE 0x0000003c
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#define A_4MEG_BLOCK_SIZE 0x0000007c
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#define A_8MEG_BLOCK_SIZE 0x000000fc
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#define A_16MB_BLOCK_SIZE 0x000001fc
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#define A_32MB_BLOCK_SIZE 0x000003fc
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#define A_64MB_BLOCK_SIZE 0x000007fc
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#define A_128M_BLOCK_SIZE 0x00000ffc
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#define A_256M_BLOCK_SIZE 0x00001ffc
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#define SUPERVISOR_ONLY 0x00000002
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#define USER_ACCESS_VALID 0x00000001
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//
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// The Lower BAT Register
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//
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#define BLOCK_REAL_PAGE_NUMBER(x) ( (x >> 8) & REAL_BITS)
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//
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// WIMG: VIMVENDERS BITS:
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//
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#define WRITE_THROUGH 0x00000040
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#define CACHE_INHIBIT 0x00000020
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#define MEMORY_COHRNCY 0x00000010
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#define GUARDED_BLOCK 0x00000008 // for IBAT use only....
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#define PAGE_RW_ACCESS 0x00000002
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#define PAGE_RO_ACCESS 0x00000001
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#define PAGE_UNAVAILBL 0x00000000
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/*
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************************************************************************
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**
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** Hardware Implementation Register 0 ( HID0 )
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**
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************************************************************************
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*/
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#define EMCP 0 // Enable Machine Check Pin
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#define EBA 2 // Enable Bus Address Parity Checking
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#define EBD 3 // Enable Bus Data Parity Checking
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#define SBCLK 4 // selct bus clock for test clock pin
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#define EICE 5 // Enable ISE outputs: pipeline tracking support
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#define ECLK 6 // Enable external test clock pin
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#define PAR 7 // Disable precharge of ARTRY_L and shared signals
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#define DOZE 8 // Doze mode: pll, time base, and snooping active
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#define NAP 9 // Nap Mode: pll and time base active
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#define SLEEP 10 // Sleep mode: no external clock required
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#define DPM 11 // Enable Dynamic power management
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#define RISEG 12 // Reserved for test
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#define ICE 16 // Instruction cache enable
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#define DCE 17 // Data cache enable
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#define ILOCK 18 // lock instruction cache
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#define DLOCK 19 // lock data cache
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#define ICFI 20 // instruction cache flash invalidate
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#define DCI 21 // Data cache flash invalidate
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#define FBIOB 27 // Force branch indirect on bus
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#define NOOPTI 31 // No-op touch instructions
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#define ENABLE_ICACHE WORD( ICE )
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#define ENABLE_DCACHE WORD( DCE )
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#define LOCK_ICACHE WORD( ILOCK )
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#define LOCK_DCACHE WORD( DLOCK )
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#define INVLIDAT_ICACHE WORD( ICFI )
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#define INVLIDAT_DCACHE WORD( DCI )
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#endif
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