190 lines
5.6 KiB
C
190 lines
5.6 KiB
C
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: fppci.h $
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* $Revision: 1.7 $
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* $Date: 1996/01/25 01:11:27 $
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* $Locker: $
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*
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* Herein are the definitions used to interact with PCI based devices. The
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* information is specific to the PCI spec as interpreted by FirePOWER and
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* not specific to the hardware ( or at the least minimally relavent to hw).
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*
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* Please look in FPIO.H for system specific information relevant to the IO
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* system such as memory maps or register read/write specifics.
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*
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*/
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#ifndef FPPCI_H
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#define FPPCI_H
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#ifdef HALDEBUG_ON
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#define PRINTBRIDGE(x) \
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if ( HalpDebugValue&DBG_PCI ) { \
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PULONG j; \
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ULONG i; \
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HalpDebugPrint("\nVendor: 0x%x, Dev: 0x%x, Cmd: 0x%x, Stat: 0x%x\n",\
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x->VendorID, x->DeviceID, x->Command, x->Status); \
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HalpDebugPrint("PrimaryBus: 0x%02x, SecondaryBus: 0x%02x", \
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x->u.type1.PrimaryBus, \
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x->u.type1.SecondaryBus); \
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HalpDebugPrint(" SubBus: 0x%02x, IOBase: 0x%02x, IOLimit:0x%02x\n", \
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x->u.type1.SubordinateBus,\
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x->u.type1.IOBase, \
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x->u.type1.IOLimit); \
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HalpDebugPrint("Secnd Status: 0x%04x, MemBase 0x%04x, MemLimit 0x%04x",\
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x->u.type1.SecondaryStatus, x->u.type1.MemoryBase, \
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x->u.type1.MemoryLimit ); \
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HalpDebugPrint(" IntLine: 0x%02x, IntPin: 0x%02x, BrdgeCntl: 0x%04x\n",\
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x->u.type1.InterruptLine, x->u.type1.InterruptPin, \
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x->u.type1.BridgeControl); \
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j=(PULONG)x; \
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for(i=0; i<(PCI_COMMON_HDR_LENGTH/4); j+=4, i+=4){ \
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HalpDebugPrint("%s 0x%08x, 0x%08x, 0x%08x, 0x%08x \n", \
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TBS, *j, *(j+1), *(j+2), *(j+3) ); \
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} \
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}
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#else
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#define PRINTBRIDGE(x)
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#endif //haldebug_on
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//
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// Hardware Specific Defines for FirePOWER:
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//
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#define TYPE1_ACCESS 0x1 // configuration space access is of Standard type 1
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#define TYPE2_ACCESS 0x2 // configuration space access is of Standard type 2
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#define BRIDGED_ACCESS 0x3 // FirePOWER specific access: modified type 1.
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/*
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* PCI Register config read/write macros: dependent on defines
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* in FPIO.H which must be included in the c file before this
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* file is included ( not included here to avoid multiple
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* includes of the file in any io specific file).
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*
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*/
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//
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// type - what type of data access: uchar, ushort, or ulong:
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// (UCHAR) bus - what pci bus ( up to 256 )
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// (UCHAR) Device - Which physical board: = physical slot. ( max of 32 )
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// (UCHAR) Fn - Which function on the board ( Max of 8 )
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// (UCHAR) Offset - The offset into the config header ( one of 64 words )
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//
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#define SLOT(DEV, FN ) (ULONG) ((ULONG)( (DEV & 0x1f) << 11 ) | \
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(ULONG)( (FN & 0x07) << 8 ) )
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#define CONFIG(BUSNUM, DEV, FN, OFFSET ) \
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(ULONG)( BUSNUM << 16 ) | SLOT(DEV, FN) | (ULONG)( OFFSET & 0xfc)
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#define RPciBusConfig(TYPE, BUSNUM, DEV, FN, OFFSET ) \
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(*(volatile type * const) (_PCIOBASE + \
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(ULONG)( CONFIG(BUSNUM, DEV, FN, OFFSET) ) ) )
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// (*(volatile type * const) (_PCIOBASE + (ULONG)( (0x800 << Slot) ) ) )
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//(*(volatile ULONG * const)(_PCIOBASE + (HalpPciConfigSlot[Slot] + Offset)))
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/*
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* Pci Configuration Header Defines:
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* These defines are in conjunction with what's in ntos\inc\pci.h.
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*
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*/
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//
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// Major Classes ( also called BaseClasses ) of devices.....
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//
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#define PRE_REV2_CLASS 0x00
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#define MASS_STORAGE_CLASS 0x01
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#define NETWORK_CTLR_CLASS 0x02
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#define DISPLAY_CTLR_CLASS 0x03
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#define MULTIMEDIA_CLASS 0x04
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#define MEMORY_CTLR_CLASS 0x05
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#define BRIDGE_CLASS 0x06
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//
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// SubClasses and Programming interfaces....
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//
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// REV2 CLASS
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//
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#define NON_VGA_SUBCLASS 0x00
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#define NON_VGA_PROGIF 0x00
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#define VGA_SUB_CLASS 0x01
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#define VGA_PROGIF 0x01
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// Mass Storage Classes
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//
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#define SCSI_SUBCLASS 0x00
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#define SCSI_PROGIF 0x00
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#define IDE_SUBCLASS 0x01
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#define IDE_PROGIF 0x00
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#define FLOPPY_SUBCLASS 0x02
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#define FLOPPY_PROGIF 0x00
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#define IPI_SUBCLASS 0x03
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#define IPI_PROGIF 0x00
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#define OTHER_SUBCLASS 0x80
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#define OTHER_PROGIF 0x00
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// Network Controller Classes
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//
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#define ENET_SUBCLASS 0x00
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#define ENET_PROGIF 0x00
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#define TKNRING_SUBCLASS 0x01
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#define TKNRING_PROGIF 0x00
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#define FDDI_SUBCLASS 0x02
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#define FDDI_PROGIF 0x00
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#define OTHR_NTWK_SUBCLASS 0x80
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#define OTHR_PROGIF 0x00
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// Display Controller Classes
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//
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#define VGA_SUBCLASS 0x00
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#define VGA_CTLR_PROGIF 0x00
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#define XGA_SUBCLASS 0x01
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#define XGA_PROGIF 0x00
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#define OTHR_DSPLY_SUBCLASS 0x80
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#define OTHR_DISPLY_PROGIF 0x00
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// Multimedia Device Classes
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//
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#define VIDEO_SUBCLASS 0x00
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#define VIDEO_PROGIF 0x00
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#define AUDIO_SUBCLASS 0x01
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#define AUDIO_PROGIF 0x00
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#define OTHR_MLTIMDIA_SUBCLASS 0x80
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#define OTHR_MLTIMDIA_PROGIF 0x00
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// Memory Controller Classes
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//
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#define RAM_SUBCLASS 0x00
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#define RAM_PROGIF 0x00
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#define FLASH_SUBCLASS 0x01
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#define FLASH_PROGIF 0x00
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#define OTHR_MEM_SUBCLASS 0x80
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#define OTHR_MEM_PROGIF 0x00
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// Bridge Device Classes
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//
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#define HOST_PCI_SUBCLASS 0x00
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#define HOST_PCI_PROGIF 0x00
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#define PCI_ISA_SUBCLASS 0x01
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#define PCI_ISA_PROGIF 0x00
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#define PCI_EISA_SUBCLASS 0x02
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#define PCI_EISA_PROGIF 0x00
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#define PCI_MCHANL_SUBCLASS 0x03
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#define PCI_MCHANL_PROGIF 0x00
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#define PCI_PCI_SUBCLASS 0x04
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#define PCI_PCI_PROGIF 0x00
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#define PCI_PCMCIA_SUBCLASS 0x05
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#define PCI_PCMCIA_PROGIF 0x00
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#define OTHER_BRIDGE_SUBCLASS 0x80
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#define OTHER_BRIDGE_PROGIF 0x00
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#define VENDOR_DIGITAL 0x1011
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#define DEVICE_21050 0x1
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#define PCI_ISA_IO_PHYSICAL_BASE 0x80000000
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#define PCI_IO_PHYSICAL_BASE 0x81000000
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#define PCI_IO_ADDRESS 0x00000001
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#define PCI_MEMORY_ADDRESS 0x00000000
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#endif
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