235 lines
5.5 KiB
C
235 lines
5.5 KiB
C
/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: pxcirrus.h $
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* $Revision: 1.2 $
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* $Date: 1996/01/11 07:09:18 $
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* $Locker: $
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*/
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/*
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* pxcirrus.h
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*
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* Defines for cirrus HAL support
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*/
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#define CIRRUS_VIDEO_MEMORY_BASE 0xc0000000
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#define CIRRUS_VENDOR_ID 0x1013
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#define CIRRUS_COMMAND_MASK 0x03
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#define CIRRUS_TEXT_MEM 0xb8000
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#define CIRRUS_FONT_MEM 0xa0000
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#define WRITE_CIRRUS_UCHAR(port,data) \
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*(volatile unsigned char *) \
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((ULONG)HalpIoControlBase+(port))=(UCHAR)(data), \
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KeFlushWriteBuffer()
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#define WRITE_CIRRUS_VRAM(port,data) \
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*((PUCHAR)((ULONG) HalpVideoMemoryBase + (port))) = (UCHAR) (data), \
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KeFlushWriteBuffer()
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#define WRITE_CIRRUS_USHORT(port,data) \
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*(volatile unsigned short*) \
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((ULONG)HalpIoControlBase+(port))=(USHORT)(data), \
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KeFlushWriteBuffer()
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#define READ_CIRRUS_VRAM(port) \
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*(HalpVideoMemoryBase + (port))
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#define READ_CIRRUS_UCHAR(port) \
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*(volatile unsigned char *)((ULONG)HalpIoControlBase + (port))
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#define setreg(port,index,data) \
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WRITE_CIRRUS_UCHAR(port,index), \
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WRITE_CIRRUS_UCHAR(port+1,data)
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#define outportb(port,data) \
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WRITE_CIRRUS_UCHAR(port,data)
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#define outp(port,data) outportb(port,data)
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#define inp(port) \
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READ_CIRRUS_UCHAR(port)
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#define INSTATUS_1 (PVOID) ((ULONG)((int)HalpIoControlBase + (int)0x03DA))
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//
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// Attributes Registers
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//
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static unsigned char attr3[] =
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{
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0x00, // AR0-ARF: Attribute Controller
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0x01, // Palette Registers
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0x02,
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0x03,
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0x04,
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0x05,
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0x14,
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0x07,
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0x38,
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0x39,
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0x3a,
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0x3b,
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0x3c,
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0x3d,
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0x3e,
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0x3f,
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0x0c, // AR10: Attribute Controller Mode
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// Blink Enable
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// Line Graphics Enable
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0x00, // AR11: Overscan (Border) color
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0x0f, // AR12: Color Plane Enable
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// All planes enabled
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0x08, // AR13: Pixel Panning
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0x00 // AR14: Color Select
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};
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//
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// CRT control
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//
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static unsigned char crtc3[] =
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{
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0x5f, // CR0: Horizontal Total
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0x4f, // CR1: Horizontal Display End
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0x50, // CR2: Start Horizontal Blinking
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0x82, // CR3: End Horizontal Blanking
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0x55, // CR4: Start Horizontal Retrace Pulse
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0x81, // CR5: End Horizontal Retrace Pulse
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0xbf, // CR6: Vertical Total
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0x1f, // CR7: Overflow
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0x00, // CR8: Row Scan
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0x4f, // CR9: Character Cell Height (16)
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0x0d, // CRa: Text Cursor Start Register
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0x0e, // CRb: Text Cursor End Register
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0x00, // CRc: Screen Start High
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0x00, // CRd: Screen Start Low
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0x00, // CRe: Text Cursor Location High
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0x00, // CRf: Text Cursor Location Low
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0x9c, // CR10: Vertical Sync Start
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0xae, // CR11: Vertical Sync End
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0x8f, // CR12: Vertical Display End
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0x28, // CR13: Offset
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0x1f, // CR14: Underline Row Scanline
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0x96, // CR15: Vertical Blank Start
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0xb9, // CR16: Vertical Blank End
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0xa3, // CR17: Mode Control
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0xff, // CR18: Line Compare
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0x00, // CR19: Interlace End
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00
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};
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//
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// Graphics Registers
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//
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static unsigned char graph3[] =
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{
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0x00, // GR0: Set/Reset Register
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0x00, // GR1: Set/Reset Enable Register
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0x00, // GR2: Color Compare
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0x00, // GR3: Data Rotate Register
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0x00, // GR4: Read Map Select Register
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0x10, // GR5: Mode Register (Odd/Even On)
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0x0e, // GR6: Miscellaneous Register
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// Memory Map b800:0
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// Chain Odd Maps to Even
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0x00, // GR7: Color Don't Care register
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0xff // GR8: Bit Mask Register
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};
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//
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// Sequencer Registers
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//
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static unsigned char seq3[] =
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{
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0x03, // SR0: Reset Register
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// Asynchronous and Synchronous reset
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0x00, // SR1: Clocking Mode
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0x03, // SR2: Plane Mask Register
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// Map 0 and 1 Enable
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0x00, // SR3: Character Map Select Register
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0x02, // SR4: Memory Mode
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// Extended Memory
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};
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//
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// Extended Sequencer Registers
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//
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static unsigned char eseq3[] =
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{
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0x6,0x12, // SR6: Unlock All Extensions
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0x7,0x00, // SR7: Extended Sequencer Mode
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0x8,0x40, // SR8: EEPROM Control
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// tsa 0x8,0x00, // SR8: EEPROM Control
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0xb,0x4a, // SRb: VCLK 0 Numerator Register
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0xc,0x5b, // SRc: VCLK 1 Numerator Register
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0xd,0x42, // SRd: VCLK 2 Numerator Register
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0xe,0x6e, // SRe: VCLK 3 Numerator Register
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//tsa x 0xe,0x7e, // SRe: VCLK 3 Numerator Register
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0xf,0x1d, // SRf: DRAM control
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0x12,0x00, // SR12: Cursor Attributes
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0x16,0x71, // SR16: Performance Tuning
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0x18,0x00, // SR18: Signature Generator Control
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0x1b,0x2b, // SR1b: VCLK Denominator and Post-Scalar
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0x1c,0x2f,
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0x1d,0x1f,
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0x1e,0x2a,
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//tsa x 0x1e,0x33,
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0x1f,0x1c,
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0xff
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};
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//
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// Extended CRTC Registers
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//
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static unsigned char ecrtc3[] =
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{
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0x19,0x00, // CR19: Inerlace End
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0x1a,0x00, // CR1a: Miscellaneous
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0x1b,0x00, // CR1b: Extended Display Controlls
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0xff
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};
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//
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// Extended Graphics Registers
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//
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static unsigned char egraph3[] =
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{
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0x9,0x00, // GR9: Offset Register 0
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0xa,0x00, // GRa: Offset Register 1
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0xb,0x00, // GRb: Graphics Controller Mode Extnsions
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0xc,0xff, // GRc: Color Key Compare
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0xd,0x00, // GRd: Color Key Compare Mask
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0x10,0x00, // GR10: Background Color Byte 1
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0x11,0x00, // GR11: Foreground Color Byte 1
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0xff
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};
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//
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// Extended Attribute Registers
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//
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static unsigned char eattr3[] =
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{
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0xff
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};
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