150 lines
5.5 KiB
C
150 lines
5.5 KiB
C
/*++ BUILD Version: 0001 // Increment this if a change has global effects
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Module Name:
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pxidaho.h
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Abstract:
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This header file defines the structures for the planar registers
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for an Idaho memory controller.
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Author:
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Jim Wooldridge
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Revision History:
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--*/
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/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: pxidaho.h $
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* $Revision: 1.5 $
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* $Date: 1996/01/11 07:10:40 $
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* $Locker: $
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*/
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//
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// define structures for the idaho memory controller
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//
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typedef struct _IDAHO_CONTROL {
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UCHAR Reserved1[0x808]; // Offset 0x000
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UCHAR HardfileLight; // Offset 0x808
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UCHAR Reserved2[3];
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UCHAR EquiptmentPresent; // Offset 0x80C
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UCHAR Reserved3[3];
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UCHAR PasswordProtect1; // Offset 0x810
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UCHAR Reserved4;
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UCHAR PasswordProtect2; // Offset 0x812
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UCHAR Reserved5;
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UCHAR L2Flush; // Offset 0x814
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UCHAR Reserved6[7];
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UCHAR SystemControl; // Offset 0x81c
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UCHAR Reserved9[0x1B];
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UCHAR Eoi9; // Offset 0x838
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UCHAR PciInterruptMap1; // Offset 0x839
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UCHAR Reserved10[2];
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UCHAR Eoi11; // Offset 0x83C
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UCHAR PciInterruptMap2; // Offset 0x83D
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UCHAR AudioSupport; // Offset 0x83E
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UCHAR Reserved11[0x14];
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UCHAR Reserved12[0x2C];
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UCHAR MemorySimmId1; // Offset 0x880
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UCHAR Reserved13[3];
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UCHAR MemorySimmId2; // Offset 0x884
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UCHAR Reserved14[3];
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UCHAR MemorySimmId3; // Offset 0x888
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UCHAR Reserved15[3];
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UCHAR MemorySimmId4; // Offset 0x88C
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UCHAR Reserved16[0x46B];
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ULONG ConfigAddress; // Offset 0xcf8
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ULONG ConfigData; // Offset 0xcfc
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} IDAHO_CONTROL, *PIDAHO_CONTROL;
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typedef struct _IDAHO_CONFIG {
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UCHAR VendorId[2]; // Offset 0x00 read-only
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UCHAR DeviceId[2]; // Offset 0x02 read-only
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UCHAR Command[2]; // Offset 0x04 unused
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UCHAR DeviceStatus[2]; // Offset 0x06
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UCHAR RevisionId; // Offset 0x08 read-only
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UCHAR Reserved1; // Offset 0x09
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UCHAR SubclassCode; // Offset 0x0A
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UCHAR ClassCode; // Offset 0x0B
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UCHAR Reserved2; // Offset 0x0C
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UCHAR Reserved3; // Offset 0x0D
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UCHAR HeaderType; // Offset 0x0E
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UCHAR BistControl; // Offset 0x0F
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UCHAR Reserved4[0x2C];
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UCHAR InterruptLine; // Offset 0x3C
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UCHAR InterruptPin; // Offset 0x3D
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UCHAR MinGnt; // Offset 0x3E
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UCHAR MaxGnt; // Offset 0x3F
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UCHAR BridgeNumber; // Offset 0x40
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UCHAR SubordBusNumber; // Offset 0x41
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UCHAR DisconnectCounter; // Offset 0x42
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UCHAR ReservedAnger;
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UCHAR SpecialCycleAddress[2]; // Offset 0x44
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UCHAR Reserved5[0x3A];
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UCHAR StartingAddress1; // Offset 0x80
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UCHAR StartingAddress2; // Offset 0x81
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UCHAR StartingAddress3; // Offset 0x82
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UCHAR StartingAddress4; // Offset 0x83
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UCHAR StartingAddress5; // Offset 0x84
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UCHAR StartingAddress6; // Offset 0x85
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UCHAR StartingAddress7; // Offset 0x86
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UCHAR StartingAddress8; // Offset 0x87
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UCHAR Reserved6[8];
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UCHAR EndingAddress1; // Offset 0x90
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UCHAR EndingAddress2; // Offset 0x91
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UCHAR EndingAddress3; // Offset 0x92
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UCHAR EndingAddress4; // Offset 0x93
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UCHAR EndingAddress5; // Offset 0x94
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UCHAR EndingAddress6; // Offset 0x95
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UCHAR EndingAddress7; // Offset 0x96
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UCHAR EndingAddress8; // Offset 0x97
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UCHAR Reserved7[8];
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UCHAR MemoryBankEnable; // Offset 0xA0
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UCHAR MemoryTiming1; // Offset 0xA1
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UCHAR MemoryTiming2; // Offset 0xA2
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UCHAR Reserved8;
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UCHAR SimmBank1; // Offset 0xA4
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UCHAR SimmBank2; // Offset 0xA5
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UCHAR SimmBank3; // Offset 0xA6
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UCHAR SimmBank4; // Offset 0xA7
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UCHAR Reserved9[9];
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UCHAR L2CacheStatus; // Offset 0xB1
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UCHAR Reserved10[2];
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UCHAR RefreshCycle; // Offset 0xB4
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UCHAR RefreshTimer; // Offset 0xB5
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UCHAR WatchdogTimer; // Offset 0xB6
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UCHAR BusTimer; // Offset 0xB7
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UCHAR LocalBusTimer; // Offset 0xB8
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UCHAR LocalBusIdleTimer; // Offset 0xB9
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UCHAR Options1; // Offset 0xBA
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UCHAR Options2; // Offset 0xBB
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UCHAR Reserved11[4];
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UCHAR EnableDetection1; // Offset 0xC0
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UCHAR ErrorDetection1; // Offset 0xC1
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UCHAR ErrorSimulation1; // Offset 0xC2
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UCHAR CpuBusErrorStatus; // Offset 0xC3
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UCHAR EnableDetection2; // Offset 0xC4
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UCHAR ErrorDetection2; // Offset 0xC5
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UCHAR ErrorSimulation2; // Offset 0xC6
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UCHAR PciBusErrorStatus; // Offset 0xC7
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UCHAR ErrorAddress[4]; // Offset 0xC8
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} IDAHO_CONFIG, *PIDAHO_CONFIG;
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