232 lines
7.6 KiB
C
232 lines
7.6 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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pxsiosup.h
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Abstract:
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The module defines the structures, and defines for the SIO chip set.
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The SIO_CONTROL structure is a superset of the EISA_CONTROL stucture.
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Differences from the Eisa control stucture are marked with comments.
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Author:
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Jim Wooldridge
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Revision History:
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--*/
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/*
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* Copyright (c) 1995 FirePower Systems, Inc.
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* DO NOT DISTRIBUTE without permission
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*
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* $RCSfile: pxsiosup.h $
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* $Revision: 1.5 $
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* $Date: 1996/01/11 07:13:41 $
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* $Locker: $
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*/
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#ifndef _SIO_
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#define _SIO_
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BOOLEAN
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HalpInitSMCSuperIo (
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VOID
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);
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BOOLEAN
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HalpInitNationalSuperIo (
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VOID
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);
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typedef struct _SIO_CONTROL {
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DMA1_CONTROL Dma1BasePort; // Offset 0x000
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UCHAR Reserved0[16];
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UCHAR Interrupt1ControlPort0; // Offset 0x020
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UCHAR Interrupt1ControlPort1; // Offset 0x021
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UCHAR Reserved1[32 - 2];
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UCHAR Timer1; // Offset 0x40
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UCHAR RefreshRequest; // Offset 0x41
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UCHAR SpeakerTone; // Offset 0x42
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UCHAR CommandMode1; // Offset 0x43
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UCHAR Reserved14[28];
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UCHAR ResetUbus; // Offset 0x60
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UCHAR NmiStatus; // Offset 0x61
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UCHAR Reserved15[14];
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UCHAR NmiEnable; // Offset 0x70
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UCHAR Reserved16[7];
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UCHAR BiosTimer[4]; // Offset 0x78
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UCHAR Reserved13[4];
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DMA_PAGE DmaPageLowPort; // Offset 0x080
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UCHAR Reserved2;
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UCHAR AlternateReset; // Offset 0x092
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UCHAR Reserved17[14];
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UCHAR Interrupt2ControlPort0; // Offset 0x0a0
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UCHAR Interrupt2ControlPort1; // Offset 0x0a1
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UCHAR Reserved3[32-2];
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DMA2_CONTROL Dma2BasePort; // Offset 0x0c0
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UCHAR CoprocessorError; // Offset 0x0f0
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UCHAR Reserved4[0x281];
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UCHAR SecondaryFloppyOutput; // Offset 0x372
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UCHAR Reserved18[0x27];
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UCHAR Reserved21[0x59];
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UCHAR PrimaryFloppyOutput; // Offset 0x3f2
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UCHAR Reserved5[19];
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UCHAR Dma1ExtendedModePort; // Offset 0x40b
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UCHAR Reserved6[4];
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UCHAR Channel0ScatterGatherCommand; // Offset 0x410
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UCHAR Channel1ScatterGatherCommand; // Offset 0x411
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UCHAR Channel2ScatterGatherCommand; // Offset 0x412
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UCHAR Channel3ScatterGatherCommand; // Offset 0x413
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UCHAR Reserved19; // Offset 0x414
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UCHAR Channel5ScatterGatherCommand; // Offset 0x415
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UCHAR Channel6ScatterGatherCommand; // Offset 0x416
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UCHAR Channel7ScatterGatherCommand; // Offset 0x417
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UCHAR Channel0ScatterGatherStatus; // Offset 0x418
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UCHAR Channel1ScatterGatherStatus; // Offset 0x419
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UCHAR Channel2ScatterGatherStatus; // Offset 0x41a
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UCHAR Channel3ScatterGatherStatus; // Offset 0x41b
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UCHAR Reserved20; // Offset 0x41c
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UCHAR Channel5ScatterGatherStatus; // Offset 0x41d
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UCHAR Channel6ScatterGatherStatus; // Offset 0x41e
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UCHAR Channel7ScatterGatherStatus; // Offset 0x41f
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UCHAR Channel0ScatterGatherTable[4]; // Offset 0x420
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UCHAR Channel1ScatterGatherTable[4]; // Offset 0x424
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UCHAR Channel2ScatterGatherTable[4]; // Offset 0x428
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UCHAR Channel3ScatterGatherTable[4]; // Offset 0x42c
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UCHAR Reserved22[4]; // Offset 0x430
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UCHAR Channel5ScatterGatherTable[4]; // Offset 0x434
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UCHAR Channel6ScatterGatherTable[4]; // Offset 0x438
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UCHAR Channel7ScatterGatherTable[4]; // Offset 0x43c
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UCHAR Reserved8[0x40];
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DMA_PAGE DmaPageHighPort; // Offset 0x480
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UCHAR Reserved10[70];
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UCHAR Dma2ExtendedModePort; // Offset 0x4d6
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} SIO_CONTROL, *PSIO_CONTROL;
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typedef struct _SIO_CONFIG {
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UCHAR VendorId[2]; // Offset 0x00 read-only
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UCHAR DeviceId[2]; // Offset 0x02 read-only
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UCHAR Command[2]; // Offset 0x04 unused
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UCHAR DeviceStatus[2]; // Offset 0x06
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UCHAR RevisionId; // Offset 0x08 read-only
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UCHAR Reserved1[0x37]; // Offset 0x09
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UCHAR PciControl; // Offset 0x40
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UCHAR PciArbiterControl; // Offset 0x41
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UCHAR PciArbiterPriorityControl; // Offset 0x42
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UCHAR Reserved2; // Offset 0x43
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UCHAR MemCsControl; // Offset 0x44
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UCHAR MemCsBottomOfHole; // Offset 0x45
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UCHAR MemCsTopOfHole; // Offset 0x46
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UCHAR MemCsTopOfMemory; // Offset 0x47
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UCHAR IsaAddressDecoderControl; // Offset 0x48
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UCHAR IsaAddressDecoderRomEnable; // Offset 0x49
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UCHAR IsaAddressDecoderBottomOfHole; // Offset 0x4a
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UCHAR IsaAddressDecoderTopOfHole; // Offset 0x4b
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UCHAR IsaControllerRecoveryTimer; // Offset 0x4c
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UCHAR IsaClockDivisor; // Offset 0x4d
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UCHAR UtilityBusEnableA; // Offset 0x4e
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UCHAR UtilityBusEnableB; // Offset 0x4f
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UCHAR Reserved3[4]; // Offset 0x50
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UCHAR MemCsAttribute1; // Offset 0x54
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UCHAR MemCsAttribute2; // Offset 0x55
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UCHAR MemCsAttribute3; // Offset 0x56
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UCHAR ScatterGatherBaseAddress; // Offset 0x57
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UCHAR Reserved4[0x8]; // Offset 0x58
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UCHAR PciIrq0RouteControl; // Offset 0x60
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UCHAR PciIrq1RouteControl; // Offset 0x61
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UCHAR PciIrq2RouteControl; // Offset 0x62
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UCHAR PciIrq3RouteControl; // Offset 0x63
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UCHAR Reserved5[0x1C]; // Offset 0x64
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UCHAR BiosTimerBaseAddress[2]; // Offset 0x80
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}SIO_CONFIG, *PSIO_CONFIG;
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//
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// Define constants used by SIO config
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//
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// PCI control register - bit values
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#define ENABLE_PCI_POSTED_WRITE_BUFFER 0x04
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#define ENABLE_ISA_MASTER_LINE_BUFFER 0x02
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#define EANBLE_DMA_LINE_BUFFER 0x01
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// PCI Arbiter contol register - bit values
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#define ENABLE_GAT 0x01
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// ISA CLock Divisor register - bit values
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#define ENABLE_COPROCESSOR_ERROR 0x20
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#define ENABLE_MOUSE_SUPPORT 0x10
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#define RSTDRV 0x08
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#define SYSCLK_DIVISOR 0x00
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//Utility Bus Chip Select A - bit values
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#define ENABLE_RTC 0x01
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#define ENABLE_KEYBOARD 0x02
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#define ENABLE_IDE_DECODE 0x10
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//Utility Bus Chip Select B - bit values
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#define ENABLE_RAM_DECODE 0x80
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#define ENABLE_PORT92 0x40
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#define DISABLE_PARALLEL_PORT 0x30
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#define DISABLE_SERIAL_PORTB 0x0c
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#define DISABLE_SERIAL_PORTA 0x03
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// Interrupt controller - bit values
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#define LEVEL_TRIGGERED 0x08
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#define SINGLE_MODE 0x02
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// NMI status/control - bit values
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#define DISABLE_IOCHK_NMI 0x08
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#define DISABLE_PCI_SERR_NMI 0x04
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// NMI enable - bit values
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#define DISABLE_NMI 0x80
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// DMA command - bit values
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#define DACK_ASSERT_HIGH 0x80
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#define DREQ_ASSERT_LOW 0x40
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#endif
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//
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// Define 8259 constants
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//
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#define SPURIOUS_VECTOR 7
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#define HIGHEST_8259_VECTOR 15
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//
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// Define 8254 timer constants
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//
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//
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// Convert the interval to rollover count for 8254 Timer1 device.
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// Since timer1 counts down a 16 bit value at a rate of 1.193M counts-per-
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// sec, the computation is:
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// RolloverCount = (Interval * 0.0000001) * (1.193 * 1000000)
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// = Interval * 0.1193
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// = Interval * 1193 / 10000
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//
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//
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#define COMMAND_8254_COUNTER0 0x00 // Select count 0
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#define COMMAND_8254_RW_16BIT 0x30 // Read/Write LSB firt then MSB
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#define COMMAND_8254_MODE2 0x4 // Use mode 2
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#define COMMAND_8254_BCD 0x0 // Binary count down
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#define COMMAND_8254_LATCH_READ 0x0 // Latch read command
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