580 lines
19 KiB
C
580 lines
19 KiB
C
/*++
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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initsys.c
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Abstract:
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This module implements the platform specific portions of the
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HAL initialization.
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Author:
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Michael D. Kinney 3-May-1995
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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//
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// Type Declarations
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//
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typedef
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VOID
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(*POPERATING_SYSTEM_STARTED) (
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VOID
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);
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//
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// Define global data used to determine the type of system I/O architecture to use.
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//
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ULONG HalpIoArchitectureType = UNKNOWN_PROCESSOR_MODULE;
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//
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// Define global data used to calibrate and stall processor execution.
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//
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ULONG HalpProfileCountRate;
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ULONG IoSpaceAlreadyMapped = FALSE;
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ULONG HalpModuleChipSetRevision = MODULE_CHIP_SET_REVISION_UNKNOWN;
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BOOLEAN HalpModuleHardwareFlushing;
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UCHAR HalpSecondPciBridgeBusNumber = 2;
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ULONG HalpMotherboardType = MOTHERBOARD_UNKNOWN;
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UCHAR *HalpInterruptLineToBit;
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UCHAR *HalpBitToInterruptLine;
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UCHAR *HalpInterruptLineToVirtualIsa;
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UCHAR *HalpVirtualIsaToInterruptLine;
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ULONGLONG HalpNoncachedDenseBasePhysicalSuperPage;
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ULONGLONG HalpPciDenseBasePhysicalSuperPage;
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ULONGLONG HalpPciConfig0BasePhysical;
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ULONGLONG HalpPciConfig1BasePhysical;
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ULONGLONG HalpIsaIoBasePhysical;
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ULONGLONG HalpIsa1IoBasePhysical;
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ULONGLONG HalpIsaMemoryBasePhysical;
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ULONGLONG HalpIsa1MemoryBasePhysical;
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ULONGLONG HalpPciIoBasePhysical;
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ULONGLONG HalpPci1IoBasePhysical;
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ULONGLONG HalpPciMemoryBasePhysical;
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ULONGLONG HalpPci1MemoryBasePhysical;
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PPLATFORM_RANGE_LIST HalpRangeList = NULL;
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ULONG HalpIntel82378BusNumber = 0;
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ULONG HalpIntel82378DeviceNumber = 0;
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ULONG HalpSecondIntel82378DeviceNumber = 0;
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ULONG HalpNonExistentPciDeviceMask = ~TREB20_MOTHERBOARD_PCI_DEVICE_MASK;
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ULONG HalpNonExistentPci1DeviceMask = 0;
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ULONG HalpNonExistentPci2DeviceMask = 0;
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ULONG HalpNumberOfIsaBusses;
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ULONG HalpVgaDecodeBusNumber;
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//
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// Function prototypes.
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//
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VOID
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HalpGetPlatformParameterBlock(
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VOID
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);
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ULONG FindIntel82378(ULONG Dec2105xBusNumber,ULONG Dec2105xDeviceNumber,ULONG BusNumber,ULONG IsaBusNumber)
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{
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ULONG i;
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ULONG MaxDevice;
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if (BusNumber == 0) {
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MaxDevice = PCI_MAX_LOCAL_DEVICE;
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} else {
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MaxDevice = 31;
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}
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for(i=0;i<=MaxDevice;i++) {
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if (HalpPciLowLevelConfigRead(BusNumber,i,0,0) == 0x04848086) {
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return(i);
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}
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}
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return(0);
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}
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VOID
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HalpGetIoArchitectureType(
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VOID
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)
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/*++
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Routine Description:
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This function gets the I/O Architecture Type from the Platform Parameter Block
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retrieved from the firmware.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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ULONG Device16;
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ULONG Device17;
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//
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// If the I/O Architecture Type is already known, then just return.
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//
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if (HalpIoArchitectureType != UNKNOWN_PROCESSOR_MODULE) {
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return;
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}
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//
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// If the Platform Parameter Block has not been retrieved from the firmware,
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// then do it now.
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//
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if (HalpPlatformParameterBlock == NULL) {
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HalpGetPlatformParameterBlock();
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}
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//
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// Check for the 21164(EV5) Apocolypse Module Type.
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//
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if (strcmp(HalpPlatformParameterBlock->ModuleName,"APOCALYPSE1.0")==0) {
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HalpIoArchitectureType = EV5_PROCESSOR_MODULE;
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}
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//
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// Check for the 21064(EV4) Rogue Module Type.
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//
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if (strcmp(HalpPlatformParameterBlock->ModuleName,"ROGUE2.0")==0) {
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HalpIoArchitectureType = EV4_PROCESSOR_MODULE;
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}
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//
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// If the I/O Architecture Type is still unknown then HALT.
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//
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if (HalpIoArchitectureType == UNKNOWN_PROCESSOR_MODULE) {
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for(;;);
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}
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//
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// Get the processor module's chip set revision.
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//
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HalpModuleChipSetRevision = HalpGetModuleChipSetRevision();
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//
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// Limit the chip set revision to the highest one allowed by this HAL.
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//
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE && HalpModuleChipSetRevision > EV5_MAX_CHIP_SET_REVISION) {
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HalpModuleChipSetRevision = EV5_MAX_CHIP_SET_REVISION;
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}
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if (HalpIoArchitectureType == EV4_PROCESSOR_MODULE && HalpModuleChipSetRevision > EV4_MAX_CHIP_SET_REVISION) {
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HalpModuleChipSetRevision = EV4_MAX_CHIP_SET_REVISION;
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}
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//
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// See if the module chip set supports hardware flushing.
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//
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HalpModuleHardwareFlushing = TRUE;
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
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switch (HalpModuleChipSetRevision) {
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case 0 : HalpModuleHardwareFlushing = FALSE;
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break;
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}
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}
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//
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// Determine base physical address of Dense PCI Space and the PCI Configuration Spaces
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//
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if (HalpIoArchitectureType == EV4_PROCESSOR_MODULE) {
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HalpNoncachedDenseBasePhysicalSuperPage = ROGUE_NONCACHED_DENSE_BASE_PHYSICAL_SUPERPAGE;
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HalpPciDenseBasePhysicalSuperPage = ROGUE_PCI_DENSE_BASE_PHYSICAL_SUPERPAGE;
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HalpPciConfig0BasePhysical = ROGUE_PCI_CONFIG0_BASE_PHYSICAL;
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HalpPciConfig1BasePhysical = ROGUE_PCI_CONFIG1_BASE_PHYSICAL;
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE && (HalpModuleChipSetRevision==0 || HalpModuleChipSetRevision==1)) {
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HalpNoncachedDenseBasePhysicalSuperPage = APOC1_NONCACHED_DENSE_BASE_PHYSICAL_SUPERPAGE;
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HalpPciDenseBasePhysicalSuperPage = APOC1_PCI_DENSE_BASE_PHYSICAL_SUPERPAGE;
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HalpPciConfig0BasePhysical = APOC1_PCI_CONFIG0_BASE_PHYSICAL;
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HalpPciConfig1BasePhysical = APOC1_PCI_CONFIG1_BASE_PHYSICAL;
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE && HalpModuleChipSetRevision==2) {
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HalpNoncachedDenseBasePhysicalSuperPage = APOC2_NONCACHED_DENSE_BASE_PHYSICAL_SUPERPAGE;
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HalpPciDenseBasePhysicalSuperPage = APOC2_PCI_DENSE_BASE_PHYSICAL_SUPERPAGE;
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HalpPciConfig0BasePhysical = APOC2_PCI_CONFIG0_BASE_PHYSICAL;
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HalpPciConfig1BasePhysical = APOC2_PCI_CONFIG1_BASE_PHYSICAL;
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}
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//
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// Determine the motherboard type. Assume TREBBIA20 so we can do some config cycles.
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//
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HalpMotherboardType = TREBBIA20;
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Device16 = HalpPciLowLevelConfigRead(0,0x10,0,0);
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Device17 = HalpPciLowLevelConfigRead(0,0x11,0,0);
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//
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// Now assume motherboard type is unknown and check out values returned from config cycles.
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//
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HalpMotherboardType = MOTHERBOARD_UNKNOWN;
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if (Device16 == 0x00211011 && Device17 == 0x00211011) {
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HalpMotherboardType = TREBBIA20;
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//
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// Find and initialize up to two Jubilee adapters.
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//
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HalpNumberOfIsaBusses = 1;
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HalpIntel82378BusNumber = 1;
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HalpIntel82378DeviceNumber = FindIntel82378(0,0x11,1,0);
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HalpSecondPciBridgeBusNumber = (UCHAR)((HalpPciLowLevelConfigRead(0,0x10,0,0x18) >> 8) & 0xff);
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HalpSecondIntel82378DeviceNumber = FindIntel82378(0,0x10,HalpSecondPciBridgeBusNumber,1);
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if (HalpSecondIntel82378DeviceNumber != 0) {
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HalpNumberOfIsaBusses = 2;
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}
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HalpVgaDecodeBusNumber = 0x00;
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if (HalpPciLowLevelConfigRead(0,0x11,0,0x3c) & 0x00080000) {
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HalpVgaDecodeBusNumber |= 0x01;
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}
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if (HalpPciLowLevelConfigRead(0,0x10,0,0x3c) & 0x00080000) {
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HalpVgaDecodeBusNumber |= 0x02;
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}
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}
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if (Device16 == 0x04848086 && Device17 == 0x00011011) {
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HalpMotherboardType = TREBBIA13;
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HalpNumberOfIsaBusses = 1;
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HalpIntel82378BusNumber = 0;
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HalpIntel82378DeviceNumber = 0x10;
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HalpVgaDecodeBusNumber = 0x01;
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if (HalpPciLowLevelConfigRead(0,0x11,0,0x3c) & 0x00080000) {
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HalpVgaDecodeBusNumber |= 0x02;
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}
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}
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//
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// If the Motherboard Type is unknown then HALT.
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//
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if (HalpMotherboardType == MOTHERBOARD_UNKNOWN) {
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for(;;);
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}
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//
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// Determine the PCI interrupt translation tables.
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//
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if (HalpMotherboardType == TREBBIA13) {
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HalpNonExistentPciDeviceMask = ~TREB13_MOTHERBOARD_PCI_DEVICE_MASK;
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HalpNonExistentPci1DeviceMask = 0;
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HalpNonExistentPci2DeviceMask = 0;
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HalpInterruptLineToBit = Treb13InterruptLineToBit;
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HalpBitToInterruptLine = Treb13BitToInterruptLine;
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HalpInterruptLineToVirtualIsa = Treb13InterruptLineToVirtualIsa;
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HalpVirtualIsaToInterruptLine = Treb13VirtualIsaToInterruptLine;
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if (HalpPlatformParameterBlock->FirmwareRevision >= 50) {
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if (!((TREB13SETUPINFO *)(HalpPlatformSpecificExtension->AdvancedSetupInfo))->EnableAmd1) {
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HalpNonExistentPciDeviceMask |= (1 << 0x0d);
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}
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if (!((TREB13SETUPINFO *)(HalpPlatformSpecificExtension->AdvancedSetupInfo))->EnableAmd2) {
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HalpNonExistentPciDeviceMask |= (1 << 0x0f);
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}
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}
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}
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if (HalpMotherboardType == TREBBIA20) {
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HalpNonExistentPciDeviceMask = ~TREB20_MOTHERBOARD_PCI_DEVICE_MASK;
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HalpNonExistentPci1DeviceMask = 0;
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HalpNonExistentPci2DeviceMask = 0;
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HalpInterruptLineToBit = Treb20InterruptLineToBit;
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HalpBitToInterruptLine = Treb20BitToInterruptLine;
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HalpInterruptLineToVirtualIsa = Treb20InterruptLineToVirtualIsa;
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HalpVirtualIsaToInterruptLine = Treb20VirtualIsaToInterruptLine;
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if (HalpPlatformParameterBlock->FirmwareRevision >= 50) {
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if (!((TREB20SETUPINFO *)(HalpPlatformSpecificExtension->AdvancedSetupInfo))->EnableNcr) {
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HalpNonExistentPci2DeviceMask |= (1 << 0x07);
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}
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}
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}
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//
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// Determine base physical address of thr ISA IO Address Space and the address translation table.
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//
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if (HalpIoArchitectureType == EV4_PROCESSOR_MODULE) {
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if (HalpMotherboardType == TREBBIA13) {
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HalpIsaIoBasePhysical = TREB1_ROGUE_ISA_IO_BASE_PHYSICAL;
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HalpIsa1IoBasePhysical = (ULONGLONG)(0);
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HalpIsaMemoryBasePhysical = TREB1_ROGUE_ISA_MEMORY_BASE_PHYSICAL;
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HalpIsa1MemoryBasePhysical = (ULONGLONG)(0);
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HalpPciIoBasePhysical = TREB1_ROGUE_PCI_IO_BASE_PHYSICAL;
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HalpPci1IoBasePhysical = (ULONGLONG)(0);
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HalpPciMemoryBasePhysical = TREB1_ROGUE_PCI_MEMORY_BASE_PHYSICAL;
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HalpPci1MemoryBasePhysical = (ULONGLONG)(0);
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if (HalpModuleChipSetRevision == 0) {
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HalpRangeList = Rogue0Trebbia13RangeList;
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}
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if (HalpModuleChipSetRevision == 1) {
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HalpRangeList = Rogue1Trebbia13RangeList;
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}
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}
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if (HalpMotherboardType == TREBBIA20) {
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HalpIsaIoBasePhysical = TREB2_ROGUE_ISA_IO_BASE_PHYSICAL;
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HalpIsa1IoBasePhysical = TREB2_ROGUE_ISA1_IO_BASE_PHYSICAL;
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HalpIsaMemoryBasePhysical = TREB2_ROGUE_ISA_MEMORY_BASE_PHYSICAL;
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HalpIsa1MemoryBasePhysical = TREB2_ROGUE_ISA1_MEMORY_BASE_PHYSICAL;
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HalpPciIoBasePhysical = TREB2_ROGUE_PCI_IO_BASE_PHYSICAL;
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HalpPci1IoBasePhysical = TREB2_ROGUE_PCI1_IO_BASE_PHYSICAL;
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HalpPciMemoryBasePhysical = TREB2_ROGUE_PCI_MEMORY_BASE_PHYSICAL;
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HalpPci1MemoryBasePhysical = TREB2_ROGUE_PCI1_MEMORY_BASE_PHYSICAL;
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if (HalpModuleChipSetRevision == 0) {
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HalpRangeList = Rogue0Trebbia20RangeList;
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}
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if (HalpModuleChipSetRevision == 1) {
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HalpRangeList = Rogue1Trebbia20RangeList;
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}
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}
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE && (HalpModuleChipSetRevision==0 || HalpModuleChipSetRevision==1)) {
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if (HalpMotherboardType == TREBBIA13) {
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HalpIsaIoBasePhysical = TREB1_APOC1_ISA_IO_BASE_PHYSICAL;
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HalpIsa1IoBasePhysical = (ULONGLONG)(0);
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HalpIsaMemoryBasePhysical = TREB1_APOC1_ISA_MEMORY_BASE_PHYSICAL;
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HalpIsa1MemoryBasePhysical = (ULONGLONG)(0);
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HalpPciIoBasePhysical = TREB1_APOC1_PCI_IO_BASE_PHYSICAL;
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HalpPci1IoBasePhysical = (ULONGLONG)(0);
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HalpPciMemoryBasePhysical = TREB1_APOC1_PCI_MEMORY_BASE_PHYSICAL;
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HalpPci1MemoryBasePhysical = (ULONGLONG)(0);
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HalpRangeList = Apoc10Trebbia13RangeList;
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}
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if (HalpMotherboardType == TREBBIA20) {
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HalpIsaIoBasePhysical = TREB2_APOC1_ISA_IO_BASE_PHYSICAL;
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HalpIsa1IoBasePhysical = TREB2_APOC1_ISA1_IO_BASE_PHYSICAL;
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HalpIsaMemoryBasePhysical = TREB2_APOC1_ISA_MEMORY_BASE_PHYSICAL;
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HalpIsa1MemoryBasePhysical = TREB2_APOC1_ISA1_MEMORY_BASE_PHYSICAL;
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HalpPciIoBasePhysical = TREB2_APOC1_PCI_IO_BASE_PHYSICAL;
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HalpPci1IoBasePhysical = TREB2_APOC1_PCI1_IO_BASE_PHYSICAL;
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HalpPciMemoryBasePhysical = TREB2_APOC1_PCI_MEMORY_BASE_PHYSICAL;
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HalpPci1MemoryBasePhysical = TREB2_APOC1_PCI1_MEMORY_BASE_PHYSICAL;
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HalpRangeList = Apoc10Trebbia20RangeList;
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}
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}
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if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE && HalpModuleChipSetRevision==2) {
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if (HalpMotherboardType == TREBBIA13) {
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HalpIsaIoBasePhysical = TREB1_APOC2_ISA_IO_BASE_PHYSICAL;
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HalpIsa1IoBasePhysical = (ULONGLONG)(0);
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HalpIsaMemoryBasePhysical = TREB1_APOC2_ISA_MEMORY_BASE_PHYSICAL;
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HalpIsa1MemoryBasePhysical = (ULONGLONG)(0);
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HalpPciIoBasePhysical = TREB1_APOC2_PCI_IO_BASE_PHYSICAL;
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HalpPci1IoBasePhysical = (ULONGLONG)(0);
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HalpPciMemoryBasePhysical = TREB1_APOC2_PCI_MEMORY_BASE_PHYSICAL;
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HalpPci1MemoryBasePhysical = (ULONGLONG)(0);
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HalpRangeList = Apoc20Trebbia13RangeList;
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}
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if (HalpMotherboardType == TREBBIA20) {
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HalpIsaIoBasePhysical = TREB2_APOC2_ISA_IO_BASE_PHYSICAL;
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HalpIsa1IoBasePhysical = TREB2_APOC2_ISA1_IO_BASE_PHYSICAL;
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HalpIsaMemoryBasePhysical = TREB2_APOC2_ISA_MEMORY_BASE_PHYSICAL;
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HalpIsa1MemoryBasePhysical = TREB2_APOC2_ISA1_MEMORY_BASE_PHYSICAL;
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HalpPciIoBasePhysical = TREB2_APOC2_PCI_IO_BASE_PHYSICAL;
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HalpPci1IoBasePhysical = TREB2_APOC2_PCI1_IO_BASE_PHYSICAL;
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HalpPciMemoryBasePhysical = TREB2_APOC2_PCI_MEMORY_BASE_PHYSICAL;
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HalpPci1MemoryBasePhysical = TREB2_APOC2_PCI1_MEMORY_BASE_PHYSICAL;
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HalpRangeList = Apoc20Trebbia20RangeList;
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}
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}
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//
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// If the address translation table is still NULL then HALT.
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//
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if (HalpRangeList == NULL) {
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for(;;);
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}
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}
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BOOLEAN
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HalpInitSystem (
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IN ULONG Phase,
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IN PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This function initializes the Hardware Architecture Layer (HAL).
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Arguments:
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Phase - Supplies the initialization phase (zero or one).
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LoaderBlock - Supplies a pointer to a loader parameter block.
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Return Value:
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A value of TRUE is returned is the initialization was successfully
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complete. Otherwise a value of FALSE is returend.
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--*/
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{
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POPERATING_SYSTEM_STARTED PrivateOperatingSystemStarted;
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PSYSTEM_PARAMETER_BLOCK SystemParameterBlock = SYSTEM_BLOCK;
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PHYSICAL_ADDRESS CacheFlushPhysicalAddress;
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if (Phase == 0) {
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//
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// Phase 0 initialization.
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//
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HalpGetIoArchitectureType();
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if (HalpIoArchitectureType != EV5_PROCESSOR_MODULE) {
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//
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// Inform the firmware that an operating system has taken control of the system.
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//
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if ((SystemParameterBlock->VendorVectorLength / 4) >= 50) {
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|
PrivateOperatingSystemStarted = *(POPERATING_SYSTEM_STARTED *)((ULONG)(SystemParameterBlock->VendorVector) + 50*4);
|
|
if (PrivateOperatingSystemStarted != NULL) {
|
|
PrivateOperatingSystemStarted();
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Map all I/O Spaces used by the HAL
|
|
//
|
|
|
|
HalpMapIoSpace();
|
|
IoSpaceAlreadyMapped = TRUE;
|
|
|
|
HalpInitializeX86DisplayAdapter();
|
|
|
|
//
|
|
// Initialize Dma Cache Parameters
|
|
//
|
|
|
|
if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
|
|
HalpMapBufferSize = APOC_DMA_CACHE_SIZE;
|
|
HalpMapBufferPhysicalAddress.QuadPart = APOC_DMA_CACHE_BASE_PHYSICAL;
|
|
} else {
|
|
HalpMapBufferSize = ROGUE_DMA_CACHE_SIZE;
|
|
HalpMapBufferPhysicalAddress.QuadPart = ROGUE_DMA_CACHE_BASE_PHYSICAL;
|
|
}
|
|
|
|
return TRUE;
|
|
|
|
} else {
|
|
|
|
UCHAR Message[80];
|
|
|
|
//
|
|
// Phase 1 initialization.
|
|
//
|
|
|
|
if (HalpMotherboardType == TREBBIA13) {
|
|
HalDisplayString("DeskStation Technology UniFlex/Raptor 3 Motherboard Rev. 1\n\r");
|
|
}
|
|
|
|
if (HalpMotherboardType == TREBBIA20) {
|
|
HalDisplayString("DeskStation Technology Raptor ReFlex Motherboard Rev. 2\n\r");
|
|
}
|
|
|
|
if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
|
|
sprintf(Message,"DeskStation Technology ALPHA 21164 Processor Module Rev. %d\n\r",HalpModuleChipSetRevision);
|
|
} else {
|
|
sprintf(Message,"DeskStation Technology ALPHA 21064A Processor Module Rev. %d\n\r",HalpModuleChipSetRevision);
|
|
}
|
|
HalDisplayString(Message);
|
|
|
|
if (HalpModuleHardwareFlushing == TRUE) {
|
|
HalDisplayString("Hardware Flushing is Enabled\n\r");
|
|
} else {
|
|
HalDisplayString("Hardware Flushing is Disabled\n\r");
|
|
}
|
|
|
|
//
|
|
// Compute the profile interrupt rate.
|
|
//
|
|
|
|
HalpProfileCountRate = ((1000 * 1000 * 10) / KeQueryTimeIncrement());
|
|
|
|
//
|
|
// Map Cache Flush Region.
|
|
//
|
|
|
|
if (HalpIoArchitectureType == EV5_PROCESSOR_MODULE) {
|
|
CacheFlushPhysicalAddress.QuadPart = APOC_CACHE_FLUSH_BASE_PHYSICAL;
|
|
HalpCacheFlushBase = MmMapIoSpace(CacheFlushPhysicalAddress,APOC_CACHE_FLUSH_SIZE,TRUE);
|
|
} else {
|
|
CacheFlushPhysicalAddress.QuadPart = ROGUE_CACHE_FLUSH_BASE_PHYSICAL;
|
|
HalpCacheFlushBase = MmMapIoSpace(CacheFlushPhysicalAddress,ROGUE_CACHE_FLUSH_SIZE,TRUE);
|
|
}
|
|
|
|
//
|
|
// Set the time increment value and connect the real clock interrupt
|
|
// routine.
|
|
//
|
|
|
|
PCR->InterruptRoutine[UNIFLEX_CLOCK2_LEVEL] = HalpClockInterrupt;
|
|
|
|
HalpEnableEisaInterrupt(UNIFLEX_CLOCK2_LEVEL,Latched);
|
|
|
|
//
|
|
// Initialize profiler.
|
|
//
|
|
|
|
HalpInitializeProfiler();
|
|
|
|
//
|
|
// Initialize the existing bus handlers.
|
|
//
|
|
|
|
HalpRegisterInternalBusHandlers();
|
|
|
|
//
|
|
// Initialize the PCI bus.
|
|
//
|
|
|
|
HalpInitializePCIBus ();
|
|
}
|
|
}
|
|
|