215 lines
8.2 KiB
C
215 lines
8.2 KiB
C
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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rattler.h
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Abstract:
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This file defines the structures and definitions describing the
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Rattler EV5 to CBUS bridge chip
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Author:
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Steve Brooks 28-Dec 1994
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Environment:
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Kernel mode
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Revision History:
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--*/
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#ifndef _RATTLERH_
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#define _RATTLERH_
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typedef struct _RATTLER_CPU_CSRS{
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UCHAR Creg; // (0000) Configuration Register
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UCHAR Esreg; // (0020) Error Summary Register
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UCHAR Evbcr; // (0040) EVB Control Register
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UCHAR Evbvear; // (0060) EVB Victim Error Address Register
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UCHAR Evbcer; // (0080) EVB Correctable Error Register
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UCHAR Evbcear; // (00a0) EVB Correctable error address register
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UCHAR Evbuer; // (00c0) EVB Uncorrectable Error Register
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UCHAR Evbuear; // (00e0) EVB Uncorrectable Error Address register
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UCHAR Evresv; // (0100) EVB Reserver Register
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UCHAR Dtctr; // (0120) Duptag Control register
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UCHAR Dter; // (0140) Duptag error register
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UCHAR Dttcr; // (0160) Duptag test control register
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UCHAR Dttr; // (0180) Duptag test register
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UCHAR Dtresv; // (01a0) Duptag reserve register
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UCHAR Ibcsr; // (01c0) I-Bus control and status register
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UCHAR Ibear; // (01e0) I-Bus error address register
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UCHAR Acr; // (0200) Arbitration control register
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UCHAR Cbcr; // (0220) Cobra-bus2 Control register
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UCHAR Cber; // (0240) Cobra-bus2 Error register
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UCHAR Cbealr; // (0260) Cobra-bus2 Error address low register
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UCHAR Cbeahr; // (0280) Cobra-bus2 Error address high register
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UCHAR Cbresv; // (02a0) Cobra-bus2 reserve register
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UCHAR Alr; // (02c0) Address lock register
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UCHAR Pmbr; // (02e0) Processor Mailbox register
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UCHAR Iirr; // (0300) Interprocessor interrupt request register
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UCHAR Sicr; // (0320) System interrupt clear register
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UCHAR Mresv; // (0340) Miscellaneous reserve register
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UCHAR Pmr1; // (0360) Performance Register 1
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UCHAR Pmr2; // (0380) Performance Register 2
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UCHAR Pmr3; // (03a0) Performance Register 3
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UCHAR Pmr4; // (03c0) Performance Register 4
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UCHAR Pmr5; // (03e0) Performance Register 5
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} RATTLER_CPU_CSRS, *PRATTLER_CPU_CSRS;
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//
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// Define the Rattler Configuration Register
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//
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typedef union _RATTLER_CONFIG_CSR{
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struct{
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ULONG RevisionNumber: 4; // (0-3)
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ULONG Reserved0: 8; // (4-11)
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ULONG EnableBusSizing0: 1; // (12)
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ULONG Reserved1: 7; // (13-19)
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ULONG EnableExchangeDly0: 1; // (20)
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ULONG Reserved2: 3; // (21-23)
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ULONG DisableIdleBcCsStall0: 1; // (24)
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ULONG Enable4IdleBc0: 1; // (25)
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ULONG AckMb0: 1; // (26)
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ULONG AckSetDirty0: 1; // (27)
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ULONG CacheSize0: 3; // (28-30)
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ULONG Reserved3: 1; // (31)
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ULONG RevisionNumber2: 4; // (32-35)
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ULONG EnableSystemInterrupts: 4; // (36-39)
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ULONG EnableIoInterrupts: 2; // (40-41)
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ULONG EnableAlternateIoInts: 2; // (42-43)
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ULONG EnableBusSizing1: 1; // (44)
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ULONG Reserved4: 7; // (45-51)
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ULONG EnableExchangeDly1: 1; // (52)
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ULONG Reserved5: 3; // (53-55)
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ULONG DisableIdleBcCsStall1: 1; // (56)
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ULONG Enable4IdleBc1: 1; // (57)
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ULONG AckMb1: 1; // (58)
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ULONG AckSetDirty1: 1; // (59)
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ULONG CacheSize1: 3; // (60-62)
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ULONG Reserved6: 1; // (63)
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};
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ULONGLONG all;
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} RATTLER_CONFIG_CSR, *PRATTLER_CONFIG_CSR;
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//
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// Define the Rattler Error Summary register:
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//
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typedef union _RATTLER_ESREG_CSR{
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struct{
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ULONG EvbCorrErr0: 3; //
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ULONG Reserved0: 1; //
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ULONG EvbFatalErr0: 4; //
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ULONG DtErr0: 2; //
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ULONG DtSummary0: 1; //
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ULONG Reserved1: 1; //
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ULONG IbParErr0: 1; //
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ULONG IbErrInfo0: 2; //
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ULONG IbSummary0: 1; //
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ULONG CbErr0: 8; //
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ULONG CbSummary0: 1; //
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ULONG CbCmdr0: 1; //
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ULONG Reserved2: 2; //
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ULONG EvNoResponse0: 1; //
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ULONG Reserved3: 3; //
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ULONG EvbCorrErr1: 3; //
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ULONG EvbCorrErrInt1: 1; //
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ULONG EvbFatalErr1: 4; //
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ULONG DtErr1: 2; //
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ULONG DtSummary1: 1; //
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ULONG Reserved4: 1; //
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ULONG IbParErr1: 1; //
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ULONG IbErrInfo1: 2; //
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ULONG IbSummary1: 1; //
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ULONG CbErr1: 4; //
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ULONG Reserved5: 4; //
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ULONG CbSummary1: 1; //
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ULONG CbCmdr1: 1; //
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ULONG Reserved6: 2; //
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ULONG EvNoResponse1: 1; //
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ULONG EvSysFail: 1; //
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ULONG Reserved7: 2; //
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};
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ULONGLONG all;
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} RATTLER_ESREG_CSR, *PRATTLER_ESREG_CSR;
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//
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// Define the Cobra-bus2 Control Register:
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//
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typedef union _RATTLER_CBCR_CSR{
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struct{
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ULONG EnableParityChecking0: 1; // Enable CBUS parity checking
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ULONG DataWrongParity0: 1; // Force bad data parity on bus
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ULONG CAWrongParity0: 1; // Force bad command/addr parity
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ULONG Reserved0: 1; //
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ULONG ForceShared: 1; // force shared bus status
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ULONG Reserved1: 7; //
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ULONG EnableCbusErrInt0: 1; // Enable Rattler error interrupt
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ULONG Reserved2: 19; //
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ULONG EnableParityChecking1: 1; // Rattler-D parity checking enable
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ULONG DataWrongParity1: 1; // Force bad data parity (Rattler-D)
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ULONG CAWrongParity1: 1; // bad command/addr parity (D)
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ULONG Reserved3: 5; //
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ULONG CommanderID: 3; // CPU Commander ID
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ULONG Reserved4: 1; //
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ULONG EnableCbusErrInt1: 1; // Enable Rattler-D error interrupt
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ULONG Reserved5: 19; //
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};
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ULONGLONG all;
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} RATTLER_CBCR_CSR, *PRATTLER_CBCR_CSR;
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//
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// Define the Interprocessor Interrupt Request Register.
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//
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typedef union _RATTLER_IPIR_CSR{
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struct{
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ULONGLONG Reserved0: 44;
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ULONGLONG RequestNodeHaltInterrupt: 1;
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ULONGLONG Reserved1: 3;
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ULONGLONG RequestInterrupt: 1;
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ULONGLONG Reserved2: 15;
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};
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ULONGLONG all;
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} RATTLER_IPIR_CSR, *PRATTLER_IPIR_CSR;
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//
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// Define the System Interrupt Clear Register format.
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//
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typedef union _RATTLER_SIC_CSR{
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struct{
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ULONG SystemBusErrorInterruptClear0: 1; // (0)
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ULONG Reserved0: 31; // (1-31)
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ULONG SystemBusErrorInterruptClear1: 1; // (32)
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ULONG Reserved1: 3; // (33-35)
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ULONG IntervalTimerInterrupt: 1; // (36)
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ULONG Reserved2: 3; // (37-39)
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ULONG SystemEventClear: 1; // (40)
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ULONG Reserved3: 3; // (41-43)
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ULONG NodeHaltInterruptClear: 1; // (44)
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ULONG Reserved4: 3; // (45-47)
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ULONG InterprocessorInterruptClear: 1; // (48)
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ULONG Reserved5: 3; // (49-51)
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ULONG IOInterruptIRQ: 2; // (52-53)
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ULONG Reserved6: 10; // (54-63)
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};
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ULONGLONG all;
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} RATTLER_SIC_CSR, *PRATTLER_SIC_CSR;
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#endif // _RATTLERH_
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