309 lines
7.4 KiB
C
309 lines
7.4 KiB
C
/*++
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Copyright (C) 1992 NCR Corporation
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Module Name:
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ncrcat.h
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Author:
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Abstract:
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System equates for dealing with the NCR Cat Bus.
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++*/
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#ifndef _NCRCAT_
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#define _NCRCAT_
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/*
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* Cat bus driver error codes
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*/
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#define CATNOERR 0
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#define CATIO 1 /* I/O error */
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#define CATFAULT 2 /* Bad address */
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#define CATACCESS 3 /* Permission denied */
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#define CATINVAL 4 /* Invalid argument */
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#define CATNOMOD 5 /* Module not found */
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#define CATNOASIC 6 /* Asic not found */
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/*
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* CAT Bus Driver Commands
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*/
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#define READ_REGISTER 1 /* Read a register */
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#define WRITE_REGISTER 2 /* Write a register */
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#define READ_SUBADDR 3 /* Read from the subaddress area */
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#define WRITE_SUBADDR 4 /* Write to the subaddress area */
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/*
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* Modules and ASICs for the Level 5
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*/
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#define PROCESSOR0 0x10 /* Processor Module 0 */
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#define PROCESSOR1 0x11 /* Processor Module 1 */
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#define PROCESSOR2 0x12 /* Processor Module 2 */
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#define PROCESSOR3 0x13 /* Processor Module 3 */
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#define NoModule0 0x1b /* No Module address */
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#define PROCESSOR4 0x1c /* Processor Module 4 */
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#define PROCESSOR5 0x1d /* Processor Module 5 */
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#define PROCESSOR6 0x1e /* Processor Module 6 */
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#define PROCESSOR7 0x1f /* Processor Module 7 */
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#define QUAD_BBID 1
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#define QUAD_LL2_AID 2
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#define QUAD_LL2_BID 3
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#define QUAD_BB0 (QUAD_BBID<<5|PROCESSOR0)
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#define QUAD_BB1 (QUAD_BBID<<5|PROCESSOR1)
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#define QUAD_BB2 (QUAD_BBID<<5|PROCESSOR2)
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#define QUAD_BB3 (QUAD_BBID<<5|PROCESSOR3)
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#define QUAD_BB4 (QUAD_BBID<<5|PROCESSOR4)
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#define QUAD_BB5 (QUAD_BBID<<5|PROCESSOR5)
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#define QUAD_BB6 (QUAD_BBID<<5|PROCESSOR6)
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#define QUAD_BB7 (QUAD_BBID<<5|PROCESSOR7)
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#define QUAD_LL2_A0 (QUAD_LL2_AID<<5|PROCESSOR0)
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#define QUAD_LL2_A1 (QUAD_LL2_AID<<5|PROCESSOR1)
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#define QUAD_LL2_A2 (QUAD_LL2_AID<<5|PROCESSOR2)
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#define QUAD_LL2_A3 (QUAD_LL2_AID<<5|PROCESSOR3)
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#define QUAD_LL2_A4 (QUAD_LL2_AID<<5|PROCESSOR4)
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#define QUAD_LL2_A5 (QUAD_LL2_AID<<5|PROCESSOR5)
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#define QUAD_LL2_A6 (QUAD_LL2_AID<<5|PROCESSOR6)
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#define QUAD_LL2_A7 (QUAD_LL2_AID<<5|PROCESSOR7)
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#define QUAD_LL2_B0 (QUAD_LL2_BID<<5|PROCESSOR0)
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#define QUAD_LL2_B1 (QUAD_LL2_BID<<5|PROCESSOR1)
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#define QUAD_LL2_B2 (QUAD_LL2_BID<<5|PROCESSOR2)
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#define QUAD_LL2_B3 (QUAD_LL2_BID<<5|PROCESSOR3)
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#define QUAD_LL2_B4 (QUAD_LL2_BID<<5|PROCESSOR4)
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#define QUAD_LL2_B5 (QUAD_LL2_BID<<5|PROCESSOR5)
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#define QUAD_LL2_B6 (QUAD_LL2_BID<<5|PROCESSOR6)
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#define QUAD_LL2_B7 (QUAD_LL2_BID<<5|PROCESSOR7)
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#define CATbaseModule(id) ((id)&0x1f)
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#define CATsubModule(id) ((id)>>5)
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#define MEMORY0 0x14 /* Memory Module 0 */
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#define MEMORY1 0x15 /* Memory Module 1 */
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#define PRIMARYMC 0x18 /* Primary Micro Channel */
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#define SECONDARYMC 0x19 /* Secondary Micro Channel */
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#define PSI 0x1A /* Power Supply Interface Module */
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#define CAT_LPB_MODULE 0x00 /* Local Peripheral Board - non CAT */
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#define CAT_I 0x00 /* Configure and Test Interface ASIC; Always */
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/* ASIC 0 on every module */
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#define NUM_PROCESSOR_CARDS 4
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#define NUM_MEMORY_CARDS 2
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#define NUM_MC_SLOTS 8
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#define NUM_MC_BUSES 2
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/*
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* CAT_I is the only ASIC on the Processor Module
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*/
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/*
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* ASIC IDs for the Memory Module
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*/
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#define MMC1 1 /* Magellan Memory Controller 1 ASIC */
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#define MMA1 2 /* Magellan Memory Address 1 ASIC */
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#define MMD1_0 3 /* Magellan Memeory Data 1 Slice 0 */
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#define MMD1_1 4 /* Magellan Memeory Data 1 Slice 1 */
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#define MMD1_2 5 /* Magellan Memeory Data 1 Slice 2 */
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#define MMD1_3 6 /* Magellan Memeory Data 1 Slice 3 */
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/*
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* ASIC IDs for the Primary Micro Channel
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*/
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#define PMC_MCADDR 1 /* Micro Channel Address/Controller */
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#define PMC_DMA 2 /* DMA Controller */
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#define PMC_DS1 3 /* Memory Controller Data Slice 1 */
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#define PMC_DS0 4 /* Memory Controller Data Slice 0 */
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#define PMC_VIC 5 /* Voyager Interrupt Controller ASIC */
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#define PMC_ARB 6 /* Dual System Bus Arbiter ASIC */
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#define PMC_DS2 7 /* Memory Controller Data Slice 2 */
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#define PMC_DS3 8 /* Memory Controller Data Slice 3 */
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/*
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* ASIC IDs for the Secondary Micro Channel
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*/
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/*
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* SMC ASIC ID's listed in scan path order
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*/
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#define SMC_MCADDR 1 /* Micro Channel Address/Controller */
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#define SMC_DS1 3 /* Memory Controller Data Slice 1 */
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#define SMC_DS0 4 /* Memory Controller Data Slice 0 */
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#define SMC_DMA 2 /* DMA Controller */
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#define SMC_DS2 7 /* Memory Controller Data Slice 2 */
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#define SMC_DS3 8 /* Memory Controller Data Slice 3 */
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/*
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* common CATI registers
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*/
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typedef struct _CAT_REGISTERS {
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UCHAR Config0; /* CAT id */
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UCHAR Config1; /* CAT device info */
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UCHAR Control2; /* CAT control bits */
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UCHAR Config3; /* subaddress read/write */
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UCHAR Config4; /* user defined configuration */
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UCHAR Config5; /* user defined configuration */
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UCHAR SubAddress6; /* low byte */
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UCHAR SubAddress7; /* high byte */
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UCHAR Config8; /* user defined configuration */
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UCHAR Config9; /* user defined configuration */
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UCHAR ConfigA; /* user defined configuration */
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UCHAR ConfigB; /* user defined configuration */
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UCHAR ConfigC; /* user defined configuration */
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UCHAR ConfigD; /* user defined configuration */
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UCHAR ConfigE; /* user defined configuration */
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UCHAR StatusF; /* CAT status bits */
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} CAT_REGISTERS, *PCAT_REGISTERS;
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/*
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* Processor Asic
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*/
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#define PBC_Status 0x0F
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/* ASIC ID's for the Processor Module */
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#define A_PBC 1
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#define B_PBC 2
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/* ASIC ID's for the Quad Baseboard (QBB) */
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#define QDATA1 1
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#define QDATA0 2
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#define QABC 3
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/* ASIC ID's for the Large Level 2 Cache Submodule (LL2) */
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#define QCC0 4
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#define QCC1 5
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#define QCD0 6
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#define QCD1 7
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/*
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* Micro Channel I/F Address/Contrlo (MCADDR) ASICs
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*/
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#define MCADDR 0xC0
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/*
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* Micro Channel Interface Data Slice (MCDATA) ASICs; One for each System Bus
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*/
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#define MCDATA_A 0xC4 /* MCDATA for bus A */
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#define MCDATA_B 0xC5 /* MCDATA for bus B */
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/*
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* System Bus Arbiter (SBA) ASIC
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*/
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#define SBA 0xC1
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/*
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* Voyager Interrupt Controller (VIC) ASIC
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*/
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#define VIC 0xC8
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/*
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* DMA Controller (DMA) ASIC
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*/
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#define DMA 0xC9
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/*
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* COUGAR ASIC
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*/
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#define COUGAR 0xE0
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/*
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* LPB EEPROM Address
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*/
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#define LPB_EEPROM_ADDRESS 0xFFF5E000 /* LPB EEPROM */
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typedef struct _CAT_CONTROL {
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UCHAR Module; // Module ID
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UCHAR Asic; // ASIC ID
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UCHAR Command; // CAT bus driver command
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USHORT Address; // Register or Sub address
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USHORT NumberOfBytes; // Number of bytes to read/write
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} CAT_CONTROL, *PCAT_CONTROL;
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//
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// Micro Channel slot information
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//
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#define NUM_POS_REGISTERS 8
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#define POS_Setup 0x96
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#define POS_Slot0 0x78 /* select slot 0 */
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//
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// POS Space Definitions
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//
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#define POS_0 0x100
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#define POS_1 0x101
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#define POS_2 0x102
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#define POS_3 0x103
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#define POS_4 0x104
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#define POS_5 0x105
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#define POS_6 0x106
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#define POS_7 0x107
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/*
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* Cat bus driver function prototypes.
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*/
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BOOLEAN
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HalCatBusAvailable (
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);
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LONG
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HalCatBusIo (
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IN PCAT_CONTROL CatControl,
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IN OUT PUCHAR Buffer
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);
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VOID
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HalCatBusReset (
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);
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LONG
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HalpCatBusIo (
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IN PCAT_CONTROL CatControl,
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IN OUT PUCHAR Buffer
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);
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VOID
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HalPowerOffSystem (
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IN BOOLEAN PowerOffSystem
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);
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#endif // _NCRCAT_
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