495 lines
14 KiB
C
495 lines
14 KiB
C
/*++
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Copyright (C) 1992 NCR Corporation
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Module Name:
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ncrmem.h
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Author:
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Abstract:
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System equates for dealing with the NCR Memory boads.
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++*/
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#ifndef _NCRMEM_
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#define _NCRMEM_
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/*
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* Memory module
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*/
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#define NUM_MEMORY_CARDS_L5 2
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#define NUM_MMC_PER_CARD 1
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#define NUM_MMA_PER_CARD 1
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#define NUM_MMD_PER_CARD 4
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#define NUM_POSSIBLE_SIMMS 48
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#define EDC_FIELD (32+7)
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#define INTERLEAVES_PER_BOARD 2
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#define MAX_BANKS 2
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/* defines for union referencing */
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#define CONFIG0 CatRegisters.CatRegs.Config0
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#define CONFIG1 CatRegisters.CatRegs.Config1
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#define CONTROL2 CatRegisters.CatRegs.Control2
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#define CONFIG3 CatRegisters.CatRegs.Config3
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#define CONFIG4 CatRegisters.CatRegs.Config4
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#define CONFIG5 CatRegisters.CatRegs.Config5
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#define SUBADDRESS6 CatRegisters.CatRegs.SubAddress6
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#define SUBADDRESS7 CatRegisters.CatRegs.SubAddress7
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#define CONFIG8 CatRegisters.CatRegs.Config8
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#define CONFIG9 CatRegisters.CatRegs.Config9
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#define CONFIGA CatRegisters.CatRegs.ConfigA
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#define CONFIGB CatRegisters.CatRegs.ConfigB
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#define CONFIGC CatRegisters.CatRegs.ConfigC
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#define CONFIGD CatRegisters.CatRegs.ConfigD
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#define CONFIGE CatRegisters.CatRegs.ConfigE
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#define StatusF CatRegisters.CatRegs.StatusF
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/*
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*
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* Description : Config registers for the Magellan Memory Address 1 ASIC.
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*/
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/* Main CAT registers */
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#define MMA1_Config 0x00
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# define MMA1_128bit 0x01
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# define MMA1_I0TwoBanks 0x10
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# define MMA1_I1TwoBanks 0x20
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#define MMA1_ParityTest 0x01
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# define MMA1_ParB3 0x80
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# define MMA1_ParB2 0x40
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# define MMA1_ParB1 0x20
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# define MMA1_ParB0 0x10
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# define MMA1_ParA3 0x08
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# define MMA1_ParA2 0x04
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# define MMA1_ParA1 0x02
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# define MMA1_ParA0 0x01
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#define MMA1_Byte_A_Error 0x0d /* Byte in Error Register */
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#define MMA1_Byte_B_Error 0x0e /* Byte in Error Register */
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# define MMA1_Prty_Byte3 0x08 /* Parity error in byte 3 */
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# define MMA1_Prty_Byte2 0x04 /* Parity error in byte 2 */
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# define MMA1_Prty_Byte1 0x02 /* Parity error in byte 1 */
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# define MMA1_Prty_Byte0 0x01 /* Parity error in byte 0 */
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#define MMA1_Subport_Data 0x03
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#define MMA1_Subport_Addr 0x06
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/* addr0 decodes MMA */
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#define MEM 0x02
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#define MOP 0x01
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#define ADDR_MASK 0xfffffff8 /* lowest 3 bits are not valid */
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#define BYTE0 0x01
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#define BYTE1 0x02
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#define BYTE2 0x04
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#define BYTE3 0x08
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#define BANK1 0x10 /* bit 4 of interleave error address */
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/* macros */
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#define MEM_BIT(_x) ( (((_x) & MEM) == MEM) ? 0x1 : 0x0 )
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#define MOP_BIT(_x) ( (((_x) & MOP) == MOP) ? 0x1 : 0x0 )
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/* Subaddress CAT Extension registers */
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#define MMA1_Sub_Start 0x00 /* First sub address extension regs */
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#define MMA1_Sub_Size 32 /* The number of subaddress extension regs */
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#define MMA1_BusB_Sub_Start 0x10 /* First Bus B register */
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#define MMA1_Bus_Sub_Size 0x0C /* Size of Bus specific registers */
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#define MMA1_Interleave_0_Start 0x0D /* First Byte of Interleave 0 */
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#define MMA1_Interleave_1_Start 0x1C /* First Byte of Interleave 1 */
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#define MMA1_Interleave_Size 0x04 /* Size of Interleave registers */
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//
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// (ts) 2/24/95 Changes for Disco Memory Support
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//
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#define DMAC1_Sub_Start (MMA1_Sub_Start+MMA_SubAddress)
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#define DMAC1_BusB_Sub_Start (MMA1_BusB_Sub_Start+MMA_SubAddress)
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#define DMAC1_Interleave_0_Start (MMA1_Interleave_0_Start+MMA_SubAddress)
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#define DMAC1_Interleave_1_Start (MMA1_Interleave_Size+MMA_SubAddress)
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/* For the DMAC1 the MMA1 direct address registers are at 0x40 - 0x4f
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* For the DMAC1 the MMA1 subaddress registers are at 0x20 - 0x3f
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*/
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#define MMA_Direct 0x40
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#define MMA_SubAddress 0x20
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typedef struct _MMA1_INFO {
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ULONG JtagId;
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UCHAR Flag;
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union {
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CAT_REGISTERS CatRegs;
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struct {
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UCHAR Dummy0;
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UCHAR ParityTest;
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UCHAR Dummy2;
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UCHAR Dummy3;
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UCHAR InterleaveLA0;
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UCHAR InterleaveLA1;
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UCHAR Dummy6;
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UCHAR IoStartAddress;
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UCHAR Dummy8;
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UCHAR IoEndAddress;
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UCHAR I1StartAddress;
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UCHAR DummyB;
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UCHAR I1EndAddress;
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UCHAR ErrorByteA;
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UCHAR ErrorByteB;
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UCHAR DummyF;
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} MmaRegisters;
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} CatRegisters;
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UCHAR LastBusAAddressError0; /* for PAR_INT diagnosis */
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UCHAR LastBusAAddressError1; /* for PAR_INT diagnosis */
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UCHAR LastBusAAddressError2; /* for PAR_INT diagnosis */
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UCHAR LastBusAAddressError3; /* for PAR_INT diagnosis */
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UCHAR GoodBusAAddressError0; /* for PAR_INT diagnosis */
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UCHAR GoodBusAAddressError1; /* for PAR_INT diagnosis */
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UCHAR GoodBusAAddressError2; /* for PAR_INT diagnosis */
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UCHAR GoodBusAAddressError3; /* for PAR_INT diagnosis */
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UCHAR BusAErrorAddress0; /* for ERROR_L diagnosis */
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UCHAR BusAErrorAddress1; /* for ERROR_L diagnosis */
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UCHAR BusAErrorAddress2; /* for ERROR_L diagnosis */
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UCHAR BusAErrorAddress3; /* for ERROR_L diagnosis */
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UCHAR Interleave0Error0;
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UCHAR Interleave0Error1;
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UCHAR Interleave0Error2;
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UCHAR Interleave0Error3;
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UCHAR LastBusBAddressError0; /* for PAR_INT diagnosis */
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UCHAR LastBusBAddressError1; /* for PAR_INT diagnosis */
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UCHAR LastBusBAddressError2; /* for PAR_INT diagnosis */
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UCHAR LastBusBAddressError3; /* for PAR_INT diagnosis */
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UCHAR GoodBusBAddressError0; /* for PAR_INT diagnosis */
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UCHAR GoodBusBAddressError1; /* for PAR_INT diagnosis */
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UCHAR GoodBusBAddressError2; /* for PAR_INT diagnosis */
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UCHAR GoodBusBAddressError3; /* for PAR_INT diagnosis */
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UCHAR BusBErrorAddress0; /* for ERROR_L diagnosis */
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UCHAR BusBErrorAddress1; /* for ERROR_L diagnosis */
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UCHAR BusBErrorAddress2; /* for ERROR_L diagnosis */
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UCHAR BusBErrorAddress3; /* for ERROR_L diagnosis */
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UCHAR Interleave1Error0;
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UCHAR Interleave1Error1;
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UCHAR Interleave1Error2;
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UCHAR Interleave1Error3;
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UCHAR FirstError[2]; /* new for DMAC1 */
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UCHAR SecondError[2]; /* new for DMAC1 */
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UCHAR DisconnectGroups[2]; /* new for DMAC1 */
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UCHAR BusyIndication[2]; /* new for DMAC1 */
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} MMA1_INFO, *PMMA1_INFO;
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/* defines for union referencing */
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#define BYTE_ERROR_A CatRegisters.MmaRegisters.ErrorByteA
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#define BYTE_ERROR_B CatRegisters.MmaRegisters.ErrorByteB
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/*
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*
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* Description : Config registers for the Magellan Memory Data 1 ASIC.
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*
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*/
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/* Main CAT registers */
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#define MMC1_Subport_Data 0x03
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#define MMC1_Subport_Addr 0x06
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#define MMC1_Parity_Status_A 0x00
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#define MMC1_Parity_Status_B 0x10
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# define MMC1_Addr_Parity_Err 0x02
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# define MMC1_Data_Parity_Err 0x01
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#define MMC1_Config1 0x08
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# define MMC1_SBErr_DetectDisable 0x04
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# define MMC1_LBEDIS_DetectDisable 0x40
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/* Subaddress space */
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#define MMC1_Inter_0_Status 0x09
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#define MMC1_Inter_1_Status 0x19
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# define MMC1_Clear_Interleave 0x01
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#define MMC1_Interleave_0_Info_0 0x0A
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#define MMC1_Interleave_1_Info_0 0x1A
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# define MMC1_BusA_Cpu0 0x01
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# define MMC1_BusA_Cpu1 0x02
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# define MMC1_BusA_Cpu2 0x04
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# define MMC1_BusA_Cpu3 0x08
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# define MMC1_BusB_Cpu0 0x10
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# define MMC1_BusB_Cpu1 0x20
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# define MMC1_BusB_Cpu2 0x40
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# define MMC1_BusB_Cpu3 0x80
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#define MMC1_Interleave_0_Info_1 0x0B
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#define MMC1_Interleave_1_Info_1 0x1B
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#define MMC1_Intr0_Single_Bit_Status 0x0D
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#define MMC1_Intr1_Single_Bit_Status 0x1D
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# define MMC1_SBerr 0x01
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# define MMC1_SB_LPE_0 0x02
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# define MMC1_SB_LPE_1 0x04
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# define MMC1_SB_LPE_2 0x08
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# define MMC1_SB_ErrInt 0x40
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# define MMC1_ErrStore 0x80
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#define MMC1_Intr0_Single_Bit_Info_0 0x0E
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#define MMC1_Intr0_Single_Bit_Info_1 0x0F
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#define MMC1_Intr1_Single_Bit_Info_0 0x1E
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#define MMC1_Intr1_Single_Bit_Info_1 0x1F
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/* Subaddress CAT Extension registers */
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#define MMC1_Sub_Start 0x00 /* First sub address extension regs */
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#define MMC1_Sub_Size 32 /* The number of subaddress extension regs */
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#define MMC1_BusB_Sub_Start 0x10 /* First sub address for Bus B */
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#define MMC1_Bus_Sub_Size 0x09 /* Size of sub address for Bus */
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#define MMC1_Interleave_0_Start 0x09 /* First sub address for Interleave 0 */
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#define MMC1_Interleave_1_Start 0x19 /* First sub address for Interleave 1 */
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#define MMC1_Interleave_Size 0x07 /* Size of interleave space */
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/* Error interrupt status MMC */
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#define MBIT 0x01
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#define MOWN 0x02
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#define ILV_LOCK 0x04
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#define LBE 0x40
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#define LPE_MASK 0x38
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#define LPE_SHIFT 3
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#define ERR_STORE 0x80
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#define LPE_BITS(_x) ( (int)((_x) & LPE_MASK) >> LPE_SHIFT )
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/* Interrupt info 0 */
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#define SB_ID_MASK 0xf0
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#define SB_ID_SHIFT 4
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#define SA_ID_MASK 0x0f
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/* Interrupt info 1 */
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#define LST8 0x01
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#define LST8_SHIFT 8
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#define SA_MID 0x02
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#define SB_MID 0x04
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#define E_AP256 0x08
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#define E_BOP_MASK 0xf0
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/* error status */
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#define CO_ERR 0x10
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#define CO_DPE 0x08
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#define LK_LPE 0x04
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#define ERROR_L_MASK (CO_ERR | CO_DPE | LK_LPE | MOWN | MBIT)
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/* last_control_X0 decodes MMC */
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#define MID 0x10
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#define ID_MASK 0x0f
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#define MACK_MASK 0x60
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#define MACK_SHIFT 5
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/* last_control_X1 decodes MMC */
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#define LOCKG 0x80
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#define LOCKL 0x40
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#define MIC 0x20
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#define AP256 0x10
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#define BOP_MASK 0x0f
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/* macros */
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#define MIC_BIT(_x) ( (((_x) & MIC) == MIC) ? 0x1 : 0x0 )
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#define MACK_BITS(_x) ( (int)((_x) & MACK_MASK) >> MACK_SHIFT )
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typedef struct _MMC1_INFO {
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ULONG JtagId;
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UCHAR Flag;
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union {
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CAT_REGISTERS CatRegs;
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struct {
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UCHAR Dummy0;
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UCHAR Dummy1;
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UCHAR Dummy2;
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UCHAR Dummy3;
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UCHAR Dummy4;
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UCHAR Dummy5;
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UCHAR Dummy6;
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UCHAR Dummy7;
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UCHAR Mode1;
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UCHAR ActiveProcessors;
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UCHAR Mode2;
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UCHAR RefreshCount;
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UCHAR RASActiveCount;
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UCHAR DummyD;
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UCHAR DummyE;
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UCHAR DummyF;
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} MmcRegisters;
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} CatRegisters;
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UCHAR ParityInterruptAStatus; /* MEM module detectd parity */
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UCHAR LastControlA0; /* for PAR_INT diagnosis */
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UCHAR LastControlA1; /* for PAR_INT diagnosis */
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UCHAR GoodControlA0; /* for PAR_INT diagnosis */
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UCHAR GoodControlA1; /* for PAR_INT diagnosis */
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UCHAR ErrorAStatus; /* MEM module generated ERROR_L */
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UCHAR ErrorA0; /* for ERROR_L diagnosis */
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UCHAR ErrorA1; /* for ERROR_L diagnosis */
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UCHAR ErrorAId; /* MIC timeout ERROR_L */
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UCHAR Interleave0Status;
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UCHAR Interleave0Info0;
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UCHAR Interleave0Info1;
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UCHAR Interleave0Lst;
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UCHAR SingleInterruptI0Status;
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UCHAR SingleInterruptI00;
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UCHAR SingleInterruptI01;
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UCHAR ParityInterruptBStatus; /* MEM module detectd parity */
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UCHAR LastControlB0; /* for PAR_INT diagnosis */
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UCHAR LastControlB1; /* for PAR_INT diagnosis */
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UCHAR GoodControlB0; /* for PAR_INT diagnosis */
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UCHAR GoodControlB1; /* for PAR_INT diagnosis */
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UCHAR ErrorBStatus; /* MEM module generated ERROR_L */
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UCHAR ErrorB0; /* for ERROR_L diagnosis */
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UCHAR ErrorB1; /* for ERROR_L diagnosis */
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UCHAR ErrorBId; /* MIC timeout ERROR_L */
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UCHAR Interleave1Status;
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UCHAR Interleave1Info0;
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UCHAR Interleave1Info1;
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UCHAR Interleave1Lst;
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UCHAR SingleInterruptI1Status;
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UCHAR SingleInterruptI10;
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UCHAR SingleInterruptI11;
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//
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// (ts) 2/24/95 Changes for Disco Memory Support
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//
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UCHAR FirstError[2]; /* new for DMAC1 */
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UCHAR SecondError[2]; /* new for DMAC1 */
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UCHAR DisconnectGroups[2]; /* new for DMAC1 */
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UCHAR BusyIndication[2]; /* new for DMAC1 */
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} MMC1_INFO, *PMMC1_INFO;
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/*
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* Description : Config registers for the Magellan Memory Data 1 ASIC.
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*
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*/
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/* Main CAT registers */
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#define MMD1_TestMode 0x04
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# define MMD1_OddPar 0x20 /* gen parity error */
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#define MMD1_Interleave0_Error 0x3 /* Interleave error register */
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# define MMD1_Intro_Line0_Sbe 0x08 /* single bit error */
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# define MMD1_Intro_Line0_Mbe 0x04 /* multiple-bit error */
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# define MMD1_Intro_Line1_Sbe 0x02 /* single bit error */
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# define MMD1_Intro_Line1_Mbe 0x01 /* multiple-bit error */
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#define MMD1_Interleave1_Error 0x8 /* Interleave error register */
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# define MMD1_Intr1_Line0_Sbe 0x08 /* single bit error */
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# define MMD1_Intr1_Line0_Mbe 0x04 /* multiple-bit error */
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# define MMD1_Intr1_Line1_Sbe 0x02 /* single bit error */
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# define MMD1_Intr1_Line1_Mbe 0x01 /* multiple-bit error */
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#define ECCERROR 0x20
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#define DATAPERR 0x02
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#define PERR_BITS 0x03
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#define MERR_ML1 0x08
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#define SERR_ML1 0x04
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#define MERR_ML0 0x02
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#define SERR_ML0 0x01
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#define MMD1_ECC_DIAG 0x05 /* ECC Diagnostic register */
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#define MMD1_Syn_Diag_0 0x09 /* ECC Syndrome register */
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#define MMD1_Syn_Diag_1 0x0a /* ECC Syndrome register */
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#define MMD1_Syn_Diag_2 0x0b /* ECC Syndrome register */
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#define MMD1_Syn_Diag_3 0x0c /* ECC Syndrome register */
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# define MMD1_CHK_MASK 0x7f /* check bit mask */
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#define MMD1_Bus_B_Parity 0x0d /* bus B Parity error */
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#define MMD1_Bus_A_Parity 0x0e /* bus A Parity error */
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# define MMD1_High_Byte 0x02 /* bus parity on high byte */
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# define MMD1_Low_Byte 0x01 /* bus parity on low byte */
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#define MMD1_STATUS 0x0f
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# define MMD1_Cat_Stuff 0x09 /* cat bus stuff dont change */
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# define MMD1_EDC_Error 0x20 /* EDC error captured */
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# define MMD1_Data_Parity_Error 0x01 /* Data parity error captured */
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typedef struct _MMD1_INFO {
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UCHAR Flag;
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union {
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CAT_REGISTERS CatRegs;
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struct {
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UCHAR Dummy0;
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UCHAR Dummy1;
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UCHAR Dummy2;
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UCHAR I0EccStatus;
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UCHAR TestMode;
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UCHAR ECCDiag;
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UCHAR Dummy6;
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UCHAR Dummy7;
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UCHAR I1EccStatus;
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UCHAR SyndromeI0ML0;
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UCHAR SyndromeI0ML1;
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UCHAR SyndromeI1ML0;
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UCHAR SyndromeI1ML1;
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UCHAR ParityAStatus;
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UCHAR ParityBStatus;
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UCHAR Status;
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} MmdRegisters;
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} CatRegisters;
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} MMD1_INFO, *PMMD1_INFO;
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/* defines for union referencing */
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#define INTERLEAVE0_ERROR CatRegisters.MmdRegisters.I0ECCStatus
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#define INTERLEAVE1_ERROR CatRegisters.MmdRegisters.I1ECCStatus
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#define SYN_DIAG_0 CatRegisters.MmdRegisters.SyndromeI0Ml0
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#define SYN_DIAG_1 CatRegisters.MmdRegisters.SyndromeI0Ml1
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#define SYN_DIAG_2 CatRegisters.MmdRegisters.SyndromeI1Ml0
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#define SYN_DIAG_3 CatRegisters.MmdRegisters.SyndromeI1Ml1
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#define BUS_A_PARITY CatRegisters.MmdRegisters.ParityAStatus
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#define BUS_B_PARITY CatRegisters.MmdRegisters.ParityBStatus
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#define MMDSTATUS CatRegisters.MmdRegisters.Status
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typedef struct _FRU_LOCATION {
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UCHAR BusType;
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UCHAR BusNumber;
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UCHAR BusSlotNumber;
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} FRU_LOCATION, *PFRU_LOCATION;
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typedef struct _MEMORY_CARD_INFO {
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ULONG FruAsic;
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ULONG FruSimm;
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ULONG AsicConfidenceLevel;
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ULONG SimmConfidenceLevel;
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FRU_LOCATION Location;
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MMC1_INFO Mmc1Info;
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MMA1_INFO Mma1Info;
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MMD1_INFO Mmd1Info[NUM_MMD_PER_CARD];
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} MEMORY_CARD_INFO, *PMEMORY_CARD_INFO;
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#endif // _NCRMEM_
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