138 lines
4.3 KiB
C
138 lines
4.3 KiB
C
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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nondef.h
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Abstract:
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This module specifies platform-specific definitions for the
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Mustang/EB66 modules.
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Author:
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Joe Notarangelo 22-Oct-1993
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Revision History:
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--*/
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#ifndef _NONDEF_
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#define _NONDEF_
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#include "alpharef.h"
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#include "lca4.h"
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#include "isaaddr.h"
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#define NUMBER_ISA_SLOTS 5
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#define NUMBER_PCI_SLOTS 3
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// Highest Virtual local PCI Slot.
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// Changed RAA was 13 but this pushes the code over to b000000 i.e AD[24]
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#define PCI_MAX_LOCAL_DEVICE 12
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// Highest PCI interrupt vector is in PCI vector space
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#define PCI_MAX_INTERRUPT_VECTOR (MAXIMUM_PCI_VECTOR - PCI_VECTORS)
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#if !defined(_LANGUAGE_ASSEMBLY)
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//
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#define PCI_INTERRUPT_READ_QVA ((PUCHAR)HAL_MAKE_QVA(HalpLca4PciIoPhysical()) + 0x26)
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#define PCI_INTERRUPT_MASK_QVA ((PUCHAR)HAL_MAKE_QVA(HalpLca4PciIoPhysical()) + 0x26)
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#endif //!_LANGUAGE_ASSEMBLY
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//
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// Define the default processor frequency to be used before the actual
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// frequency can be determined.
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//
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#define DEFAULT_PROCESSOR_FREQUENCY_MHZ (166)
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//
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// PCI-E/ISA Bridge chip configuration space base is at physical address
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// 0x1e0000000. The equivalent QVA is:
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// ((0x1e0000000 + cache line offset) >> IO_BIT_SHIFT) | QVA_ENABLE
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//
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#define PCI_CONFIGURATION_BASE_QVA 0xaf000000
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#define PCI_SPARSE_IO_BASE_QVA 0xae000000
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#define PCI_CONFIG_CYCLE_TYPE_0 0x0 // Local PCI device
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#define PCI_ISA_BRIDGE_HEADER_OFFSET (0x00800000 >> IO_BIT_SHIFT) // AD[18]
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//#define PCI_ISA_BRIDGE_HEADER_OFFSET (0x00040000 >> IO_BIT_SHIFT) // AD[13]
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//
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// PCI-ISA Bridge Configuration register offsets.
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//
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#define PCI_VENDOR_ID (0x0000 >> IO_BIT_SHIFT)
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#define PCI_DEVICE_ID (0x0040 >> IO_BIT_SHIFT)
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#define PCI_COMMAND (0x0080 >> IO_BIT_SHIFT)
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#define PCI_DEVICE_STATUS (0x00c0 >> IO_BIT_SHIFT)
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#define PCI_REVISION (0x0100 >> IO_BIT_SHIFT)
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#define PCI_CONTROL (0x0800 >> IO_BIT_SHIFT)
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#define PCI_ARBITER_CONTROL (0x0820 >> IO_BIT_SHIFT)
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#define ISA_ADDR_DECODER_CONTROL (0x0900 >> IO_BIT_SHIFT)
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#define UTIL_BUS_CHIP_SELECT_ENAB_A (0x09c0 >> IO_BIT_SHIFT)
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#define UTIL_BUS_CHIP_SELECT_ENAB_B (0x09e0 >> IO_BIT_SHIFT)
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#define PIRQ0_ROUTE_CONTROL (0x0c00 >> IO_BIT_SHIFT)
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#define PIRQ1_ROUTE_CONTROL (0x0c20 >> IO_BIT_SHIFT)
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#define PIRQ2_ROUTE_CONTROL (0x0c40 >> IO_BIT_SHIFT)
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#define PIRQ3_ROUTE_CONTROL (0x0c60 >> IO_BIT_SHIFT)
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//
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// Values for enabling an IORQ route control setting.
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//
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#define PIRQX_ROUTE_IRQ3 0x03
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#define PIRQX_ROUTE_IRQ4 0x04
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#define PIRQX_ROUTE_IRQ5 0x05
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#define PIRQX_ROUTE_IRQ6 0x06
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#define PIRQX_ROUTE_IRQ7 0x07
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#define PIRQX_ROUTE_IRQ9 0x09
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#define PIRQX_ROUTE_IRQ10 0x0a
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#define PIRQX_ROUTE_IRQ11 0x0b
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#define PIRQX_ROUTE_IRQ12 0x0c
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#define PIRQX_ROUTE_IRQ14 0x0d
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#define PIRQX_ROUTE_IRQ15 0x0f
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#define PIRQX_ROUTE_ENABLE 0x00
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//
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// PCI-ISA Bridge Non-Configuration control register offsets.
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//
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#define SIO_II_EDGE_LEVEL_CONTROL_1 (0x9a00 >> IO_BIT_SHIFT)
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#define SIO_II_EDGE_LEVEL_CONTROL_2 (0x9a20 >> IO_BIT_SHIFT)
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//
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// SIO-II value for setting edge/level operation in the control words.
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//
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#define IRQ0_LEVEL_SENSITIVE 0x01
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#define IRQ1_LEVEL_SENSITIVE 0x02
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#define IRQ2_LEVEL_SENSITIVE 0x04
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#define IRQ3_LEVEL_SENSITIVE 0x08
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#define IRQ4_LEVEL_SENSITIVE 0x10
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#define IRQ5_LEVEL_SENSITIVE 0x20
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#define IRQ6_LEVEL_SENSITIVE 0x40
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#define IRQ7_LEVEL_SENSITIVE 0x80
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#define IRQ8_LEVEL_SENSITIVE 0x01
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#define IRQ9_LEVEL_SENSITIVE 0x02
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#define IRQ10_LEVEL_SENSITIVE 0x04
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#define IRQ11_LEVEL_SENSITIVE 0x08
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#define IRQ12_LEVEL_SENSITIVE 0x10
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#define IRQ13_LEVEL_SENSITIVE 0x20
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#define IRQ14_LEVEL_SENSITIVE 0x40
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#define IRQ15_LEVEL_SENSITIVE 0x80
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#define SIO_II_INIT_COMMAND_1 (0x0400 >> IO_BIT_SHIFT)
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#define SIO_II_INIT_COMMAND_2 (0x1400 >> IO_BIT_SHIFT)
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#endif // _NONDEF_
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