184 lines
4.0 KiB
ArmAsm
184 lines
4.0 KiB
ArmAsm
//
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//
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// Copyright (c) 1993 IBM Corporation
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//
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// Copyright (c) 1994 MOTOROLA, INC. All Rights Reserved. This file
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// contains copyrighted material. Use of this file is restricted
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// by the provisions of a Motorola Software License Agreement.
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//
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// Module Name:
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//
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// PXL2.S
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//
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// Abstract:
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//
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// This module implements the routines to size the L2 cache
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// on PowerStack based system.
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//
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// Author:
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//
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// Karl Rusnock (karl_rusnock@phx.mcd.mot.com)
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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// 08-Dec-95 kjr Created this file for MCG PowerStack 2 Systems.
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//
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#include "kxppc.h"
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#include "halppc.h"
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.extern HalpIoControlBase
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.set HID0, 1008
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//
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// L2 cache sizes:
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//
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.set L2_SIZE, 0x3 // Bits 1..0 (LE bit order)
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.set L2_1M, 0x2
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.set L2_512K, 0x0
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.set L2_256K, 0x1
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.set L2_LINE_SIZE, 32
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.set CacheSize, r.3 // Return value
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.set L2CONFIG, r.9
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.set ISA, r.10 // Pointer to ISA I/O space
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//***********************************************************************
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//
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// Synopsis:
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// ULONG HalpSizeL2(VOID)
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//
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// Purpose:
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// Sizes the L2 cache.
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//
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// Returns:
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// Size of L2 cache or zero if not installed.
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// Valid sizes are 256, 512, and 1024.
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//
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// Global Variables Referenced:
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// HalpIoControlBase
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//
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// NOTE: Interrupts are assumed to be disabled upon entry.
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//***********************************************************************
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LEAF_ENTRY(HalpSizeL2)
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//
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// Get ptr to Bridge I/O (ISA bus)
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//
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lwz ISA,[toc]HalpIoControlBase(r.toc) // Get base of ISA I/O
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lwz ISA,0(ISA)
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lbz r.0, 0x823(ISA) // Cache Configuration Register.
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andi. r.0, r.0, L2_SIZE // Isolate L2 size field
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cmpi 0,0, r.0, L2_SIZE // L2 Cache Not Present?
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li CacheSize, 0
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beq L2_Exit
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li CacheSize, 256
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cmpi 0,0,r.0, L2_256K
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beq L2_Exit
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li CacheSize, 512
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cmpi 0,0,r.0, L2_512K
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beq L2_Exit
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li CacheSize, 1024
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L2_Exit:
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//
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// r.3 = cache size in KB
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//
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LEAF_EXIT(HalpSizeL2)
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//***********************************************************************
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//
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// Synopsis:
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// VOID HalpFlushAndDisableL2(VOID)
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//
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// Purpose:
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// Assumes that the L2 is enabled and in WRITE-THROUGH mode.
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// The L2 is invalidated and disabled.
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//
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// Returns:
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// nothing
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//
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// Global Variables Referenced:
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// HalpIoControlBase
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//
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// NOTE: Interrupts are assumed to be disabled upon entry.
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//***********************************************************************
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LEAF_ENTRY(HalpFlushAndDisableL2)
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mfspr r.9, HID0 // Lock the Icache
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ori r.0, r.9, 0x2000
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mtspr HID0, r.0
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isync
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li r.3, 0xC0 // Bits controlling L2
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lwz ISA, [toc]HalpIoControlBase(r.toc) // Get base of ISA I/O
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lwz ISA, 0(ISA)
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lbz r.5, 0x81C(ISA) // Read System Control Register.
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andc r.5, r.5, r.3 // Set bits to disable L2.
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stb r.5, 0x814(ISA) // Invalidate L2 first.
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stb r.5, 0x81C(ISA) // Disable L2 second.
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stb r.5, 0x814(ISA) // Invalidate L2 again, to be safe.
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lbz r.5, 0x81C(ISA) // Synchronize with I/O.
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sync
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mtspr HID0, r.9 // Unlock the Icache
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LEAF_EXIT(HalpFlushAndDisableL2)
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//***********************************************************************
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//
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// Synopsis:
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// VOID HalpFlushAndEnableL2(VOID)
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//
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// Purpose:
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// Assumes that the L2 is Disabled.
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// The L2 is invalidated and enabled.
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//
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// Returns:
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// nothing
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//
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// Global Variables Referenced:
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// HalpIoControlBase
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//
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// NOTE: Interrupts are assumed to be disabled upon entry.
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//***********************************************************************
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LEAF_ENTRY(HalpFlushAndEnableL2)
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mfspr r.9, HID0 // Lock the Icache
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ori r.0, r.9, 0x2000
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mtspr HID0, r.0
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isync
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li r.3, 0xC0 // Bits controlling L2
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lwz ISA, [toc]HalpIoControlBase(r.toc) // Get base of ISA I/O
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lwz ISA, 0(ISA)
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lbz r.5, 0x81C(ISA) // Read System Control Register.
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or r.5, r.5, r.3 // Set bits to disable L2.
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stb r.5, 0x814(ISA) // Invalidate L2 first.
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stb r.5, 0x81C(ISA) // Enable L2 second.
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lbz r.5, 0x81C(ISA) // Synchronize with I/O.
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sync
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mtspr HID0, r.9 // Unlock the Icache
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LEAF_EXIT(HalpFlushAndEnableL2)
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