2290 lines
61 KiB
C
2290 lines
61 KiB
C
/*++
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Copyright (C) 1989-1995 Microsoft Corporation
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Module Name:
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pxpcibus.c
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Abstract:
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Get/Set bus data routines for the PCI bus
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Author:
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Ken Reneris (kenr) 14-June-1994
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Jim Wooldridge Port to PowerPC
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "pci.h"
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#include "pcip.h"
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#include "pxmemctl.h"
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#include "pxpcisup.h"
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extern WCHAR rgzMultiFunctionAdapter[];
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extern WCHAR rgzConfigurationData[];
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extern WCHAR rgzIdentifier[];
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extern WCHAR rgzPCIIdentifier[];
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extern ULONG HalpPciMaxSlots;
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typedef ULONG (*FncConfigIO) (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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typedef VOID (*FncSync) (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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typedef VOID (*FncReleaseSync) (
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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typedef struct _PCI_CONFIG_HANDLER {
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FncSync Synchronize;
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FncReleaseSync ReleaseSynchronzation;
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FncConfigIO ConfigRead[3];
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FncConfigIO ConfigWrite[3];
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} PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
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//
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// Prototypes
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//
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ULONG
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HalpGetPCIData (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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HalpSetPCIData (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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NTSTATUS
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HalpAssignPCISlotResources (
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PUNICODE_STRING RegistryPath,
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IN PUNICODE_STRING DriverClassName OPTIONAL,
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IN PDRIVER_OBJECT DriverObject,
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IN PDEVICE_OBJECT DeviceObject OPTIONAL,
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IN ULONG SlotNumber,
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IN OUT PCM_RESOURCE_LIST *AllocatedResources
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);
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VOID
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HalpInitializePciBus (
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VOID
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);
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BOOLEAN
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HalpIsValidPCIDevice (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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BOOLEAN
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HalpValidPCISlot (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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//-------------------------------------------------
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VOID HalpPCISynchronizeType1 (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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VOID HalpPCIReleaseSynchronzationType1 (
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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ULONG HalpPCIReadUlongType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUcharType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUshortType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUlongType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUcharType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUshortType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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VOID HalpPCISynchronizeType2 (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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VOID HalpPCIReleaseSynchronzationType2 (
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IN PBUS_HANDLER BusHandler,
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IN KIRQL Irql
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);
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ULONG HalpPCIReadUlongType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUcharType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUshortType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUlongType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUcharType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUshortType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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//
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// Globals
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//
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KSPIN_LOCK HalpPCIConfigLock;
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PCI_CONFIG_HANDLER PCIConfigHandler;
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PCI_CONFIG_HANDLER PCIConfigHandlerType1 = {
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HalpPCISynchronizeType1,
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HalpPCIReleaseSynchronzationType1,
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{
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HalpPCIReadUlongType1, // 0
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HalpPCIReadUcharType1, // 1
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HalpPCIReadUshortType1 // 2
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},
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{
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HalpPCIWriteUlongType1, // 0
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HalpPCIWriteUcharType1, // 1
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HalpPCIWriteUshortType1 // 2
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}
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};
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PCI_CONFIG_HANDLER PCIConfigHandlerType2 = {
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HalpPCISynchronizeType2,
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HalpPCIReleaseSynchronzationType2,
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{
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HalpPCIReadUlongType2, // 0
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HalpPCIReadUcharType2, // 1
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HalpPCIReadUshortType2 // 2
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},
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{
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HalpPCIWriteUlongType2, // 0
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HalpPCIWriteUcharType2, // 1
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HalpPCIWriteUshortType2 // 2
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}
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};
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UCHAR PCIDeref[4][4] = { {0,1,2,2},{1,1,1,1},{2,1,2,2},{1,1,1,1} };
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VOID
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HalpPCIConfig (
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IN PBUS_HANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length,
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IN FncConfigIO *ConfigIO
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);
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#if DBG
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#define DBGMSG(a) DbgPrint(a)
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VOID
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HalpTestPci (
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ULONG
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);
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#else
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#define DBGMSG(a)
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#endif
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(INIT,HalpInitializePciBus)
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#pragma alloc_text(INIT,HalpAllocateAndInitPciBusHandler)
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#pragma alloc_text(INIT,HalpIsValidPCIDevice)
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#pragma alloc_text(PAGE,HalpAssignPCISlotResources)
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#endif
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VOID
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HalpInitializePciBus (
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VOID
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)
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{
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PPCI_REGISTRY_INFO PCIRegInfo;
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UNICODE_STRING unicodeString, ConfigName, IdentName;
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OBJECT_ATTRIBUTES objectAttributes;
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HANDLE hMFunc, hBus;
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NTSTATUS status;
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UCHAR buffer [sizeof(PPCI_REGISTRY_INFO) + 99];
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PWSTR p;
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WCHAR wstr[8];
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ULONG i, d, junk, HwType;
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PBUS_HANDLER BusHandler;
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PCI_SLOT_NUMBER SlotNumber;
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PKEY_VALUE_FULL_INFORMATION ValueInfo;
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PCM_FULL_RESOURCE_DESCRIPTOR Desc;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR PDesc;
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//
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// Search the hardware description looking for any reported
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// PCI bus. The first ARC entry for a PCI bus will contain
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// the PCI_REGISTRY_INFO.
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RtlInitUnicodeString (&unicodeString, rgzMultiFunctionAdapter);
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InitializeObjectAttributes (
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&objectAttributes,
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&unicodeString,
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OBJ_CASE_INSENSITIVE,
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NULL, // handle
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NULL);
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status = ZwOpenKey (&hMFunc, KEY_READ, &objectAttributes);
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if (!NT_SUCCESS(status)) {
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return ;
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}
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unicodeString.Buffer = wstr;
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unicodeString.MaximumLength = sizeof (wstr);
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RtlInitUnicodeString (&ConfigName, rgzConfigurationData);
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RtlInitUnicodeString (&IdentName, rgzIdentifier);
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ValueInfo = (PKEY_VALUE_FULL_INFORMATION) buffer;
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for (i=0; TRUE; i++) {
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RtlIntegerToUnicodeString (i, 10, &unicodeString);
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InitializeObjectAttributes (
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&objectAttributes,
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&unicodeString,
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OBJ_CASE_INSENSITIVE,
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hMFunc,
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NULL);
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status = ZwOpenKey (&hBus, KEY_READ, &objectAttributes);
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if (!NT_SUCCESS(status)) {
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//
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// Out of Multifunction adapter entries...
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//
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ZwClose (hMFunc);
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return ;
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}
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//
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// Check the Indentifier to see if this is a PCI entry
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//
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status = ZwQueryValueKey (
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hBus,
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&IdentName,
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KeyValueFullInformation,
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ValueInfo,
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sizeof (buffer),
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&junk
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);
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if (!NT_SUCCESS (status)) {
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ZwClose (hBus);
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continue;
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}
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p = (PWSTR) ((PUCHAR) ValueInfo + ValueInfo->DataOffset);
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if (p[0] != L'P' || p[1] != L'C' || p[2] != L'I' || p[3] != 0) {
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ZwClose (hBus);
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continue;
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}
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//
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// The first PCI entry has the PCI_REGISTRY_INFO structure
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// attached to it.
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//
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status = ZwQueryValueKey (
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hBus,
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&ConfigName,
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KeyValueFullInformation,
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ValueInfo,
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sizeof (buffer),
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&junk
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);
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ZwClose (hBus);
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if (!NT_SUCCESS(status)) {
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continue ;
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}
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Desc = (PCM_FULL_RESOURCE_DESCRIPTOR) ((PUCHAR)
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ValueInfo + ValueInfo->DataOffset);
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PDesc = (PCM_PARTIAL_RESOURCE_DESCRIPTOR) ((PUCHAR)
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Desc->PartialResourceList.PartialDescriptors);
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if (PDesc->Type == CmResourceTypeDeviceSpecific) {
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// got it..
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PCIRegInfo = (PPCI_REGISTRY_INFO) (PDesc+1);
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break;
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}
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}
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//
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// Initialize spinlock for synchronizing access to PCI space
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//
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KeInitializeSpinLock (&HalpPCIConfigLock);
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//
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// PCIRegInfo describes the system's PCI support as indicated by the BIOS.
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//
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HwType = PCIRegInfo->HardwareMechanism & 0xf;
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#if 0
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//
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// Some AMI bioses claim machines are Type2 configuration when they
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// are really type1. If this is a Type2 with at least one bus,
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// try to verify it's not really a type1 bus
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//
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if (PCIRegInfo->NoBuses && HwType == 2) {
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//
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// Check each slot for a valid device. Which every style configuration
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// space shows a valid device first will be used
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//
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SlotNumber.u.bits.Reserved = 0;
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SlotNumber.u.bits.FunctionNumber = 0;
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for (d = 0; d < PCI_MAX_DEVICES; d++) {
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SlotNumber.u.bits.DeviceNumber = d;
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//
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// First try what the BIOS claims - type 2. Allocate type2
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// test handle for PCI bus 0.
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//
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HwType = 2;
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BusHandler = HalpAllocateAndInitPciBusHandler (HwType, 0, TRUE);
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if (HalpIsValidPCIDevice (BusHandler, SlotNumber)) {
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break;
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}
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//
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// Valid device not found on Type2 access for this slot.
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// Reallocate the bus handler are Type1 and take a look.
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//
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HwType = 1;
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BusHandler = HalpAllocateAndInitPciBusHandler (HwType, 0, TRUE);
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if (HalpIsValidPCIDevice (BusHandler, SlotNumber)) {
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break;
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}
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HwType = 2;
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}
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//
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// Reset handler for PCI bus 0 to whatever style config space
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// was finally decided.
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//
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HalpAllocateAndInitPciBusHandler (HwType, 0, FALSE);
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}
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#endif
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//
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// For each PCI bus present, allocate a handler structure and
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// fill in the dispatch functions
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//
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do {
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for (i=0; i < PCIRegInfo->NoBuses; i++) {
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//
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// If handler not already built, do it now
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//
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if (!HalpHandlerForBus (PCIBus, i)) {
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HalpAllocateAndInitPciBusHandler (HwType, i, FALSE);
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}
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}
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//
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// Bus handlers for all PCI buses have been allocated, go collect
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// pci bridge information.
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//
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} while (HalpGetPciBridgeConfig (HwType, &PCIRegInfo->NoBuses)) ;
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//
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// Fixup SUPPORTED_RANGES
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//
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HalpFixupPciSupportedRanges (PCIRegInfo->NoBuses);
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#if DBG
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HalpTestPci (0);
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#endif
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}
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PBUS_HANDLER
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HalpAllocateAndInitPciBusHandler (
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IN ULONG HwType,
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IN ULONG BusNo,
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IN BOOLEAN TestAllocation
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)
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{
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PBUS_HANDLER Bus;
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PPCIPBUSDATA BusData;
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Bus = HalpAllocateBusHandler (
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PCIBus, // Interface type
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PCIConfiguration, // Has this configuration space
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BusNo, // bus #
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Internal, // child of this bus
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0, // and number
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sizeof (PCIPBUSDATA) // sizeof bus specific buffer
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);
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//
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// Fill in PCI handlers
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//
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Bus->GetBusData = (PGETSETBUSDATA) HalpGetPCIData;
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Bus->SetBusData = (PGETSETBUSDATA) HalpSetPCIData;
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Bus->GetInterruptVector = (PGETINTERRUPTVECTOR) HalpGetPCIIntOnISABus;
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Bus->AdjustResourceList = (PADJUSTRESOURCELIST) HalpAdjustPCIResourceList;
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Bus->AssignSlotResources = (PASSIGNSLOTRESOURCES) HalpAssignPCISlotResources;
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Bus->BusAddresses->Dma.Limit = 0;
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BusData = (PPCIPBUSDATA) Bus->BusData;
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//
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// Fill in common PCI data
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//
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BusData->CommonData.Tag = PCI_DATA_TAG;
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BusData->CommonData.Version = PCI_DATA_VERSION;
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BusData->CommonData.ReadConfig = (PciReadWriteConfig) HalpReadPCIConfig;
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BusData->CommonData.WriteConfig = (PciReadWriteConfig) HalpWritePCIConfig;
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BusData->CommonData.Pin2Line = (PciPin2Line) HalpPCIPin2ISALine;
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BusData->CommonData.Line2Pin = (PciLine2Pin) HalpPCIISALine2Pin;
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//
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// Set defaults
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//
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Bus->BusAddresses->Memory.Limit = 0x3EFFFFFF;
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Bus->BusAddresses->IO.Limit = 0x3F7FFFFF;
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BusData->GetIrqRange = (PciIrqRange) HalpGetISAFixedPCIIrq;
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RtlInitializeBitMap (&BusData->DeviceConfigured,
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BusData->ConfiguredBits, 256);
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switch (HwType) {
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case 1:
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//
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// Initialize access port information for Type1 handlers
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// direct Method.
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//
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RtlCopyMemory (&PCIConfigHandler,
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&PCIConfigHandlerType1,
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sizeof (PCIConfigHandler));
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BusData->MaxDevice = HalpPciMaxSlots;
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break;
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case 2:
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//
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// Initialize access port information for Type2 handlers
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// indirect Method.
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//
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RtlCopyMemory (&PCIConfigHandler,
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&PCIConfigHandlerType2,
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sizeof (PCIConfigHandler));
|
|
|
|
//
|
|
// Allow access all 32 devices per bus.
|
|
//
|
|
BusData->MaxDevice = PCI_MAX_DEVICES;
|
|
break;
|
|
|
|
default:
|
|
// unsupport type
|
|
DBGMSG ("HAL: Unkown PCI type\n");
|
|
}
|
|
|
|
if (!TestAllocation) {
|
|
#ifdef SUBCLASSPCI
|
|
HalpSubclassPCISupport (Bus, HwType);
|
|
#endif
|
|
}
|
|
|
|
return Bus;
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpIsValidPCIDevice (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Reads the device configuration data for the given slot and
|
|
returns TRUE if the configuration data appears to be valid for
|
|
a PCI device; otherwise returns FALSE.
|
|
|
|
Arguments:
|
|
|
|
BusHandler - Bus to check
|
|
Slot - Slot to check
|
|
|
|
--*/
|
|
|
|
{
|
|
PPCI_COMMON_CONFIG PciData;
|
|
UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
|
|
ULONG i, j;
|
|
|
|
|
|
PciData = (PPCI_COMMON_CONFIG) iBuffer;
|
|
|
|
//
|
|
// Read device common header
|
|
//
|
|
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
//
|
|
// Valid device header?
|
|
//
|
|
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID ||
|
|
PCI_CONFIG_TYPE (PciData) != PCI_DEVICE_TYPE) {
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
//
|
|
// Check fields for reasonable values
|
|
//
|
|
|
|
if ((PciData->u.type0.InterruptPin && PciData->u.type0.InterruptPin > 4) ||
|
|
(PciData->u.type0.InterruptLine & 0x70)) {
|
|
return FALSE;
|
|
}
|
|
|
|
for (i=0; i < PCI_TYPE0_ADDRESSES; i++) {
|
|
j = PciData->u.type0.BaseAddresses[i];
|
|
|
|
if (j & PCI_ADDRESS_IO_SPACE) {
|
|
if (j > 0xffff) {
|
|
// IO port > 64k?
|
|
return FALSE;
|
|
}
|
|
} else {
|
|
if (j > 0xf && j < 0x80000) {
|
|
// Mem address < 0x8000h?
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
if (Is64BitBaseAddress(j)) {
|
|
i += 1;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Guess it's a valid device..
|
|
//
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
ULONG
|
|
HalpGetPCIData (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PBUS_HANDLER RootHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
The function returns the Pci bus data for a device.
|
|
|
|
Arguments:
|
|
|
|
BusNumber - Indicates which bus.
|
|
|
|
VendorSpecificDevice - The VendorID (low Word) and DeviceID (High Word)
|
|
|
|
Buffer - Supplies the space to store the data.
|
|
|
|
Length - Supplies a count in bytes of the maximum amount to return.
|
|
|
|
Return Value:
|
|
|
|
Returns the amount of data stored into the buffer.
|
|
|
|
If this PCI slot has never been set, then the configuration information
|
|
returned is zeroed.
|
|
|
|
|
|
--*/
|
|
{
|
|
PPCI_COMMON_CONFIG PciData;
|
|
UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
|
|
PPCIPBUSDATA BusData;
|
|
ULONG Len;
|
|
ULONG i, bit;
|
|
|
|
if (Length > sizeof (PCI_COMMON_CONFIG)) {
|
|
Length = sizeof (PCI_COMMON_CONFIG);
|
|
}
|
|
|
|
Len = 0;
|
|
PciData = (PPCI_COMMON_CONFIG) iBuffer;
|
|
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH) {
|
|
//
|
|
// The user did not request any data from the common
|
|
// header. Verify the PCI device exists, then continue
|
|
// in the device specific area.
|
|
//
|
|
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, sizeof(ULONG));
|
|
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID) {
|
|
return 0;
|
|
}
|
|
|
|
} else {
|
|
|
|
//
|
|
// Caller requested at least some data within the
|
|
// common header. Read the whole header, effect the
|
|
// fields we need to and then copy the user's requested
|
|
// bytes from the header
|
|
//
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
|
|
//
|
|
// Read this PCI devices slot data
|
|
//
|
|
|
|
Len = PCI_COMMON_HDR_LENGTH;
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, Len);
|
|
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID ||
|
|
PCI_CONFIG_TYPE (PciData) != PCI_DEVICE_TYPE) {
|
|
PciData->VendorID = PCI_INVALID_VENDORID;
|
|
Len = 2; // only return invalid id
|
|
|
|
} else {
|
|
|
|
BusData->CommonData.Pin2Line (BusHandler, RootHandler, Slot, PciData);
|
|
}
|
|
|
|
//
|
|
// Has this PCI device been configured?
|
|
//
|
|
|
|
#if 0
|
|
//
|
|
// On DBG build, if this PCI device has not yet been configured,
|
|
// then don't report any current configuration the device may have.
|
|
//
|
|
|
|
bit = PciBitIndex(Slot.u.bits.DeviceNumber, Slot.u.bits.FunctionNumber);
|
|
if (!RtlCheckBit(&BusData->DeviceConfigured, bit)) {
|
|
|
|
for (i=0; i < PCI_TYPE0_ADDRESSES; i++) {
|
|
PciData->u.type0.BaseAddresses[i] = 0;
|
|
}
|
|
|
|
PciData->u.type0.ROMBaseAddress = 0;
|
|
PciData->Command &= ~(PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE);
|
|
}
|
|
#endif
|
|
|
|
|
|
//
|
|
// Copy whatever data overlaps into the callers buffer
|
|
//
|
|
|
|
if (Len < Offset) {
|
|
// no data at caller's buffer
|
|
return 0;
|
|
}
|
|
|
|
Len -= Offset;
|
|
if (Len > Length) {
|
|
Len = Length;
|
|
}
|
|
|
|
RtlMoveMemory(Buffer, iBuffer + Offset, Len);
|
|
|
|
Offset += Len;
|
|
Buffer += Len;
|
|
Length -= Len;
|
|
}
|
|
|
|
if (Length) {
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH) {
|
|
//
|
|
// The remaining Buffer comes from the Device Specific
|
|
// area - put on the kitten gloves and read from it.
|
|
//
|
|
// Specific read/writes to the PCI device specific area
|
|
// are guarenteed:
|
|
//
|
|
// Not to read/write any byte outside the area specified
|
|
// by the caller. (this may cause WORD or BYTE references
|
|
// to the area in order to read the non-dword aligned
|
|
// ends of the request)
|
|
//
|
|
// To use a WORD access if the requested length is exactly
|
|
// a WORD long.
|
|
//
|
|
// To use a BYTE access if the requested length is exactly
|
|
// a BYTE long.
|
|
//
|
|
|
|
HalpReadPCIConfig (BusHandler, Slot, Buffer, Offset, Length);
|
|
Len += Length;
|
|
}
|
|
}
|
|
|
|
return Len;
|
|
}
|
|
|
|
ULONG
|
|
HalpSetPCIData (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PBUS_HANDLER RootHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
The function returns the Pci bus data for a device.
|
|
|
|
Arguments:
|
|
|
|
|
|
VendorSpecificDevice - The VendorID (low Word) and DeviceID (High Word)
|
|
|
|
Buffer - Supplies the space to store the data.
|
|
|
|
Length - Supplies a count in bytes of the maximum amount to return.
|
|
|
|
Return Value:
|
|
|
|
Returns the amount of data stored into the buffer.
|
|
|
|
--*/
|
|
{
|
|
PPCI_COMMON_CONFIG PciData, PciData2;
|
|
UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
|
|
UCHAR iBuffer2[PCI_COMMON_HDR_LENGTH];
|
|
PPCIPBUSDATA BusData;
|
|
ULONG Len, cnt;
|
|
|
|
|
|
if (Length > sizeof (PCI_COMMON_CONFIG)) {
|
|
Length = sizeof (PCI_COMMON_CONFIG);
|
|
}
|
|
|
|
|
|
Len = 0;
|
|
PciData = (PPCI_COMMON_CONFIG) iBuffer;
|
|
PciData2 = (PPCI_COMMON_CONFIG) iBuffer2;
|
|
|
|
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH) {
|
|
//
|
|
// The user did not request any data from the common
|
|
// header. Verify the PCI device exists, then continue in
|
|
// the device specific area.
|
|
//
|
|
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, sizeof(ULONG));
|
|
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID) {
|
|
return 0;
|
|
}
|
|
|
|
} else {
|
|
|
|
//
|
|
// Caller requested to set at least some data within the
|
|
// common header.
|
|
//
|
|
|
|
Len = PCI_COMMON_HDR_LENGTH;
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, Len);
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID ||
|
|
PCI_CONFIG_TYPE (PciData) != PCI_DEVICE_TYPE) {
|
|
|
|
// no device, or header type unkown
|
|
return 0;
|
|
}
|
|
|
|
|
|
//
|
|
// Set this device as configured
|
|
//
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
#if 0
|
|
cnt = PciBitIndex(Slot.u.bits.DeviceNumber, Slot.u.bits.FunctionNumber);
|
|
RtlSetBits (&BusData->DeviceConfigured, cnt, 1);
|
|
#endif
|
|
//
|
|
// Copy COMMON_HDR values to buffer2, then overlay callers changes.
|
|
//
|
|
|
|
RtlMoveMemory (iBuffer2, iBuffer, Len);
|
|
BusData->CommonData.Pin2Line (BusHandler, RootHandler, Slot, PciData2);
|
|
|
|
Len -= Offset;
|
|
if (Len > Length) {
|
|
Len = Length;
|
|
}
|
|
|
|
RtlMoveMemory (iBuffer2+Offset, Buffer, Len);
|
|
|
|
// in case interrupt line or pin was editted
|
|
BusData->CommonData.Line2Pin (BusHandler, RootHandler, Slot, PciData2, PciData);
|
|
|
|
#if DBG
|
|
//
|
|
// Verify R/O fields haven't changed
|
|
//
|
|
if (PciData2->VendorID != PciData->VendorID ||
|
|
PciData2->DeviceID != PciData->DeviceID ||
|
|
PciData2->RevisionID != PciData->RevisionID ||
|
|
PciData2->ProgIf != PciData->ProgIf ||
|
|
PciData2->SubClass != PciData->SubClass ||
|
|
PciData2->BaseClass != PciData->BaseClass ||
|
|
PciData2->HeaderType != PciData->HeaderType ||
|
|
PciData2->BaseClass != PciData->BaseClass ||
|
|
PciData2->u.type0.MinimumGrant != PciData->u.type0.MinimumGrant ||
|
|
PciData2->u.type0.MaximumLatency != PciData->u.type0.MaximumLatency) {
|
|
DbgPrint ("PCI SetBusData: Read-Only configuration value changed\n");
|
|
//DbgBreakPoint ();
|
|
}
|
|
#endif
|
|
//
|
|
// Set new PCI configuration
|
|
//
|
|
|
|
HalpWritePCIConfig (BusHandler, Slot, iBuffer2+Offset, Offset, Len);
|
|
|
|
Offset += Len;
|
|
Buffer += Len;
|
|
Length -= Len;
|
|
}
|
|
|
|
if (Length) {
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH) {
|
|
//
|
|
// The remaining Buffer comes from the Device Specific
|
|
// area - put on the kitten gloves and write it
|
|
//
|
|
// Specific read/writes to the PCI device specific area
|
|
// are guarenteed:
|
|
//
|
|
// Not to read/write any byte outside the area specified
|
|
// by the caller. (this may cause WORD or BYTE references
|
|
// to the area in order to read the non-dword aligned
|
|
// ends of the request)
|
|
//
|
|
// To use a WORD access if the requested length is exactly
|
|
// a WORD long.
|
|
//
|
|
// To use a BYTE access if the requested length is exactly
|
|
// a BYTE long.
|
|
//
|
|
|
|
HalpWritePCIConfig (BusHandler, Slot, Buffer, Offset, Length);
|
|
Len += Length;
|
|
}
|
|
}
|
|
|
|
return Len;
|
|
}
|
|
|
|
VOID
|
|
HalpReadPCIConfig (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
{
|
|
#define ATIBUG 1
|
|
#if ATIBUG
|
|
USHORT VendorId;
|
|
LONG Len;
|
|
#endif
|
|
|
|
if (!HalpValidPCISlot (BusHandler, Slot)) {
|
|
//
|
|
// Invalid SlotID return no data
|
|
//
|
|
|
|
RtlFillMemory (Buffer, Length, (UCHAR) -1);
|
|
return ;
|
|
}
|
|
|
|
#if ATIBUG
|
|
//
|
|
// Temporary Hack (MOTKJR) - We have discovered a problem between the ATI
|
|
// Video Driver and the NCR 810/825 SCSI parts. The NCR chip has hardware
|
|
// registers in Configuration Space above 0x40 which have a side effect that
|
|
// a read from these registers is destructive to its contents. If a SCSI
|
|
// operation is active when these registers are read, the NCR device will
|
|
// abort the operation and further I/O is impossible. Therefore, we will
|
|
// not allow anyone to read from Offset 0x40 to 0xFF for any PCI slot that
|
|
// has an NCR vendor ID number. Care must be taken to check for requests
|
|
// which overlap both the PCI Common Header and the Device Dependent area.
|
|
//
|
|
#define NCR_VENDOR_ID 0x1000
|
|
|
|
HalpPCIConfig (BusHandler, Slot, (PUCHAR) &VendorId, 0x0, sizeof(VendorId),
|
|
PCIConfigHandler.ConfigRead);
|
|
|
|
if ((VendorId == NCR_VENDOR_ID) && (Offset + Length > PCI_COMMON_HDR_LENGTH)) {
|
|
Len = PCI_COMMON_HDR_LENGTH - Offset;
|
|
if (Len < 0)
|
|
Len = 0;
|
|
RtlFillMemory ((PVOID)((PUCHAR)Buffer+Len), Length-Len, (UCHAR) -1);
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH)
|
|
return;
|
|
Length = Len;
|
|
}
|
|
#endif
|
|
|
|
HalpPCIConfig (BusHandler, Slot, (PUCHAR) Buffer, Offset, Length,
|
|
PCIConfigHandler.ConfigRead);
|
|
}
|
|
|
|
VOID
|
|
HalpWritePCIConfig (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
{
|
|
if (!HalpValidPCISlot (BusHandler, Slot)) {
|
|
//
|
|
// Invalid SlotID do nothing
|
|
//
|
|
return ;
|
|
}
|
|
|
|
HalpPCIConfig (BusHandler, Slot, (PUCHAR) Buffer, Offset, Length,
|
|
PCIConfigHandler.ConfigWrite);
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpValidPCISlot (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot
|
|
)
|
|
{
|
|
PCI_SLOT_NUMBER Slot2;
|
|
PPCIPBUSDATA BusData;
|
|
UCHAR HeaderType;
|
|
ULONG i;
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
|
|
if (Slot.u.bits.Reserved != 0) {
|
|
return FALSE;
|
|
}
|
|
|
|
if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) {
|
|
return FALSE;
|
|
}
|
|
|
|
if (Slot.u.bits.FunctionNumber == 0) {
|
|
return TRUE;
|
|
}
|
|
|
|
//
|
|
// Non zero function numbers are only supported if the
|
|
// device has the PCI_MULTIFUNCTION bit set in it's header
|
|
//
|
|
|
|
i = Slot.u.bits.DeviceNumber;
|
|
|
|
//
|
|
// Read DeviceNumber, Function zero, to determine if the
|
|
// PCI supports multifunction devices
|
|
//
|
|
|
|
Slot2 = Slot;
|
|
Slot2.u.bits.FunctionNumber = 0;
|
|
|
|
HalpReadPCIConfig (
|
|
BusHandler,
|
|
Slot2,
|
|
&HeaderType,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, HeaderType),
|
|
sizeof (UCHAR)
|
|
);
|
|
|
|
if (!(HeaderType & PCI_MULTIFUNCTION) || HeaderType == 0xFF) {
|
|
// this device doesn't exists or doesn't support MULTIFUNCTION types
|
|
return FALSE;
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpPCIConfig (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length,
|
|
IN FncConfigIO *ConfigIO
|
|
)
|
|
{
|
|
KIRQL OldIrql;
|
|
ULONG i;
|
|
UCHAR State[20];
|
|
PPCIPBUSDATA BusData;
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
PCIConfigHandler.Synchronize (BusHandler, Slot, &OldIrql, State);
|
|
|
|
while (Length) {
|
|
i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
|
|
i = ConfigIO[i] (BusData, State, Buffer, Offset);
|
|
|
|
Offset += i;
|
|
Buffer += i;
|
|
Length -= i;
|
|
}
|
|
|
|
PCIConfigHandler.ReleaseSynchronzation (BusHandler, OldIrql);
|
|
}
|
|
|
|
VOID HalpPCISynchronizeType1 (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PKIRQL Irql,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1
|
|
)
|
|
{
|
|
//
|
|
// Initialize PciCfg1
|
|
//
|
|
|
|
PciCfg1->u.AsULONG = HalpTranslatePciSlotNumber(BusHandler->BusNumber, Slot.u.bits.DeviceNumber)
|
|
+ 0x100 * Slot.u.bits.FunctionNumber;
|
|
|
|
}
|
|
|
|
VOID HalpPCIReleaseSynchronzationType1 (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN KIRQL Irql
|
|
)
|
|
{
|
|
|
|
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIReadUcharType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
*Buffer = READ_PORT_UCHAR ((PUCHAR)(PciCfg1->u.AsULONG + i));
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUshortType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
*((PUSHORT) Buffer) = READ_PORT_USHORT ((PUSHORT)(PciCfg1->u.AsULONG + i));
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUlongType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
*((PULONG) Buffer) = READ_PORT_ULONG ((PULONG) (PciCfg1->u.AsULONG));
|
|
return sizeof (ULONG);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIWriteUcharType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_UCHAR (PciCfg1->u.AsULONG + i, *Buffer );
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUshortType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_USHORT (PciCfg1->u.AsULONG + i, *((PUSHORT) Buffer) );
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUlongType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (PciCfg1->u.AsULONG, *((PULONG) Buffer) );
|
|
return sizeof (ULONG);
|
|
}
|
|
|
|
VOID HalpPCISynchronizeType2 (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PKIRQL Irql,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1
|
|
)
|
|
{
|
|
|
|
//
|
|
// Initialize PciCfg1
|
|
//
|
|
|
|
PciCfg1->u.AsULONG = 0;
|
|
if ((PciCfg1->u.bits.BusNumber = BusHandler->BusNumber) == 0) {
|
|
|
|
// This hack is to maintain device number compatibility
|
|
// on bus 0 with the Type1 functions. We do this so that
|
|
// the installed base maintains the same "slot" numbering.
|
|
// The notable issue is with network interfaces where the
|
|
// slot number is stored in the registry at install time.
|
|
// It was judged too subtle and too painful to have everyone
|
|
// reinstall networking if they added a bridged device to
|
|
// their system.
|
|
|
|
int MappedDev;
|
|
ULONG Offset;
|
|
#define PRESHIFT 9 // Make invalid slot numbers to map to dev 0.
|
|
// Dev 0 is inaccessible from the 27-82660 Bridge.
|
|
|
|
// Get the offset from the Type1 (direct mapping) offset table.
|
|
// If the device number isn't "valid", use an offset that won't
|
|
// actually end up selecting any device.
|
|
|
|
Offset = (Slot.u.bits.DeviceNumber < HalpPciMaxSlots) ?
|
|
HalpPciConfigSlot[Slot.u.bits.DeviceNumber] : (1 << (PRESHIFT+1));
|
|
|
|
// Determine the device number accessed by the "offset".
|
|
// If bit 11 is set, MappedDev = 11; bit 12, MappedDev = 12;...
|
|
|
|
Offset >>= PRESHIFT;
|
|
MappedDev = PRESHIFT - 1;
|
|
|
|
do {
|
|
MappedDev++;
|
|
Offset >>= 1;
|
|
|
|
} while (Offset);
|
|
|
|
// The 27-82660 docs say to set the device number field to
|
|
// 10 less than the PCI Address bit number.
|
|
|
|
PciCfg1->u.bits.DeviceNumber = MappedDev - 10;
|
|
|
|
} else {
|
|
PciCfg1->u.bits.DeviceNumber = Slot.u.bits.DeviceNumber;
|
|
}
|
|
PciCfg1->u.bits.FunctionNumber = Slot.u.bits.FunctionNumber;
|
|
PciCfg1->u.bits.Enable = TRUE;
|
|
|
|
KeRaiseIrql (PROFILE_LEVEL, Irql);
|
|
KiAcquireSpinLock (&HalpPCIConfigLock);
|
|
|
|
}
|
|
|
|
|
|
VOID HalpPCIReleaseSynchronzationType2 (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN KIRQL Irql
|
|
)
|
|
{
|
|
|
|
KiReleaseSpinLock (&HalpPCIConfigLock);
|
|
KeLowerIrql (Irql);
|
|
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIReadUcharType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigAddress, PciCfg1->u.AsULONG );
|
|
*((PUCHAR) Buffer) = READ_PORT_UCHAR ((PUCHAR)&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigData + i);
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUshortType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigAddress, PciCfg1->u.AsULONG );
|
|
*((PUSHORT) Buffer) = READ_PORT_USHORT ((PUCHAR)&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigData + i);
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUlongType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigAddress, PciCfg1->u.AsULONG);
|
|
*((PULONG) Buffer) = READ_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigData);
|
|
return sizeof(ULONG);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIWriteUcharType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigAddress, PciCfg1->u.AsULONG );
|
|
WRITE_PORT_UCHAR ((PUCHAR)&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigData + i,*Buffer);
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUshortType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigAddress, PciCfg1->u.AsULONG );
|
|
WRITE_PORT_USHORT ((PUCHAR)&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigData + (USHORT) i,*((PUSHORT)Buffer));
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUlongType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigAddress, PciCfg1->u.AsULONG);
|
|
WRITE_PORT_ULONG (&((PPLANAR_CONTROL)HalpIoControlBase)->ConfigData,*((PULONG)Buffer));
|
|
return sizeof(ULONG);
|
|
}
|
|
|
|
|
|
NTSTATUS
|
|
HalpAssignPCISlotResources (
|
|
IN PBUS_HANDLER BusHandler,
|
|
IN PBUS_HANDLER RootHandler,
|
|
IN PUNICODE_STRING RegistryPath,
|
|
IN PUNICODE_STRING DriverClassName OPTIONAL,
|
|
IN PDRIVER_OBJECT DriverObject,
|
|
IN PDEVICE_OBJECT DeviceObject OPTIONAL,
|
|
IN ULONG Slot,
|
|
IN OUT PCM_RESOURCE_LIST *pAllocatedResources
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Reads the targeted device to determine it's required resources.
|
|
Calls IoAssignResources to allocate them.
|
|
Sets the targeted device with it's assigned resoruces
|
|
and returns the assignments to the caller.
|
|
|
|
Arguments:
|
|
|
|
Return Value:
|
|
|
|
STATUS_SUCCESS or error
|
|
|
|
--*/
|
|
{
|
|
NTSTATUS status;
|
|
PUCHAR WorkingPool;
|
|
PPCI_COMMON_CONFIG PciData, PciOrigData, PciData2;
|
|
PCI_SLOT_NUMBER PciSlot;
|
|
PPCIPBUSDATA BusData;
|
|
PIO_RESOURCE_REQUIREMENTS_LIST CompleteList;
|
|
PIO_RESOURCE_DESCRIPTOR Descriptor;
|
|
PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
|
|
ULONG BusNumber;
|
|
ULONG i, j, m, length, memtype;
|
|
ULONG NoBaseAddress, RomIndex, Option;
|
|
PULONG BaseAddress[PCI_TYPE0_ADDRESSES + 1];
|
|
PULONG OrigAddress[PCI_TYPE0_ADDRESSES + 1];
|
|
BOOLEAN Match, EnableRomBase;
|
|
|
|
|
|
*pAllocatedResources = NULL;
|
|
PciSlot = *((PPCI_SLOT_NUMBER) &Slot);
|
|
BusNumber = BusHandler->BusNumber;
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
|
|
//
|
|
// Allocate some pool for working space
|
|
//
|
|
|
|
i = sizeof (IO_RESOURCE_REQUIREMENTS_LIST) +
|
|
sizeof (IO_RESOURCE_DESCRIPTOR) * (PCI_TYPE0_ADDRESSES + 2) * 2 +
|
|
PCI_COMMON_HDR_LENGTH * 3;
|
|
|
|
WorkingPool = (PUCHAR) ExAllocatePool (PagedPool, i);
|
|
if (!WorkingPool) {
|
|
return STATUS_INSUFFICIENT_RESOURCES;
|
|
}
|
|
|
|
//
|
|
// Zero initialize pool, and get pointers into memory
|
|
//
|
|
|
|
RtlZeroMemory (WorkingPool, i);
|
|
CompleteList = (PIO_RESOURCE_REQUIREMENTS_LIST) WorkingPool;
|
|
PciData = (PPCI_COMMON_CONFIG) (WorkingPool + i - PCI_COMMON_HDR_LENGTH * 3);
|
|
PciData2 = (PPCI_COMMON_CONFIG) (WorkingPool + i - PCI_COMMON_HDR_LENGTH * 2);
|
|
PciOrigData = (PPCI_COMMON_CONFIG) (WorkingPool + i - PCI_COMMON_HDR_LENGTH * 1);
|
|
|
|
//
|
|
// Read the PCI device's configuration
|
|
//
|
|
|
|
HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID) {
|
|
ExFreePool (WorkingPool);
|
|
return STATUS_NO_SUCH_DEVICE;
|
|
}
|
|
|
|
//
|
|
// Make a copy of the device's current settings
|
|
//
|
|
|
|
RtlMoveMemory (PciOrigData, PciData, PCI_COMMON_HDR_LENGTH);
|
|
|
|
//
|
|
// Initialize base addresses base on configuration data type
|
|
//
|
|
|
|
switch (PCI_CONFIG_TYPE(PciData)) {
|
|
case 0 :
|
|
NoBaseAddress = PCI_TYPE0_ADDRESSES+1;
|
|
for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
|
|
BaseAddress[j] = &PciData->u.type0.BaseAddresses[j];
|
|
OrigAddress[j] = &PciOrigData->u.type0.BaseAddresses[j];
|
|
}
|
|
BaseAddress[j] = &PciData->u.type0.ROMBaseAddress;
|
|
OrigAddress[j] = &PciOrigData->u.type0.ROMBaseAddress;
|
|
RomIndex = j;
|
|
break;
|
|
case 1:
|
|
NoBaseAddress = PCI_TYPE1_ADDRESSES+1;
|
|
for (j=0; j < PCI_TYPE1_ADDRESSES; j++) {
|
|
BaseAddress[j] = &PciData->u.type1.BaseAddresses[j];
|
|
OrigAddress[j] = &PciOrigData->u.type1.BaseAddresses[j];
|
|
}
|
|
BaseAddress[j] = &PciData->u.type1.ROMBaseAddress;
|
|
OrigAddress[j] = &PciOrigData->u.type1.ROMBaseAddress;
|
|
RomIndex = j;
|
|
break;
|
|
|
|
default:
|
|
ExFreePool (WorkingPool);
|
|
return STATUS_NO_SUCH_DEVICE;
|
|
}
|
|
|
|
//
|
|
// If the BIOS doesn't have the device's ROM enabled, then we won't
|
|
// enable it either. Remove it from the list.
|
|
//
|
|
|
|
EnableRomBase = TRUE;
|
|
if (!(*BaseAddress[RomIndex] & PCI_ROMADDRESS_ENABLED)) {
|
|
ASSERT (RomIndex+1 == NoBaseAddress);
|
|
EnableRomBase = FALSE;
|
|
NoBaseAddress -= 1;
|
|
}
|
|
|
|
//
|
|
// Set resources to all bits on to see what type of resources
|
|
// are required.
|
|
//
|
|
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
*BaseAddress[j] = 0xFFFFFFFF;
|
|
}
|
|
|
|
//*BJ* PciData->Command &= ~(PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE);
|
|
*BaseAddress[RomIndex] &= ~PCI_ROMADDRESS_ENABLED;
|
|
HalpWritePCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
// note type0 & type1 overlay ROMBaseAddress, InterruptPin, and InterruptLine
|
|
BusData->CommonData.Pin2Line (BusHandler, RootHandler, PciSlot, PciData);
|
|
|
|
//
|
|
// Build an IO_RESOURCE_REQUIREMENTS_LIST for the PCI device
|
|
//
|
|
|
|
CompleteList->InterfaceType = PCIBus;
|
|
CompleteList->BusNumber = BusNumber;
|
|
CompleteList->SlotNumber = Slot;
|
|
CompleteList->AlternativeLists = 1;
|
|
|
|
CompleteList->List[0].Version = 1;
|
|
CompleteList->List[0].Revision = 1;
|
|
|
|
Descriptor = CompleteList->List[0].Descriptors;
|
|
|
|
//
|
|
// If PCI device has an interrupt resource, add it
|
|
//
|
|
|
|
if (PciData->u.type0.InterruptPin) {
|
|
CompleteList->List[0].Count++;
|
|
|
|
Descriptor->Option = 0;
|
|
Descriptor->Type = CmResourceTypeInterrupt;
|
|
Descriptor->ShareDisposition = CmResourceShareShared;
|
|
Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
|
|
|
|
// Fill in any vector here - we'll pick it back up in
|
|
// HalAdjustResourceList and adjust it to it's allowed settings
|
|
Descriptor->u.Interrupt.MinimumVector = 0;
|
|
Descriptor->u.Interrupt.MaximumVector = 0xff;
|
|
Descriptor++;
|
|
}
|
|
|
|
//
|
|
// Add a memory/port resoruce for each PCI resource
|
|
//
|
|
|
|
*BaseAddress[RomIndex] &= ~0x7ff;
|
|
|
|
//
|
|
// Rom Base Address resource is not enabled, as the ROM code cannot
|
|
// be executed on a risk box, and the algorithm below interprets
|
|
// the card's Rom Base Address requirements incorrectly
|
|
//
|
|
|
|
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
if (*BaseAddress[j]) {
|
|
i = *BaseAddress[j];
|
|
|
|
// scan for first set bit, that's the length & alignment
|
|
length = 1 << (i & PCI_ADDRESS_IO_SPACE ? 2 : 4);
|
|
while (!(i & length) && length) {
|
|
length <<= 1;
|
|
}
|
|
|
|
// scan for last set bit, that's the maxaddress + 1
|
|
for (m = length; i & m; m <<= 1) ;
|
|
m--;
|
|
|
|
// check for hosed PCI configuration requirements
|
|
if (length & ~m) {
|
|
#if DBG
|
|
DbgPrint ("PCI: defective device! Bus %d, Slot %d, Function %d\n",
|
|
BusNumber,
|
|
PciSlot.u.bits.DeviceNumber,
|
|
PciSlot.u.bits.FunctionNumber
|
|
);
|
|
|
|
DbgPrint ("PCI: BaseAddress[%d] = %08lx\n", j, i);
|
|
#endif
|
|
// the device is in error - punt. don't allow this
|
|
// resource any option - it either gets set to whatever
|
|
// bits it was able to return, or it doesn't get set.
|
|
|
|
if (i & PCI_ADDRESS_IO_SPACE) {
|
|
m = i & ~0x3;
|
|
Descriptor->u.Port.MinimumAddress.LowPart = m;
|
|
} else {
|
|
m = i & ~0xf;
|
|
Descriptor->u.Memory.MinimumAddress.LowPart = m;
|
|
}
|
|
|
|
m += length; // max address is min address + length
|
|
}
|
|
|
|
//
|
|
// Add requested resource
|
|
//
|
|
|
|
Descriptor->Option = 0;
|
|
if (i & PCI_ADDRESS_IO_SPACE) {
|
|
memtype = 0;
|
|
|
|
if (PciOrigData->Command & PCI_ENABLE_IO_SPACE) {
|
|
|
|
//
|
|
// The IO range is/was already enabled at some location, add that
|
|
// as it's preferred setting.
|
|
//
|
|
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO;
|
|
Descriptor->Option = IO_RESOURCE_PREFERRED;
|
|
|
|
Descriptor->u.Port.Length = length;
|
|
Descriptor->u.Port.Alignment = length;
|
|
Descriptor->u.Port.MinimumAddress.LowPart = *OrigAddress[j] & ~0x3;
|
|
Descriptor->u.Port.MaximumAddress.LowPart =
|
|
Descriptor->u.Port.MinimumAddress.LowPart + length - 1;
|
|
|
|
CompleteList->List[0].Count++;
|
|
Descriptor++;
|
|
|
|
Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
|
|
}
|
|
|
|
//
|
|
// Add this IO range
|
|
//
|
|
|
|
Descriptor->Type = CmResourceTypePort;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Flags = CM_RESOURCE_PORT_IO;
|
|
|
|
Descriptor->u.Port.Length = length;
|
|
Descriptor->u.Port.Alignment = length;
|
|
Descriptor->u.Port.MaximumAddress.LowPart = m;
|
|
|
|
} else {
|
|
|
|
memtype = i & PCI_ADDRESS_MEMORY_TYPE_MASK;
|
|
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
|
|
if (j == RomIndex) {
|
|
// this is a ROM address
|
|
Descriptor->Flags = CM_RESOURCE_MEMORY_READ_ONLY;
|
|
}
|
|
|
|
if (i & PCI_ADDRESS_MEMORY_PREFETCHABLE) {
|
|
Descriptor->Flags |= CM_RESOURCE_MEMORY_PREFETCHABLE;
|
|
}
|
|
|
|
if (!Is64BitBaseAddress(i) &&
|
|
(j == RomIndex ||
|
|
PciOrigData->Command & PCI_ENABLE_MEMORY_SPACE)) {
|
|
|
|
//
|
|
// The memory range is/was already enabled at some location, add that
|
|
// as it's preferred setting.
|
|
//
|
|
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
Descriptor->Option = IO_RESOURCE_PREFERRED;
|
|
|
|
Descriptor->u.Port.Length = length;
|
|
Descriptor->u.Port.Alignment = length;
|
|
Descriptor->u.Port.MinimumAddress.LowPart = *OrigAddress[j] & ~0xF;
|
|
Descriptor->u.Port.MaximumAddress.LowPart =
|
|
Descriptor->u.Port.MinimumAddress.LowPart + length - 1;
|
|
|
|
CompleteList->List[0].Count++;
|
|
Descriptor++;
|
|
|
|
Descriptor->Flags = Descriptor[-1].Flags;
|
|
Descriptor->Option = IO_RESOURCE_ALTERNATIVE;
|
|
}
|
|
|
|
//
|
|
// Add this memory range
|
|
//
|
|
|
|
Descriptor->Type = CmResourceTypeMemory;
|
|
Descriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
|
|
Descriptor->u.Memory.Length = length;
|
|
Descriptor->u.Memory.Alignment = length;
|
|
Descriptor->u.Memory.MaximumAddress.LowPart = m;
|
|
|
|
if (memtype == PCI_TYPE_20BIT && m > 0xFFFFF) {
|
|
// limit to 20 bit address
|
|
Descriptor->u.Memory.MaximumAddress.LowPart = 0xFFFFF;
|
|
}
|
|
|
|
if (Is64BitBaseAddress(i)) {
|
|
// skip upper half of 64 bit address since this processor
|
|
// only supports 32 bits of address space
|
|
j++;
|
|
}
|
|
}
|
|
|
|
CompleteList->List[0].Count++;
|
|
Descriptor++;
|
|
|
|
}
|
|
}
|
|
|
|
CompleteList->ListSize = (ULONG)
|
|
((PUCHAR) Descriptor - (PUCHAR) CompleteList);
|
|
|
|
//
|
|
// Restore the device settings as we found them, enable memory
|
|
// and io decode after setting base addresses. This is done in
|
|
// case HalAdjustResourceList wants to read the current settings
|
|
// in the device.
|
|
//
|
|
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
&PciOrigData->Status,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Status),
|
|
PCI_COMMON_HDR_LENGTH - FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
PciOrigData,
|
|
0,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
|
|
//
|
|
// Have the IO system allocate resource assignments
|
|
//
|
|
|
|
status = IoAssignResources (
|
|
RegistryPath,
|
|
DriverClassName,
|
|
DriverObject,
|
|
DeviceObject,
|
|
CompleteList,
|
|
pAllocatedResources
|
|
);
|
|
|
|
if (!NT_SUCCESS(status)) {
|
|
goto CleanUp;
|
|
}
|
|
|
|
//
|
|
// Slurp the assigments back into the PciData structure and
|
|
// perform them
|
|
//
|
|
|
|
CmDescriptor = (*pAllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
|
|
|
|
//
|
|
// If PCI device has an interrupt resource then that was
|
|
// passed in as the first requested resource
|
|
//
|
|
|
|
if (PciData->u.type0.InterruptPin) {
|
|
PciData->u.type0.InterruptLine = (UCHAR) CmDescriptor->u.Interrupt.Vector;
|
|
BusData->CommonData.Line2Pin (BusHandler, RootHandler, PciSlot, PciData, PciOrigData);
|
|
CmDescriptor++;
|
|
}
|
|
|
|
//
|
|
// Pull out resources in the order they were passed to IoAssignResources
|
|
//
|
|
|
|
m = 0;
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
i = *BaseAddress[j];
|
|
if (i) {
|
|
if (i & PCI_ADDRESS_IO_SPACE) {
|
|
m |= PCI_ENABLE_IO_SPACE;
|
|
*BaseAddress[j] = CmDescriptor->u.Port.Start.LowPart;
|
|
} else {
|
|
m |= PCI_ENABLE_MEMORY_SPACE;
|
|
*BaseAddress[j] = CmDescriptor->u.Memory.Start.LowPart;
|
|
|
|
if (Is64BitBaseAddress(i)) {
|
|
// skip upper 32 bits
|
|
j++;
|
|
}
|
|
}
|
|
CmDescriptor++;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Set addresses, but do not turn on decodes
|
|
//
|
|
|
|
HalpWritePCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
//
|
|
// Read configuration back and verify address settings took
|
|
//
|
|
|
|
HalpReadPCIConfig(BusHandler, PciSlot, PciData2, 0, PCI_COMMON_HDR_LENGTH);
|
|
|
|
Match = TRUE;
|
|
if (PciData->u.type0.InterruptLine != PciData2->u.type0.InterruptLine ||
|
|
PciData->u.type0.InterruptPin != PciData2->u.type0.InterruptPin ||
|
|
PciData->u.type0.ROMBaseAddress != PciData2->u.type0.ROMBaseAddress) {
|
|
Match = FALSE;
|
|
}
|
|
|
|
for (j=0; j < NoBaseAddress; j++) {
|
|
if (*BaseAddress[j]) {
|
|
if (*BaseAddress[j] & PCI_ADDRESS_IO_SPACE) {
|
|
i = (ULONG) ~0x3;
|
|
} else {
|
|
i = (ULONG) ~0xF;
|
|
}
|
|
|
|
if ((*BaseAddress[j] & i) !=
|
|
*((PULONG) ((PUCHAR) BaseAddress[j] -
|
|
(PUCHAR) PciData +
|
|
(PUCHAR) PciData2)) & i) {
|
|
|
|
Match = FALSE;
|
|
}
|
|
|
|
if (!(*BaseAddress[j] & PCI_ADDRESS_IO_SPACE) &&
|
|
(Is64BitBaseAddress(*BaseAddress[j]))) {
|
|
// skip upper 32 bits
|
|
j++;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!Match) {
|
|
#if DBG
|
|
DbgPrint ("PCI: defective device! Bus %d, Slot %d, Function %d\n",
|
|
BusNumber,
|
|
PciSlot.u.bits.DeviceNumber,
|
|
PciSlot.u.bits.FunctionNumber
|
|
);
|
|
#endif
|
|
status = STATUS_DEVICE_PROTOCOL_ERROR;
|
|
goto CleanUp;
|
|
}
|
|
|
|
//
|
|
// Settings took - turn on the appropiate decodes
|
|
//
|
|
|
|
if (EnableRomBase && *BaseAddress[RomIndex]) {
|
|
// a rom address was allocated and should be enabled
|
|
*BaseAddress[RomIndex] |= PCI_ROMADDRESS_ENABLED;
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
BaseAddress[RomIndex],
|
|
(ULONG) ((PUCHAR) BaseAddress[RomIndex] - (PUCHAR) PciData),
|
|
sizeof (ULONG)
|
|
);
|
|
}
|
|
|
|
// enable IO & Memory decodes (use HalSetBusData since valid settings now set)
|
|
|
|
// Set Bus master bit on for win95 compatability
|
|
m |= PCI_ENABLE_BUS_MASTER;
|
|
|
|
PciData->Command |= (USHORT) m;
|
|
HalSetBusDataByOffset (
|
|
PCIConfiguration,
|
|
BusHandler->BusNumber,
|
|
PciSlot.u.AsULONG,
|
|
&PciData->Command,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Command),
|
|
sizeof (PciData->Command)
|
|
);
|
|
|
|
CleanUp:
|
|
if (!NT_SUCCESS(status)) {
|
|
|
|
//
|
|
// Failure, if there are any allocated resources free them
|
|
//
|
|
|
|
if (*pAllocatedResources) {
|
|
IoAssignResources (
|
|
RegistryPath,
|
|
DriverClassName,
|
|
DriverObject,
|
|
DeviceObject,
|
|
NULL,
|
|
NULL
|
|
);
|
|
|
|
ExFreePool (*pAllocatedResources);
|
|
*pAllocatedResources = NULL;
|
|
}
|
|
|
|
//
|
|
// Restore the device settings as we found them, enable memory
|
|
// and io decode after setting base addresses
|
|
//
|
|
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
&PciOrigData->Status,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Status),
|
|
PCI_COMMON_HDR_LENGTH - FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
|
|
HalpWritePCIConfig (
|
|
BusHandler,
|
|
PciSlot,
|
|
PciOrigData,
|
|
0,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, Status)
|
|
);
|
|
}
|
|
|
|
ExFreePool (WorkingPool);
|
|
return status;
|
|
}
|
|
|
|
#if DBG
|
|
VOID
|
|
HalpTestPci (ULONG flag2)
|
|
{
|
|
PCI_SLOT_NUMBER SlotNumber;
|
|
PCI_COMMON_CONFIG PciData, OrigData;
|
|
ULONG i, f, j, k, bus;
|
|
BOOLEAN flag;
|
|
|
|
|
|
if (!flag2) {
|
|
return ;
|
|
}
|
|
|
|
DbgBreakPoint ();
|
|
SlotNumber.u.bits.Reserved = 0;
|
|
|
|
//
|
|
// Read every possible PCI Device/Function and display it's
|
|
// default info.
|
|
//
|
|
// (note this destories it's current settings)
|
|
//
|
|
|
|
flag = TRUE;
|
|
for (bus = 0; flag; bus++) {
|
|
|
|
for (i = 0; i < PCI_MAX_DEVICES; i++) {
|
|
SlotNumber.u.bits.DeviceNumber = i;
|
|
|
|
for (f = 0; f < PCI_MAX_FUNCTION; f++) {
|
|
SlotNumber.u.bits.FunctionNumber = f;
|
|
|
|
//
|
|
// Note: This is reading the DeviceSpecific area of
|
|
// the device's configuration - normally this should
|
|
// only be done on device for which the caller understands.
|
|
// I'm doing it here only for debugging.
|
|
//
|
|
|
|
j = HalGetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
if (j == 0) {
|
|
// out of buses
|
|
flag = FALSE;
|
|
break;
|
|
}
|
|
|
|
if (j < PCI_COMMON_HDR_LENGTH) {
|
|
continue;
|
|
}
|
|
|
|
HalSetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
1
|
|
);
|
|
|
|
HalGetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
#if 0
|
|
memcpy (&OrigData, &PciData, sizeof PciData);
|
|
|
|
for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
|
|
PciData.u.type0.BaseAddresses[j] = 0xFFFFFFFF;
|
|
}
|
|
|
|
PciData.u.type0.ROMBaseAddress = 0xFFFFFFFF;
|
|
|
|
HalSetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
HalGetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
#endif
|
|
|
|
DbgPrint ("PCI Bus %d Slot %2d %2d ID:%04lx-%04lx Rev:%04lx",
|
|
bus, i, f, PciData.VendorID, PciData.DeviceID,
|
|
PciData.RevisionID);
|
|
|
|
|
|
if (PciData.u.type0.InterruptPin) {
|
|
DbgPrint (" IntPin:%x", PciData.u.type0.InterruptPin);
|
|
}
|
|
|
|
if (PciData.u.type0.InterruptLine) {
|
|
DbgPrint (" IntLine:%x", PciData.u.type0.InterruptLine);
|
|
}
|
|
|
|
if (PciData.u.type0.ROMBaseAddress) {
|
|
DbgPrint (" ROM:%08lx", PciData.u.type0.ROMBaseAddress);
|
|
}
|
|
|
|
DbgPrint ("\n Cmd:%04x Status:%04x ProgIf:%04x SubClass:%04x BaseClass:%04lx\n",
|
|
PciData.Command, PciData.Status, PciData.ProgIf,
|
|
PciData.SubClass, PciData.BaseClass);
|
|
|
|
k = 0;
|
|
for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
|
|
if (PciData.u.type0.BaseAddresses[j]) {
|
|
DbgPrint (" Ad%d:%08lx", j, PciData.u.type0.BaseAddresses[j]);
|
|
k = 1;
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
if (PciData.u.type0.ROMBaseAddress == 0xC08001) {
|
|
|
|
PciData.u.type0.ROMBaseAddress = 0xC00001;
|
|
HalSetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
HalGetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&PciData,
|
|
sizeof (PciData)
|
|
);
|
|
|
|
DbgPrint ("\n Bogus rom address, edit yields:%08lx",
|
|
PciData.u.type0.ROMBaseAddress);
|
|
}
|
|
#endif
|
|
|
|
if (k) {
|
|
DbgPrint ("\n");
|
|
}
|
|
|
|
if (PciData.VendorID == 0x8086) {
|
|
// dump complete buffer
|
|
DbgPrint ("Command %x, Status %x, BIST %x\n",
|
|
PciData.Command, PciData.Status,
|
|
PciData.BIST
|
|
);
|
|
|
|
DbgPrint ("CacheLineSz %x, LatencyTimer %x",
|
|
PciData.CacheLineSize, PciData.LatencyTimer
|
|
);
|
|
|
|
for (j=0; j < 192; j++) {
|
|
if ((j & 0xf) == 0) {
|
|
DbgPrint ("\n%02x: ", j + 0x40);
|
|
}
|
|
DbgPrint ("%02x ", PciData.DeviceSpecific[j]);
|
|
}
|
|
DbgPrint ("\n");
|
|
}
|
|
|
|
|
|
#if 0
|
|
//
|
|
// now print original data
|
|
//
|
|
|
|
if (OrigData.u.type0.ROMBaseAddress) {
|
|
DbgPrint (" oROM:%08lx", OrigData.u.type0.ROMBaseAddress);
|
|
}
|
|
|
|
DbgPrint ("\n");
|
|
k = 0;
|
|
for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
|
|
if (OrigData.u.type0.BaseAddresses[j]) {
|
|
DbgPrint (" oAd%d:%08lx", j, OrigData.u.type0.BaseAddresses[j]);
|
|
k = 1;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Restore original settings
|
|
//
|
|
|
|
HalSetBusData (
|
|
PCIConfiguration,
|
|
bus,
|
|
SlotNumber.u.AsULONG,
|
|
&OrigData,
|
|
sizeof (PciData)
|
|
);
|
|
#endif
|
|
|
|
//
|
|
// Next
|
|
//
|
|
|
|
if (k) {
|
|
DbgPrint ("\n\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
DbgBreakPoint ();
|
|
}
|
|
#endif
|