226 lines
6.7 KiB
C
226 lines
6.7 KiB
C
//
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// Error Log Offset
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//
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#ifndef _CHELOG_H
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#define _CHELOG_H
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//
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// For R10000
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//
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#define R10_FATAL_ERR 0x00
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#define R10_NORMAL_ERR 0x80
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#define R10_ICHE 0x80
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#define R10_DCHE 0x81
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#define R10_SCHE_2BIT 0x82
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#define R10_SYSAD_PARITY 0x83
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#define R10_CHER_IN_CHER 0x84
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#define R10_SCHE_1BIT 0x86
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#define R10_St2 0x0a
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#define R10_St3 0x0b
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#define R10_ErrEPC 0x20
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#define R10_Status 0x28
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#define R10_Config 0x2c
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#define R10_PRid 0x30
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#define R10_CacheEr 0x34
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#define R10_BrDiag 0x38
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#define R10_PC_Ctrl 0x40
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#define R10_PC_Count 0x44
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#define R10_p_count 0x48
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#define R10_s_count 0x4c
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#define R10_CheAdd_1bit 0x50
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#define R10_CheAdd 0x54
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#define R10_TagHi 0x58
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#define R10_TagLo 0x5c
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#define R10_Cache_data0_Hi 0x60
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#define R10_Cache_data0_Lo 0x64
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#define R10_Cache_data1_Hi 0x68
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#define R10_Cache_data1_Lo 0x6c
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#define R10_Cache_data2_Hi 0x70
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#define R10_Cache_data2_Lo 0x74
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#define R10_Cache_data3_Hi 0x78
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#define R10_Cache_data3_Lo 0x7c
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#define R10_Cache_data4_Hi 0x80
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#define R10_Cache_data4_Lo 0x84
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#define R10_Cache_data5_Hi 0x88
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#define R10_Cache_data5_Lo 0x8c
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#define R10_Cache_data6_Hi 0x90
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#define R10_Cache_data6_Lo 0x94
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#define R10_Cache_data7_Hi 0x98
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#define R10_Cache_data7_Lo 0x9c
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#define R10_ECC0 0xa0
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#define R10_ECC1 0xa4
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#define R10_ECC2 0xa8
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#define R10_ECC3 0xac
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#define R10_ECC4 0xb0
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#define R10_ECC5 0xb4
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#define R10_ECC6 0xb8
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#define R10_ECC7 0xbc
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#define R10_BrDiag_Hi 0x38
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#define R10_BrDiag_Lo 0x3c
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/*
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* R10000 CacheErr register bit structure define
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*/
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#define R10CHE_KIND_MASK 0xc0000000 /* Kind of Cache error */
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#define R10CHE_KIND_I 0x00000000 /* I-Cache error */
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#define R10CHE_KIND_D 0x40000000 /* D-Cache error */
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#define R10CHE_KIND_S 0x80000000 /* S-Cache error */
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#define R10CHE_KIND_Y 0xc0000000 /* System I/F error */
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#define R10CHE_EW 0x20000000 /* Duplicated cache error */
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#define R10CHE_EE 0x10000000 /* Fatal error(D/Y) */
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#define R10CHE_D_MASK 0x0c000000 /* Data aray(I/D/S/Y) */
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#define R10CHE_D_WAY0 0x04000000 /* way0 */
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#define R10CHE_D_WAY1 0x08000000 /* way1 */
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#define R10CHE_TA_MASK 0x03000000 /* Tag Address aray(I/D/S) */
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#define R10CHE_TA_WAY0 0x01000000 /* way0 */
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#define R10CHE_TA_WAY1 0x02000000 /* way1 */
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#define R10CHE_TS_MASK 0x00c00000 /* Tag State aray(I/D) */
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#define R10CHE_TS_WAY0 0x00400000 /* way0 */
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#define R10CHE_TS_WAY1 0x00800000 /* way1 */
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#define R10CHE_TM_MASK 0x00300000 /* Tag Mod aray(D) */
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#define R10CHE_TM_WAY0 0x00100000 /* way0 */
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#define R10CHE_TM_WAY1 0x00200000 /* way1 */
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#define R10CHE_SA 0x02000000 /* SysAD address parity error */
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#define R10CHE_SC 0x01000000 /* SysCmd parity error */
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#define R10CHE_SR 0x00800000 /* SysResp parity error */
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#define R10CHE_PIDX_BLK 0x00003fC0 /* Primary block index */
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#define R10CHE_PIDX_DW 0x00003ff8 /* Primary double word index */
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#define R10CHE_SIDX_BLK 0x007fffC0 /* Secondary block index */
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#define R10CHE_BLK_SHIFT 6 /* block index shift */
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#define R10CHE_DW_SHIFT 3 /* double word index shift */
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/*
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* R10000 Cache Instruction Opecode define
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*/
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#define IndexInvalidate_I 0x00
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#define IndexLoadTag_I 0x04
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#define IndexStoreTag_I 0x08
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#define HitInvalidate_I 0x10
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#define CacheBarrier_I 0x14
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#define IndexLoadData_I 0x18
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#define IndexStoreData_I 0x1c
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#define IndexWriteBack_D 0x01
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#define IndexLoadTag_D 0x05
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#define IndexStoreTag_D 0x09
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#define HitInvalidate_D 0x11
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#define HitWriteBack_D 0x15
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#define IndexLoadData_D 0x19
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#define IndexStoreData_D 0x1d
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#define IndexWriteBack_S 0x03
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#define IndexLoadTag_S 0x07
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#define IndexStoreTag_S 0x0b
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#define HitInvalidate_S 0x13
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#define HitWriteBack_S 0x17
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#define IndexLoadData_S 0x1b
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#define IndexStoreData_S 0x1f
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#define branchdiag $22
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#if 0
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/* dmfc0 rt, rd */
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#define DMFC0( rt, rd ) \
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.word 0x40200000 | (rt<<16) | (rd<<11)
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/* dmfc0 rt, rd */
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#define DMTC0( rt, rd ) \
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.word 0x40a00000 | (rt<<16) | (rd<<11)
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/* mfpc rt, reg */
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#define MFPC( rt, reg ) \
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.word 0x4000c801 | (rt<<16) | (reg<<1)
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/* mtpc rt, reg */
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#define MTPC( rt, reg ) \
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.word 0x4080c801 | (rt<<16) | (reg<<1)
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/* mfps rt, reg */
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#define MFPS( rt, reg ) \
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.word 0x4000c800 | (rt<<16) | (reg<<1)
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/* mtps rt, reg */
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#define MTPS( rt, reg ) \
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.word 0x4080c800 | (rt<<16) | (reg<<1)
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#endif
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//
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// For R4400
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//
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#define EPC_cpu 0x0
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#define Psr_cpu 0x8
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#define CFG_cpu 0xc
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#define PRID_cpu 0x10
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#define CHERR_cpu 0x14
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#define CheAdd_p 0x18
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#define CheAdd_s 0x1c
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#define TagLo_p 0x20
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#define ECC_p 0x24
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#define TagLo_s 0x28
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#define ECC_s 0x2c
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#define data_s 0x30
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#define Good_data_s 0x38
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#define Good_TagLo_s 0x40
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#define Good_ECC_s 0x44
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#define tag_synd_s 0x48
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#define data_synd_s 0x4c
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#define xkphs_share 0x50
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//Error Code
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#define ICHE_EX 0x00
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#define ICHE_TAG 0x01
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#define ICHE_DAT 0x02
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#define ICHE_EB 0x03
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#define ICHE_UNKNOWN 0x0f
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#define DCHE_TAG_EX 0x10
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#define DCHE_TAG_CLEAN 0x11
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#define DCHE_TAG_DIRTY 0x12
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#define DCHE_TAG_UNKNOW 0x13
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#define DCHE_DAT_EX 0x14
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#define DCHE_DAT_DIRTY 0x16
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#define DCHE_UNKNOWN 0x1f
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#define SCHE_TAG_1BIT 0x20
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#define SCHE_TAG_2BIT 0x21
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#define SCHE_TAG_UNKNOW 0x23
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#define SCHE_DAT_EX 0x24
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#define SCHE_DAT_INV 0x25
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#define SCHE_DAT_1BIT 0x26
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#define SCHE_DAT_2BIT_C 0x27
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#define SCHE_DAT_2BIT_D 0x28
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#define SCHE_DAT_UNKNOW 0x29
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#define SCHE_UNKNOWN 0x2f
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#define SYSAD_PARITY 0x30
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// REG MASK
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#define CHERR_ER 0x80000000
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#define CHERR_EC 0x40000000
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#define CHERR_ED 0x20000000
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#define CHERR_ET 0x10000000
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#define CHERR_ES 0x08000000
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#define CHERR_EE 0x04000000
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#define CHERR_EB 0x02000000
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#define CHERR_EI 0x01000000
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#define CHERR_EW 0x00800000
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#define CHERR_SIDX 0x0003fff8
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#define CHERR_SIDX2 0x0003fff8
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#define CHERR_PIDX 0x00000007
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#define R4CT_PSTAT_MASK 0x000000c0
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#define R4CT_PSTAT_DRE 0x000000c0
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#define R4CT_PTAG_MASK 0xffffff00
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#define R4CT_SSTAT_MASK 0x00001c00
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#define R4CT_SSTAT_DRE 0x00001400
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#define R4CT_SSTAT_INV 0x00000000
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#define R4CT_STAG_MASK 0xffffe000
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#define CHERR_PSHF 12
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#endif /* _CHELOG_H */
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