1179 lines
26 KiB
C
1179 lines
26 KiB
C
/*++
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Copyright (c) 1990-1994 Microsoft Corporation
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Module Name:
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jxebsup.c
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Abstract:
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The module provides the EISA bus support for R98B systems.
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--*/
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#include "halp.h"
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#include "eisa.h"
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#include "bugcodes.h"
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//
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// Define the context structure for use by the interrupt routine.
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//
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typedef
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BOOLEAN
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(*PSECONDARY_DISPATCH)(
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PKINTERRUPT Interrupt
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);
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//
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// Define save area for EISA adapter objects.
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//
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PADAPTER_OBJECT HalpEisaAdapter[8];
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//
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// Define save area for EISA interrupt mask resiters and level\edge control
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// registers.
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//
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UCHAR HalpEisaInterrupt1Mask;
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UCHAR HalpEisaInterrupt2Mask;
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UCHAR HalpEisaInterrupt1Level;
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UCHAR HalpEisaInterrupt2Level;
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PADAPTER_OBJECT
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HalpAllocateEisaAdapter(
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IN PDEVICE_DESCRIPTION DeviceDescriptor
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)
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/*++
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Routine Description:
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This function allocates an EISA adapter object according to the
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specification supplied in the device description. The necessary device
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descriptor information is saved. If there is
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no existing adapter object for this channel then a new one is allocated.
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The saved information in the adapter object is used to set the various DMA
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modes when the channel is allocated or a map transfer is done.
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Arguments:
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DeviceDescription - Supplies the description of the device which want to
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use the DMA adapter.
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Return Value:
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Returns a pointer to the newly created adapter object or NULL if one
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cannot be created.
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--*/
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{
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PADAPTER_OBJECT adapterObject;
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PVOID adapterBaseVa;
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ULONG channelNumber;
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ULONG controllerNumber;
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DMA_EXTENDED_MODE extendedMode;
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UCHAR adapterMode;
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BOOLEAN useChannel;
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BOOLEAN eisaSystem;
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//
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// Determine if the the channel number is important. Master cards on
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// Eisa do not use a channel number.
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//
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if (DeviceDescriptor->InterfaceType == Eisa &&
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DeviceDescriptor->Master) {
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useChannel = FALSE;
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} else {
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useChannel = TRUE;
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}
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//
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// Channel 4 cannot be used since it is used for chaining. Return null if
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// it is requested.
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//
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if ((DeviceDescriptor->DmaChannel == 4 ||
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DeviceDescriptor->DmaChannel > 7) && useChannel) {
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return(NULL);
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}
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//
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// Set the channel number number.
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//
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channelNumber = DeviceDescriptor->DmaChannel & 0x03;
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//
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// Set the adapter base address to the Base address register and controller
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// number.
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//
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if (!(DeviceDescriptor->DmaChannel & 0x04)) {
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controllerNumber = 1;
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adapterBaseVa = (PVOID) &((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort;
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} else {
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controllerNumber = 2;
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adapterBaseVa = &((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort;
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}
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//
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// Determine if a new adapter object is necessary. If so then allocate it.
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//
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if (useChannel && HalpEisaAdapter[DeviceDescriptor->DmaChannel] != NULL) {
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adapterObject = HalpEisaAdapter[DeviceDescriptor->DmaChannel];
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} else {
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//
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// Allocate an adapter object.
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//
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adapterObject = (PADAPTER_OBJECT) HalpAllocateAdapter(
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0,
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adapterBaseVa,
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NULL
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);
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if (adapterObject == NULL) {
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return(NULL);
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}
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if (useChannel) {
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HalpEisaAdapter[DeviceDescriptor->DmaChannel] = adapterObject;
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}
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}
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//
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// If the channel is not used then indicate the this is an Eisa bus
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// master by setting the page port and mode to cascade even though
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// it is not used.
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//
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if (!useChannel) {
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adapterObject->PagePort = (PVOID) (~0x0);
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((PDMA_EISA_MODE) &adapterMode)->RequestMode = CASCADE_REQUEST_MODE;
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return(adapterObject);
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}
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//
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// Setup the pointers to all the random registers.
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//
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adapterObject->ChannelNumber = (UCHAR)channelNumber; // S004
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if (controllerNumber == 1) {
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switch ((UCHAR)channelNumber) {
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case 0:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel0;
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break;
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case 1:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel1;
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break;
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case 2:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel2;
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break;
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case 3:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel3;
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break;
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}
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//
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// Set the adapter number.
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//
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adapterObject->AdapterNumber = 1;
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//
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// Save the extended mode register address.
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//
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adapterBaseVa =
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma1ExtendedModePort;
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} else {
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switch (channelNumber) {
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case 1:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel5;
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break;
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case 2:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel6;
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break;
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case 3:
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adapterObject->PagePort = &((PDMA_PAGE) 0)->Channel7;
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break;
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}
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//
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// Set the adapter number.
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//
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adapterObject->AdapterNumber = 2;
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//
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// Save the extended mode register address.
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//
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adapterBaseVa =
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma2ExtendedModePort;
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}
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//
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// Initialzie the extended mode port.
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//
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*((PUCHAR) &extendedMode) = 0;
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extendedMode.ChannelNumber = (UCHAR)channelNumber; // S004
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switch (DeviceDescriptor->DmaSpeed) {
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case Compatible:
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extendedMode.TimingMode = COMPATIBLITY_TIMING;
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break;
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case TypeA:
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extendedMode.TimingMode = TYPE_A_TIMING;
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break;
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case TypeB:
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extendedMode.TimingMode = TYPE_B_TIMING;
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break;
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case TypeC:
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extendedMode.TimingMode = BURST_TIMING;
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break;
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default:
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ObDereferenceObject( adapterObject );
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return(NULL);
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}
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switch (DeviceDescriptor->DmaWidth) {
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case Width8Bits:
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extendedMode.TransferSize = BY_BYTE_8_BITS;
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break;
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case Width16Bits:
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extendedMode.TransferSize = BY_BYTE_16_BITS;
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break;
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case Width32Bits:
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extendedMode.TransferSize = BY_BYTE_32_BITS;
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break;
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default:
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ObDereferenceObject( adapterObject );
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return(NULL);
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}
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WRITE_REGISTER_UCHAR( adapterBaseVa, *((PUCHAR) &extendedMode));
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//
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// Initialize the adapter mode register value to the correct parameters,
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// and save them in the adapter object.
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//
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adapterMode = 0;
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((PDMA_EISA_MODE) &adapterMode)->Channel = adapterObject->ChannelNumber;
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if (DeviceDescriptor->Master) {
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((PDMA_EISA_MODE) &adapterMode)->RequestMode = CASCADE_REQUEST_MODE;
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//
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// Set the mode, and enable the request.
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//
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if (adapterObject->AdapterNumber == 1) {
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//
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// This request is for DMA controller 1
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//
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PDMA1_CONTROL dmaControl;
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dmaControl = adapterObject->AdapterBaseVa;
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WRITE_REGISTER_UCHAR( &dmaControl->Mode, adapterMode );
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//
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// Unmask the DMA channel.
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//
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WRITE_REGISTER_UCHAR(
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&dmaControl->SingleMask,
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(UCHAR) (DMA_CLEARMASK | adapterObject->ChannelNumber)
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);
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} else {
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//
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// This request is for DMA controller 1
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//
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PDMA2_CONTROL dmaControl;
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dmaControl = adapterObject->AdapterBaseVa;
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WRITE_REGISTER_UCHAR( &dmaControl->Mode, adapterMode );
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//
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// Unmask the DMA channel.
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//
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WRITE_REGISTER_UCHAR(
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&dmaControl->SingleMask,
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(UCHAR) (DMA_CLEARMASK | adapterObject->ChannelNumber)
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);
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}
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} else if (DeviceDescriptor->DemandMode) {
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((PDMA_EISA_MODE) &adapterMode)->RequestMode = DEMAND_REQUEST_MODE;
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} else {
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((PDMA_EISA_MODE) &adapterMode)->RequestMode = SINGLE_REQUEST_MODE;
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}
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if (DeviceDescriptor->AutoInitialize) {
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((PDMA_EISA_MODE) &adapterMode)->AutoInitialize = 1;
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}
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adapterObject->AdapterMode = adapterMode;
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return(adapterObject);
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}
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BOOLEAN
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HalpCreateEisaStructures (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the structures necessary for EISA operations
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and connects the intermediate interrupt dispatcher. It also initializes the
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EISA interrupt controller.
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Arguments:
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None.
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Return Value:
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If the second level interrupt dispatcher is connected, then a value of
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TRUE is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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UCHAR DataByte;
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KIRQL oldIrql;
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UCHAR charBuffer;
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//
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// Directly connect the EISA interrupt dispatcher to the level for
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// EISA bus interrupt.
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//
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// N.B. This vector is reserved for exclusive use by the HAL (see
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// interrupt initialization.
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//
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PCR->InterruptRoutine[EISA_DISPATCH_VECTOR] = (PKINTERRUPT_ROUTINE)HalpEisaDispatch;
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//
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// Raise the IRQL while the EISA interrupt controller is initalized.
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//
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KeRaiseIrql(EISA_LEVEL, &oldIrql);
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//
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// Initialize the EISA interrupt controller. There are two cascaded
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// interrupt controllers, each of which must initialized with 4 initialize
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// control words.
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//
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DataByte = 0;
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((PINITIALIZATION_COMMAND_1) &DataByte)->Icw4Needed = 1;
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((PINITIALIZATION_COMMAND_1) &DataByte)->InitializationFlag = 1;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
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DataByte
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);
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
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DataByte
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);
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//
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// The second intitialization control word sets the iterrupt vector to
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// 0-15.
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//
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DataByte = 0;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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DataByte = 0x08;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// The thrid initialization control word set the controls for slave mode.
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// The master ICW3 uses bit position and the slave ICW3 uses a numberic.
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//
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DataByte = 1 << SLAVE_IRQL_LEVEL;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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DataByte = SLAVE_IRQL_LEVEL;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// The fourth initialization control word is used to specify normal
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// end-of-interrupt mode and not special-fully-nested mode.
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//
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DataByte = 0;
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((PINITIALIZATION_COMMAND_4) &DataByte)->I80x86Mode = 1;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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DataByte
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);
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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DataByte
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);
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//
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// Disable all of the interrupts except the slave.
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//
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HalpEisaInterrupt1Mask = (UCHAR)~(1 << SLAVE_IRQL_LEVEL);
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
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HalpEisaInterrupt1Mask
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);
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HalpEisaInterrupt2Mask = 0xFF;
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
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HalpEisaInterrupt2Mask
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);
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//
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// Initialize the edge/level register masks to 0 which is the default
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// edge sensitive value.
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//
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HalpEisaInterrupt1Level = 0;
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HalpEisaInterrupt2Level = 0;
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//
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// Restore IRQL level.
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//
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KeLowerIrql(oldIrql);
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//
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// EISA Interrupt to PONCE Enable!!.
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//
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HalpInterruptFromPonce(EISA_DISPATCH_VECTOR ,1); //SNES
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//
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// Initialize the DMA mode registers to a default value.
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// Disable all of the DMA channels except channel 4 which is that
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// cascade of channels 0-3.
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//
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask,
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0x0F
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);
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WRITE_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask,
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0x0E
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);
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charBuffer = READ_REGISTER_UCHAR( &((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus );
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//
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// IOCHK# NMI Disable and Clear
|
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// PERR# PCI System Board Error Disable
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//
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charBuffer = ((charBuffer & 0x03) | 0x0C);
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WRITE_REGISTER_UCHAR( &((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus,
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charBuffer
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);
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//
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// Disbale Bus Timeout,Fail Safe NMI adn Software NMI
|
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//
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charBuffer = READ_REGISTER_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->ExtendedNmiResetControl
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);
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charBuffer = (charBuffer & 0x01);
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WRITE_REGISTER_UCHAR( &((PEISA_CONTROL) HalpEisaControlBase)->ExtendedNmiResetControl,
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charBuffer );
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return(TRUE);
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}
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|
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|
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VOID
|
|
HalpDisableEisaInterrupt(
|
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IN ULONG Vector
|
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)
|
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|
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/*++
|
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|
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Routine Description:
|
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|
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This function Disables the EISA bus specified EISA bus interrupt.
|
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|
|
Arguments:
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Vector - Supplies the vector of the ESIA interrupt that is Disabled.
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Return Value:
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None.
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--*/
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|
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{
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//
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// Calculate the EISA interrupt vector.
|
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//
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Vector -= EISA_VECTORS;
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|
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//
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// Determine if this vector is for interrupt controller 1 or 2.
|
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//
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if (Vector & 0x08) {
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|
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//
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// The interrupt is in controller 2.
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//
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Vector &= 0x7;
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HalpEisaInterrupt2Mask |= (UCHAR) 1 << Vector;
|
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WRITE_REGISTER_UCHAR(
|
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
|
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HalpEisaInterrupt2Mask
|
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);
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|
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} else {
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|
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//
|
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// The interrupt is in controller 1.
|
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//
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|
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Vector &= 0x7;
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|
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HalpEisaInterrupt1Mask |= (ULONG) 1 << Vector;
|
|
WRITE_REGISTER_UCHAR(
|
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&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
|
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HalpEisaInterrupt1Mask
|
|
);
|
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}
|
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|
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}
|
|
//
|
|
//
|
|
//extern KSPIN_LOCK HalpIoMapSpinLock;
|
|
VOID
|
|
HalpEisaMapTransfer(
|
|
IN PADAPTER_OBJECT AdapterObject,
|
|
IN ULONG Offset,
|
|
IN ULONG Length,
|
|
IN BOOLEAN WriteToDevice
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function programs the EISA DMA controller for a transfer.
|
|
|
|
Arguments:
|
|
|
|
Adapter - Supplies the DMA adapter object to be programed.
|
|
|
|
Offset - Supplies the logical address to use for the transfer.
|
|
|
|
Length - Supplies the length of the transfer in bytes.
|
|
|
|
WriteToDevice - Indicates the direction of the transfer.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
PUCHAR BytePtr;
|
|
UCHAR adapterMode;
|
|
KIRQL Irql;
|
|
|
|
BytePtr = (PUCHAR) &Offset;
|
|
|
|
// ASSERT(Offset >= 0x100000); // S009
|
|
|
|
|
|
//
|
|
// grab the spinlock for the system DMA controller
|
|
// Internal Floppy Device used ESC DMA and May be diffirent Onprocessor
|
|
// with EISA Drivers OnProcessor.
|
|
// So grab.
|
|
|
|
KeAcquireSpinLock( &AdapterObject->MasterAdapter->SpinLock, &Irql );
|
|
|
|
|
|
adapterMode = AdapterObject->AdapterMode;
|
|
|
|
//
|
|
// Check to see if this request is for a master I/O card.
|
|
//
|
|
|
|
if (((PDMA_EISA_MODE) &adapterMode)->RequestMode == CASCADE_REQUEST_MODE) {
|
|
|
|
//
|
|
// Set the mode, Disable the request and return.
|
|
//
|
|
|
|
if (AdapterObject->AdapterNumber == 1) {
|
|
|
|
//
|
|
// This request is for DMA controller 1
|
|
//
|
|
|
|
PDMA1_CONTROL dmaControl;
|
|
|
|
dmaControl = AdapterObject->AdapterBaseVa;
|
|
|
|
WRITE_REGISTER_UCHAR( &dmaControl->Mode, adapterMode );
|
|
|
|
//
|
|
// Unmask the DMA channel.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->SingleMask,
|
|
(UCHAR) (DMA_CLEARMASK | AdapterObject->ChannelNumber)
|
|
);
|
|
|
|
} else {
|
|
|
|
//
|
|
// This request is for DMA controller 1
|
|
//
|
|
|
|
PDMA2_CONTROL dmaControl;
|
|
|
|
dmaControl = AdapterObject->AdapterBaseVa;
|
|
|
|
WRITE_REGISTER_UCHAR( &dmaControl->Mode, adapterMode );
|
|
|
|
//
|
|
// Unmask the DMA channel.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->SingleMask,
|
|
(UCHAR) (DMA_CLEARMASK | AdapterObject->ChannelNumber)
|
|
);
|
|
|
|
}
|
|
KeReleaseSpinLock (&AdapterObject->MasterAdapter->SpinLock, Irql);
|
|
return;
|
|
}
|
|
|
|
|
|
//
|
|
// Determine the mode based on the transfer direction.
|
|
//
|
|
|
|
((PDMA_EISA_MODE) &adapterMode)->TransferType = WriteToDevice ?
|
|
WRITE_TRANSFER : READ_TRANSFER;
|
|
|
|
//
|
|
// Determine the controller number based on the Adapter base va.
|
|
//
|
|
|
|
if (AdapterObject->AdapterNumber == 1) {
|
|
|
|
//
|
|
// This request is for DMA controller 1
|
|
//
|
|
|
|
PDMA1_CONTROL dmaControl;
|
|
|
|
dmaControl = AdapterObject->AdapterBaseVa;
|
|
|
|
WRITE_REGISTER_UCHAR( &dmaControl->ClearBytePointer, 0 );
|
|
|
|
WRITE_REGISTER_UCHAR( &dmaControl->Mode, adapterMode );
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseAddress,
|
|
BytePtr[0]
|
|
);
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseAddress,
|
|
BytePtr[1]
|
|
);
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
((PUCHAR) &((PEISA_CONTROL) HalpEisaControlBase)->DmaPageLowPort) +
|
|
(ULONG)AdapterObject->PagePort,
|
|
BytePtr[2]
|
|
);
|
|
|
|
//
|
|
// Write the high page register with zero value. This enable a special mode
|
|
// which allows ties the page register and base count into a single 24 bit
|
|
// address register.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
((PUCHAR) &((PEISA_CONTROL) HalpEisaControlBase)->DmaPageHighPort) +
|
|
(ULONG)AdapterObject->PagePort,
|
|
0
|
|
);
|
|
|
|
|
|
//
|
|
// Notify DMA chip of the length to transfer.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseCount,
|
|
(UCHAR) ((Length - 1) & 0xff)
|
|
);
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseCount,
|
|
(UCHAR) ((Length - 1) >> 8)
|
|
);
|
|
|
|
|
|
//
|
|
// Set the DMA chip to read or write mode; and unmask it.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->SingleMask,
|
|
(UCHAR) (DMA_CLEARMASK | AdapterObject->ChannelNumber)
|
|
);
|
|
|
|
} else {
|
|
|
|
//
|
|
// This request is for DMA controller 1
|
|
//
|
|
|
|
PDMA2_CONTROL dmaControl;
|
|
|
|
dmaControl = AdapterObject->AdapterBaseVa;
|
|
|
|
WRITE_REGISTER_UCHAR( &dmaControl->ClearBytePointer, 0 );
|
|
|
|
WRITE_REGISTER_UCHAR( &dmaControl->Mode, adapterMode );
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseAddress,
|
|
BytePtr[0]
|
|
);
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseAddress,
|
|
BytePtr[1]
|
|
);
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
((PUCHAR) &((PEISA_CONTROL) HalpEisaControlBase)->DmaPageLowPort) +
|
|
(ULONG)AdapterObject->PagePort,
|
|
BytePtr[2]
|
|
);
|
|
|
|
//
|
|
// Write the high page register with zero value. This enable a special mode
|
|
// which allows ties the page register and base count into a single 24 bit
|
|
// address register.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
((PUCHAR) &((PEISA_CONTROL) HalpEisaControlBase)->DmaPageHighPort) +
|
|
(ULONG)AdapterObject->PagePort,
|
|
0
|
|
);
|
|
|
|
|
|
//
|
|
// Notify DMA chip of the length to transfer.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseCount,
|
|
(UCHAR) ((Length - 1) & 0xff)
|
|
);
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->DmaAddressCount[AdapterObject->ChannelNumber]
|
|
.DmaBaseCount,
|
|
(UCHAR) ((Length - 1) >> 8)
|
|
);
|
|
|
|
|
|
//
|
|
// Set the DMA chip to read or write mode; and unmask it.
|
|
//
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&dmaControl->SingleMask,
|
|
(UCHAR) (DMA_CLEARMASK | AdapterObject->ChannelNumber)
|
|
);
|
|
}
|
|
|
|
KeReleaseSpinLock (&AdapterObject->MasterAdapter->SpinLock, Irql);
|
|
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpEnableEisaInterrupt(
|
|
IN ULONG Vector,
|
|
IN KINTERRUPT_MODE InterruptMode
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function enables the EISA bus specified EISA bus interrupt and sets
|
|
the level/edge register to the requested value.
|
|
|
|
Arguments:
|
|
|
|
Vector - Supplies the vector of the EISA interrupt that is enabled.
|
|
|
|
InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
|
|
Latched.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
//
|
|
// Calculate the EISA interrupt vector.
|
|
//
|
|
|
|
Vector -= EISA_VECTORS;
|
|
|
|
//
|
|
// Determine if this vector is for interrupt controller 1 or 2.
|
|
//
|
|
|
|
if (Vector & 0x08) {
|
|
|
|
//
|
|
// The interrupt is in controller 2.
|
|
//
|
|
|
|
Vector &= 0x7;
|
|
|
|
HalpEisaInterrupt2Mask &= (UCHAR) ~(1 << Vector);
|
|
WRITE_REGISTER_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort1,
|
|
HalpEisaInterrupt2Mask
|
|
);
|
|
|
|
//
|
|
// Set the level/edge control register.
|
|
//
|
|
|
|
if (InterruptMode == LevelSensitive) {
|
|
|
|
HalpEisaInterrupt2Level |= (UCHAR) (1 << Vector);
|
|
|
|
} else {
|
|
|
|
HalpEisaInterrupt2Level &= (UCHAR) ~(1 << Vector);
|
|
|
|
}
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2EdgeLevel,
|
|
HalpEisaInterrupt2Level
|
|
);
|
|
|
|
} else {
|
|
|
|
//
|
|
// The interrupt is in controller 1.
|
|
//
|
|
|
|
Vector &= 0x7;
|
|
|
|
HalpEisaInterrupt1Mask &= (UCHAR) ~(1 << Vector);
|
|
WRITE_REGISTER_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort1,
|
|
HalpEisaInterrupt1Mask
|
|
);
|
|
|
|
//
|
|
// Set the level/edge control register.
|
|
//
|
|
|
|
if (InterruptMode == LevelSensitive) {
|
|
|
|
HalpEisaInterrupt1Level |= (UCHAR) (1 << Vector);
|
|
|
|
} else {
|
|
|
|
HalpEisaInterrupt1Level &= (UCHAR) ~(1 << Vector);
|
|
|
|
}
|
|
|
|
WRITE_REGISTER_UCHAR(
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1EdgeLevel,
|
|
HalpEisaInterrupt1Level
|
|
);
|
|
}
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
HalpEisaDispatch(
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is entered as the result of an interrupt being generated
|
|
via the vector that is directly connected to EISA device interrupt.
|
|
|
|
N.B. This interrupt is directly connected and therefore, no argument
|
|
values are defined.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
Returns the value returned from the second level routine.
|
|
|
|
--*/
|
|
|
|
{
|
|
PULONG dispatchCode;
|
|
USHORT interruptVector;
|
|
PKINTERRUPT interruptObject;
|
|
BOOLEAN returnValue;
|
|
|
|
//
|
|
// Read the interrupt vector.
|
|
//
|
|
|
|
interruptVector = (UCHAR)READ_REGISTER_ULONG( (PULONG)&PONCE_CNTL(0)->INTAC);
|
|
|
|
|
|
//
|
|
// If the vector is nonzero, then it is either an EISA interrupt
|
|
// of an NMI interrupt. Otherwise, the interrupt is no longer
|
|
// present.
|
|
//
|
|
|
|
if (interruptVector != 0) {
|
|
|
|
//
|
|
// If the interrupt vector is 0x8000 then the interrupt is an NMI.
|
|
// Otherwise, dispatch the interrupt to the appropriate interrupt
|
|
// handler.
|
|
//
|
|
|
|
// if (interruptVector != 0x8000) {
|
|
//K001 Start
|
|
if(interruptVector == 7|| interruptVector==15 ){
|
|
|
|
PVOID IsrPortAddr;
|
|
UCHAR IsrValue;
|
|
|
|
#define OCW3_READ_ISR 0x0B
|
|
#define OCW3_READ_IRR 0x0A
|
|
|
|
//
|
|
// Master or Slave ?
|
|
//
|
|
IsrPortAddr = (interruptVector == 7) ?
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0:
|
|
&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0;
|
|
|
|
// SetUp to ISR Regsiter
|
|
WRITE_REGISTER_UCHAR( IsrPortAddr, OCW3_READ_ISR );
|
|
// Read ISR Register
|
|
IsrValue=READ_REGISTER_UCHAR( IsrPortAddr );
|
|
// Resume to IRR Register
|
|
WRITE_REGISTER_UCHAR( IsrPortAddr, OCW3_READ_IRR);
|
|
|
|
if(!IsrValue){
|
|
// This is a spurious interrupt!!. No Call Driver.
|
|
goto NocallDriver;
|
|
}
|
|
}
|
|
// K001 End
|
|
|
|
//
|
|
// Mask the upper bits off since the vector is only a byte and
|
|
// dispatch to the secondary interrupt service routine.
|
|
//
|
|
|
|
interruptVector &= 0xff;
|
|
dispatchCode = (PULONG)(PCR->InterruptRoutine[EISA_VECTORS + interruptVector]);
|
|
interruptObject = CONTAINING_RECORD(dispatchCode,
|
|
KINTERRUPT,
|
|
DispatchCode);
|
|
|
|
returnValue = ((PSECONDARY_DISPATCH)interruptObject->DispatchAddress)(interruptObject);
|
|
|
|
NocallDriver:
|
|
|
|
//
|
|
// Dismiss the interrupt in the EISA interrupt controllers.
|
|
//
|
|
// If this is a cascaded interrupt then the interrupt must be
|
|
// dismissed in both controllers.
|
|
//
|
|
|
|
if (interruptVector & 0x08) {
|
|
WRITE_REGISTER_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt2ControlPort0,
|
|
NONSPECIFIC_END_OF_INTERRUPT);
|
|
}
|
|
|
|
WRITE_REGISTER_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->Interrupt1ControlPort0,
|
|
NONSPECIFIC_END_OF_INTERRUPT);
|
|
|
|
// } else {
|
|
// returnValue = HalHandleNMI(NULL, NULL);
|
|
// }
|
|
|
|
} else {
|
|
returnValue = FALSE;
|
|
}
|
|
|
|
return returnValue;
|
|
}
|
|
|
|
|
|
BOOLEAN
|
|
HalHandleNMI(
|
|
IN PKINTERRUPT Interrupt,
|
|
IN PVOID ServiceContext
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is called when an EISA NMI occurs. It print the appropriate
|
|
status information and bugchecks.
|
|
|
|
Arguments:
|
|
|
|
Interrupt - Supplies a pointer to the interrupt object
|
|
|
|
ServiceContext - Bug number to call bugcheck with.
|
|
|
|
Return Value:
|
|
|
|
Returns TRUE.
|
|
|
|
--*/
|
|
{
|
|
KeBugCheck(NMI_HARDWARE_FAILURE);
|
|
return(TRUE);
|
|
}
|