229 lines
6.6 KiB
C
229 lines
6.6 KiB
C
/*
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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r98bdef.h
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Abstract:
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This module is the header file that describes hardware addresses
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for the r98B system.
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Author:
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Revision History:
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--*/
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#ifndef _R98BDEF_
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#define _R98BDEF_
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//
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// Define the size of the DMA translation table.
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//
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#define DMA_TRANSLATION_LIMIT 0x5000 // translation table limit
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//
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// Define the maximum number of map registers allowed per allocation.
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//
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// 2M 2M 2M
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// + PONCE0: PONCE1:
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// | | |
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// | +-------------+
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// +
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// +
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// EISA/ISA
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// Max 3 Slot + Internal Floppy(Use ESC DMA channel #2) = 4 --> 512K *4 = 2M
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//
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// 2M is for 1M Logical Area Reserv!!.
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//
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#define DMA_TRANSLATION_RESERV 0x1000 // 4k /8 = 2M
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#define DMA_REQUEST_LIMIT ((DMA_TRANSLATION_LIMIT-DMA_TRANSLATION_RESERV)/(sizeof(TRANSLATION_ENTRY) * 16))
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//
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//#define DMA_REQUEST_LIMIT (DMA_TRANSLATION_LIMIT/(sizeof(TRANSLATION_ENTRY) * 4))
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//
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// N.B
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// May be 1 page reserved for PCEB Prefetch cycle.
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// It Cause Ponce I/O TLB page fault.
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//
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#define DMA_REQUEST_EISA_LIMIT (DMA_REQUEST_LIMIT-1)
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#define EISA_MAX_DEVICE 3
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#define R98B_MAX_CPU 4
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#define R98B_MAX_MAGELLAN 2
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#define R98B_MAX_PONCE 3 //R100
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#define R98_CPU_R4400 0
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#define R98_CPU_R10000 1
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#define R98_CPU_NUM_TYPE 2
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#define DEVICE_VECTORS 32
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#define EISA_DISPATCH_VECTOR (13+DEVICE_VECTORS)
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#define PARALLEL_VECTOR (14+DEVICE_VECTORS) // Parallel device interrupt vector
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#define NET_VECTOR (29+DEVICE_VECTORS) // ethernet device interrupt vector
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#define SCSI0_VECTOR (31+DEVICE_VECTORS) // SCSI device interrupt vector
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#define SCSI1_VECTOR (30+DEVICE_VECTORS) // SCSI device interrupt vector
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#define UNDEFINE_TLB_VECTOR (35+DEVICE_VECTORS) // TLB undefine address interrupt vector
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#define MOUSE_VECTOR (36+DEVICE_VECTORS) // Mouse device interrupt vector
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#define KEYBOARD_VECTOR (37+DEVICE_VECTORS) // Keyboard device interrupt vector
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#define SERIAL1_VECTOR (38+DEVICE_VECTORS) // Serial device 1 interrupt vector
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#define SERIAL0_VECTOR (39+DEVICE_VECTORS) // Serial device 0 interrupt vector
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#define IPI_VECTOR3 (48+DEVICE_VECTORS) // IPI From #3
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#define IPI_VECTOR2 (49+DEVICE_VECTORS) // IPI From #2
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#define IPI_VECTOR1 (50+DEVICE_VECTORS) // IPI From #1
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#define IPI_VECTOR0 (51+DEVICE_VECTORS) // IPI From #0
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#define PROFILE_VECTOR (56+DEVICE_VECTORS) // Define Profile interrupt vector
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#define CLOCK_VECTOR (57+DEVICE_VECTORS) // Define Clock interrupt vector
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#define EIF_VECTOR (61+DEVICE_VECTORS) // EIF Vector
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#define ECC_1BIT_VECTOR (62+DEVICE_VECTORS) // ECC 1bit Error interrupt vector
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//SNES #define MAXIMUM_DEVICE_VECTORS 43 // IPR Bit 43
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#define MAXIMUM_DEVICE_VECTORS (43+DEVICE_VECTORS)
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//
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// Define EISA device interrupt vectors.
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//
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#define EISA_VECTORS 16
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#define MAXIMUM_EISA_VECTORS (15 + EISA_VECTORS) // maximum EISA vector
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#define INT0_LEVEL 3 // PCR->InterruptRoutine[3]
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#define INT1_LEVEL 4 // PCR->InterruptRoutine[4]
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#define INT2_LEVEL 5 // PCR->InterruptRoutine[5]
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#define INT3_LEVEL 6 // PCR->InterruptRoutine[6]
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#define INT4_LEVEL 7 // PCR->InterruptRoutine[7]
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#define INT5_LEVEL 8 // PCR->InterruptRoutine[8]
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#define EISA_LEVEL INT0_LEVEL // R98B/R98A same
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#define NUMBER_OF_INT 6
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//
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// Define the minimum and maximum system time increment values in 100ns units.
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//
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#define MAXIMUM_INCREMENT (10 * 1000 * 10)
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#define MINIMUM_INCREMENT (1 * 1000 * 10)
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//
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//
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// Time increment in 1us units
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// The Columbus chip clock frequency is 1.024 MHZ
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#define COLUMBUS_CLOCK_FREQUENCY 1024
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// The hardware expects that this value is decremented by one
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#define CLOCK_INTERVAL (((MAXIMUM_INCREMENT * COLUMBUS_CLOCK_FREQUENCY) / 1000) / 10)
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//
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// 1 Interval != 1 micro sec. ==> 1 Interval = 1/1.024 microsec
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// 1 Count (H/W register) is 1/1.024 microsec
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//
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#define DEFAULT_PROFILETIMER_INTERVAL (500 * 10) // = 500 us (100ns units)
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#define MAXIMUM_PROFILETIMER_INTERVAL (64000 * 10) // = 64 ms (100ns units)
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#define DEFAULT_PROFILETIMER_COUNT (MAXIMUM_PROFILETIMER_INTERVAL / 10) //Set count value
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#define MINIMUM_PROFILETIMER_INTERVAL (40 * 10) // = 40 us (100ns units)
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//
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// Chip Set Addr
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//
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#define COLUMNBS_LPHYSICAL_BASE 0x19800000
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#define COLUMNBS_GPHYSICAL_BASE 0x19000000
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#define PONCE_PHYSICAL_BASE 0x1a000000
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#define MAGELLAN_0_PHYSICAL_BASE 0x18000000
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#define MAGELLAN_1_PHYSICAL_BASE 0x18020000
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#define LOCALDEV_PHYSICAL_BASE 0x1f0f0000
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#define EISA_CONTROL_PHYSICAL_BASE 0x1C000000 // physical base of EISA control
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#define SERIAL0_PHYSICAL_BASE (EISA_CONTROL_PHYSICAL_BASE+0x3f8) //serial
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#define KEYBOARD_PHYSICAL_BASE (EISA_CONTROL_PHYSICAL_BASE+0x60) //serial
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//
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// R98X have 2 I/O Area(per Ponce). But Not Use apper area!!.
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// used lower area only.
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//
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#define PCI_CNTL_PHYSICAL_BASE 0x1c000000
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#define PCI_MAX_CNTL_SIZE 0x400000 //4M
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//
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// R98X PCI Memory area size 1Gmax. Not 4G!!.
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//
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#define PCI_MAX_MEMORY_SIZE 0x40000000 //1G max
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#define PCI_MEMORY_PHYSICAL_BASE_LOW 0x40000000
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#define PCI_MEMORY_PHYSICAL_BASE_HIGH 0x1
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// Ponce #0 have EISA/ISA.
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//
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#define EISA_MEMORY_PHYSICAL_BASE_LOW PCI_MEMORY_PHYSICAL_BASE_LOW
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#define EISA_MEMORY_PHYSICAL_BASE_HIGH PCI_MEMORY_PHYSICAL_BASE_HIGH
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#define EISA_CNTL_PHYSICAL_BASE PCI_CNTL_PHYSICAL_BASE
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#define EISA_CNTL_PHYSICAL_BASE_LOW PCI_CNTL_PHYSICAL_BASE
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#define EISA_CNTL_PHYSICAL_BASE_HIGH 0x0
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//
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// RTC Register
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//
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#define RTCLOCK_PHYSICAL_BASE 0x1c000071 // physical base of realtime clock
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//
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// Actually nvram start at
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//
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#define NVRAM_ACTUALLY_PHYSICAL_BASE 0x1F080000 // physical base of NonVolatile RAM
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//
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// s/w read/write ble erea this address
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//
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#define NVRAM_PHYSICAL_BASE 0x1F082000 // physical base of NonVolatile RAM For S/W
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#define NVRAM_MEMORY_BASE (KSEG1_BASE + NVRAM_PHYSICAL_BASE)
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//
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// R4400 cause register.
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//
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#define CAUSE_INT_PEND_BIT 0xA //Int0 base
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//
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// Local Device Function Operation.
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//
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#define LOCALDEV_OP_READ 0x1
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#define LOCALDEV_OP_WRITE 0x0
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//
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// Local Device MRC Function Operation.
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//
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#define MRC_OP_DUMP_ONLY_NMI 0x1
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#define MRC_OP_DUMP_AND_POWERSW_NMI 0x0
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//
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// ECC 1bit/Multi bit Error Operation.
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//
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#define ECC_1BIT_ENABLE 0xfffffff5
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#define ECC_MULTI_ENABLE 0xfffffffa
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#define ECC_ERROR_DISABLE 0x0000000f
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#define ECC_ERROR_ENABLE 0xfffffff0
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#define MAGELLAN_ERRI_OFFSET 0x2330
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//
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// Define cause register read macro
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//
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#define READ_CAUSE_REGISTER(reg) \
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.set noreorder; \
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.set noat; \
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mfc0 reg,cause; \
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nop; \
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nop; \
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.set at; \
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.set reorder;
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#endif // _R98BDEF_
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