650 lines
20 KiB
C
650 lines
20 KiB
C
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#ifndef _R98BREG_
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#define _R98BREG_
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#include <r98bdef.h>
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//
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// R98B Chip Set Register Define
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//
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//
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// Define COLUMBS register structure.
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//
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typedef struct _COLUMNBUS_REGISTER {
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ULONG Long;
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ULONG Fill;
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} COLUMNBUS_REGISTER, *PCOLUMNBUS_REGISTER;
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typedef struct _COLUMNBUS_LARGE_REGISTER {
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// ULONG Low;
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// ULONG High;
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ULONGLONG Llong;
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} COLUMNBUS_LARGE_REGISTER, *PCOLUMNBUS_LARGE_REGISTER;
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typedef volatile struct _COLUMNBUS_REGISTERS {
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// offset(H)
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COLUMNBUS_LARGE_REGISTER IPR; // 0x0
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COLUMNBUS_LARGE_REGISTER MKR; // 0x8
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COLUMNBUS_LARGE_REGISTER IPRR; // 0x10
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COLUMNBUS_REGISTER IPSR; // 0x18
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COLUMNBUS_REGISTER MKRR; // 0x20
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COLUMNBUS_REGISTER MKSR; // 0x28
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COLUMNBUS_REGISTER NMIR; // 0x30
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COLUMNBUS_REGISTER NMIRST; // 0x38
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COLUMNBUS_REGISTER TMSR1; // 0x40
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COLUMNBUS_REGISTER TMR1; // 0x48
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COLUMNBUS_REGISTER TOVCT1; // 0x50
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COLUMNBUS_REGISTER TMCR1; // 0x58
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COLUMNBUS_REGISTER TMSR2; // 0x60
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COLUMNBUS_REGISTER TMR2; // 0x68
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COLUMNBUS_REGISTER TOVCT2; // 0x70
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COLUMNBUS_REGISTER TMCR2; // 0x78
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COLUMNBUS_REGISTER WDTSR; // 0x80
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COLUMNBUS_REGISTER WDT; // 0x88
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COLUMNBUS_REGISTER WDTCR; // 0x90
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COLUMNBUS_REGISTER IRLEV; // 0x98
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COLUMNBUS_REGISTER Reserved1[12]; // 0xa0-0xF8
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COLUMNBUS_REGISTER SYNDM; // 0x100
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COLUMNBUS_REGISTER SDMRST; // 0x108
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COLUMNBUS_REGISTER Reserved2[14]; // 0x110
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COLUMNBUS_REGISTER STCON; // 0x180
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COLUMNBUS_REGISTER STSAD; // 0x188
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COLUMNBUS_REGISTER STADMK; // 0x190
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COLUMNBUS_REGISTER STDATH; // 0x198
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COLUMNBUS_REGISTER STDATL; // 0x1a0
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COLUMNBUS_REGISTER Reserved21; // 0x1a8
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COLUMNBUS_REGISTER Reserved3[10]; // 0x1b0 - 0x1f8
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COLUMNBUS_REGISTER CTAddr; // 0x200
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COLUMNBUS_REGISTER CTDataA; // 0x208
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COLUMNBUS_REGISTER CTDataB; // 0x210
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COLUMNBUS_REGISTER CTCTL; // 0x218
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COLUMNBUS_REGISTER EVCNT1H; // 0x220
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COLUMNBUS_REGISTER EVCNT1L; // 0x228
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COLUMNBUS_REGISTER EVCNTCR1; // 0x230
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COLUMNBUS_REGISTER Reserved4[25]; // 0x238- 0x2F8
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COLUMNBUS_REGISTER CNFG; // 0x300
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COLUMNBUS_REGISTER DISN; // 0x208
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COLUMNBUS_REGISTER REVR; // 0x310
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COLUMNBUS_REGISTER AERR; // 0x318
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COLUMNBUS_REGISTER FERR; // 0x320
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COLUMNBUS_REGISTER ERRMK; // 0x328
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COLUMNBUS_REGISTER ERRI; // 0x330
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COLUMNBUS_REGISTER ERRST; // 0x338
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COLUMNBUS_REGISTER NMIM; // 0x340
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COLUMNBUS_REGISTER EAHI; // 0x348
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COLUMNBUS_REGISTER EALI; // 0x350
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COLUMNBUS_REGISTER AERR2; // 0x358
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COLUMNBUS_REGISTER FERR2; // 0x360
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COLUMNBUS_REGISTER ERRMK2; // 0x368
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COLUMNBUS_REGISTER ERRI2; // 0x370
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COLUMNBUS_REGISTER ERRST2; // 0x378
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COLUMNBUS_REGISTER NMIM2; // 0x380
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COLUMNBUS_REGISTER STSR; // 0x388
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COLUMNBUS_REGISTER EVCNT0H; // 0x390
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COLUMNBUS_REGISTER EVCNT0L; // 0x398
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COLUMNBUS_REGISTER EVCNTCR0; // 0x3a0
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COLUMNBUS_REGISTER MODE; // 0x3a8
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COLUMNBUS_REGISTER Reserved5[10]; // 0x3b0- 0x3f8
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COLUMNBUS_REGISTER RRMT0H; // 0x400
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COLUMNBUS_REGISTER RRMT0L; // 0x408
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COLUMNBUS_REGISTER RRMT1H; // 0x410
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COLUMNBUS_REGISTER RRMT1L; // 0x418
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COLUMNBUS_REGISTER RRMT2H; // 0x420
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COLUMNBUS_REGISTER RRMT2L; // 0x428
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COLUMNBUS_REGISTER RRMT3H; // 0x430
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COLUMNBUS_REGISTER RRMT3L; // 0x438
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COLUMNBUS_REGISTER RRMT4H; // 0x440
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COLUMNBUS_REGISTER RRMT4L; // 0x448
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COLUMNBUS_REGISTER RRMT5H; // 0x450
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COLUMNBUS_REGISTER RRMT5L; // 0x458
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COLUMNBUS_REGISTER RRMT6H; // 0x460
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COLUMNBUS_REGISTER RRMT6L; // 0x468
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COLUMNBUS_REGISTER RRMT7H; // 0x470
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COLUMNBUS_REGISTER RRMT7L; // 0x478
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COLUMNBUS_REGISTER RRMT8H; // 0x480
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COLUMNBUS_REGISTER RRMT8L; // 0x488
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COLUMNBUS_REGISTER RRMT9H; // 0x490
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COLUMNBUS_REGISTER RRMT9L; // 0x498
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COLUMNBUS_REGISTER RRMT10H; // 0x4a0
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COLUMNBUS_REGISTER RRMT10L; // 0x4a8
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COLUMNBUS_REGISTER RRMT11H; // 0x4b0
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COLUMNBUS_REGISTER RRMT11L; // 0x4b8
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COLUMNBUS_REGISTER RRMT12H; // 0x4c0
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COLUMNBUS_REGISTER RRMT12L; // 0x4c8
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COLUMNBUS_REGISTER RRMT13H; // 0x4d0
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COLUMNBUS_REGISTER RRMT13L; // 0x4d8
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COLUMNBUS_REGISTER RRMT14H; // 0x4e0
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COLUMNBUS_REGISTER RRMT14L; // 0x4e8
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COLUMNBUS_REGISTER RRMT15H; // 0x4f0
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COLUMNBUS_REGISTER RRMT15L; // 0x4f8
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COLUMNBUS_REGISTER HPT0; // 0x500
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COLUMNBUS_REGISTER HPT1; // 0x508
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COLUMNBUS_REGISTER HPT2; // 0x510
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COLUMNBUS_REGISTER HPT3; // 0x518
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COLUMNBUS_REGISTER HPT4; // 0x520
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COLUMNBUS_REGISTER HPT5; // 0x528
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COLUMNBUS_REGISTER HPT6; // 0x530
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COLUMNBUS_REGISTER HPT7; // 0x538
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COLUMNBUS_REGISTER HPT8; // 0x540
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COLUMNBUS_REGISTER HPT9; // 0x548
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COLUMNBUS_REGISTER NRTY1; // 0x550
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COLUMNBUS_REGISTER Reserved6[5]; // 0x558-0x57f
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COLUMNBUS_REGISTER IntIR; // 0x580
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COLUMNBUS_REGISTER RCIR; // 0x588
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COLUMNBUS_REGISTER TCIR; // 0x590
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COLUMNBUS_REGISTER HPTIR; // 0x598
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COLUMNBUS_REGISTER CBIR; // 0x5a0
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COLUMNBUS_REGISTER Reserved7[11]; // 0x5a8-0x5f8
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COLUMNBUS_REGISTER SIOCNT; // 0x600
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COLUMNBUS_REGISTER SIODAT; // 0x608
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COLUMNBUS_REGISTER ERRNOD; // 0x610
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COLUMNBUS_REGISTER ERNDRS; // 0x618
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COLUMNBUS_REGISTER Reserved8[28]; // 0x620-0x6f8
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COLUMNBUS_REGISTER ARTYCT; // 0x700
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COLUMNBUS_REGISTER DRTYCT; // 0x708
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COLUMNBUS_REGISTER TOSR; // 0x710
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COLUMNBUS_REGISTER NRTY2; // 0x718
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} COLUMNBUS_REGISTERS, *PCOLUMNBUS_REGISTERS;
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#define COLUMNBS_GADDR_SHIFT 12
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//
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// How to Access Local Area
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//
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#define COLUMNBS_LCNTL ((volatile PCOLUMNBUS_REGISTERS)(KSEG1_BASE | COLUMNBS_LPHYSICAL_BASE))
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//
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// How to Access Gloabal Area
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// N.B parameter is Node
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// Columbs #0: NODE 4
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// Columbs #1: NODE 5
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// Columbs #2: NODE 6
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// Columbs #3: NODE 7
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//
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#define COLUMNBS_GCNTL( Node ) ((volatile PCOLUMNBUS_REGISTERS)(KSEG1_BASE | \
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COLUMNBS_GPHYSICAL_BASE | \
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((Node) << COLUMNBS_GADDR_SHIFT)))
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//
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// IPR Register
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//
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#define NUMBER_OF_IPR_BIT 64
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//
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// TMCRX Register Bit Define
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//
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#define TIMER_NOOP 0x00
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#define TIMER_STOP 0x1
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#define TIMER_START 0x2
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#define TIMER_RELOAD_START 0x3
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//
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// TCIR Register Bit Define
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//
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#define TCIR_CLOCK_CMD_SHIFT 26
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#define TCIR_PROFILE_CMD_SHIFT 24
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#define TCIR_ALL_CLOCK_RESTART (TIMER_RELOAD_START << TCIR_CLOCK_CMD_SHIFT)
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//
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// STSR Register Bit Define
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//
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#define STSR_EIF 0x80000000
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#define STSR_EIFMK 0x40000000
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#define STSR_FREEZ 0x20000000
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#define STSR_NMIMK 0x08000000
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#define STSR_NVWINH 0x04000000
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#define STSR_NVBINH 0x02000000
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#define STSR_WEIF 0x00800000
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#define STSR_WEIFMK 0x00400000
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#define STSR_WFREEZ 0x00200000
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#define STSR_WNMIMK 0x00080000
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#define STSR_WNVWINH 0x00040000
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#define STSR_WNVBINH 0x00020000
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#define STSR_CLBER 0x00008000
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#define STSR_WAMRST 0x00004000
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#define STSR_EFIFOEMP 0x00000800
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#define STSR_ITVPND 0x00000400
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#define STSR_WRPND 0x00000200
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#define STSR_CTEXE 0x00000100
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#define STSR_MPU 0x00000080
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#define STSR_ENDIAN 0x00000040
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#define STSR_SCSIZE 0x0000001c
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//
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// IntIR Register define
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//
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#define IntIR_REQUEST_IPI 0x80000000 // Interrupt Kick
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#define IntIR_CODE_BIT 24 // Bit 24-30 is interrupt code
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#define ATLANTIC_CODE_IPI_FROM_CPU0 0xC
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#define ToNODE4 0x00080000 // to CPU#0
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#define ToNODE5 0x00040000 // to CPU#1
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#define ToNODE6 0x00020000 // to CPU#2
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#define ToNODE7 0x00010000 // to CPU#3
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//
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// ERRNOD Register define
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//
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#define ERRNOD_NODE0 0x0008 //PONCE#0
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#define ERRNOD_NODE1 0x0004 //PONCE#1
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#define ERRNOD_NODE4 0x8000 //CPU#0
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#define ERRNOD_NODE5 0x4000 //CPU#1
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#define ERRNOD_NODE6 0x2000 //CPU#2
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#define ERRNOD_NODE7 0x1000 //CPU#3
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#define ERRNOD_NODE8 0x0080 //Magellan#0
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#define ERRNOD_NODE9 0x0040 //Magellan#1
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#define ERRNOD_EISANMI 0x0200 //EISANMI
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#define ERRNOD_ALARM 0x0100 //ALARM
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//
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// CNFG Register define
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//
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//
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#define CNFG_CONNECT0_PONCE0 0x80000000 //it is Ponce 0
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#define CNFG_CONNECT1_PONCE1 0x40000000 //it is Ponce 1
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#define CNFG_CONNECT4_CPU0 0x08000000 //it is CPU #0
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#define CNFG_CONNECT4_CPU1 0x04000000 //it is CPU #1
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#define CNFG_CONNECT4_CPU2 0x02000000 //it is CPU #2
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#define CNFG_CONNECT4_CPU3 0x01000000 //it is CPU #3
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#define CNFG_CONNECT4_MAGELLAN0 0x00800000 //it is MAGELLAN 0
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#define CNFG_CONNECT4_MAGELLAN1 0x00400000 //it is MAGELLAN 1
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#define ERRNOD_ALLNODE ((ERRNOD_NODE0|ERRNOD_NODE1| \
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ERRNOD_NODE4|ERRNOD_NODE5| \
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ERRNOD_NODE6|ERRNOD_NODE7| \
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ERRNOD_NODE8|ERRNOD_NODE9))
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//
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// NMIR Register define
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//
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//
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#define NMIR_EXNMI 0x0008 //DUMP Key
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#define NMIR_WDTOV 0x0004 //watch dog timer
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#define NMIR_CLBNMI 0x0002 //COLUMBUS Internal
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#define NMIR_UNANMI 0x0001 //F/W,S/W
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//
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// ********************************************************************
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// PONCE Register
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//
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typedef struct _PONCE_REGISTER {
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ULONG Long;
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ULONG Fill;
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}PONCE_REGISTER,*PPONCE_REGISTER;
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//
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// PONCE Register define
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//
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typedef volatile struct _PONCE_REGISTERS {
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PONCE_REGISTER INTAC; //0x000
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PONCE_REGISTER CONFA; //0x008
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PONCE_REGISTER CONFD; //0x010
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PONCE_REGISTER PTBSR; //0x018
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PONCE_REGISTER Reserve0; //0x020
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PONCE_REGISTER PTLMR; //0x028
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PONCE_REGISTER Reserve1; //0x030
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PONCE_REGISTER TFLSR; //0x038
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PONCE_REGISTER Reserve2; //0x040
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PONCE_REGISTER TLBTG[8]; //0x048
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PONCE_REGISTER Reserve3[9]; //0x088
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PONCE_REGISTER ADCFR0; //0x0d0
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PONCE_REGISTER Reserve4; //0x0d8
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PONCE_REGISTER PMODR; //0x0e0
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PONCE_REGISTER Reserve5[3]; //0x0e8
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PONCE_REGISTER VENID; //0x100
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PONCE_REGISTER DEVID; //0x108
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PONCE_REGISTER PCMDN; //0x110
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PONCE_REGISTER PSTAT; //0x118
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PONCE_REGISTER REVID; //0x120
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PONCE_REGISTER CLASS; //0x128
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PONCE_REGISTER LTNCY; //0x130
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PONCE_REGISTER Reserve6[2]; //0x138
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PONCE_REGISTER TLBDT[8]; //0x148
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PONCE_REGISTER Reserve7[0xf]; //0x188
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PONCE_REGISTER INTRG; //0x200
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PONCE_REGISTER INTM; //0x208
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PONCE_REGISTER INTPH; //0x210
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PONCE_REGISTER INTPL; //0x218
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PONCE_REGISTER INTTG[11]; //0x220
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PONCE_REGISTER INTCD[11]; //0x278 - 0x2c8
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PONCE_REGISTER CAFLS; //0x2d0
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PONCE_REGISTER CASEL; //0x2d8
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PONCE_REGISTER CADATH; //0x2e0
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PONCE_REGISTER CADATL; //0x2e8
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PONCE_REGISTER CATAGH; //0x2f0
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PONCE_REGISTER CATAGL; //0x2f8
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PONCE_REGISTER Reserve8[2]; //0x300 0x308
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PONCE_REGISTER REVR; //0x310
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PONCE_REGISTER AERR; //0x318
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PONCE_REGISTER FERR; //0x320
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PONCE_REGISTER ERRM; //0x328
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PONCE_REGISTER ERRI; //0x330
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PONCE_REGISTER ERRST; //0x338
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PONCE_REGISTER Reserve9; //0x340
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PONCE_REGISTER EAHI; //0x348
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PONCE_REGISTER EALI; //0x350
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PONCE_REGISTER Reservea[21]; //0x358
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PONCE_REGISTER RRMT0H; //0x400
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PONCE_REGISTER RRMT0L; //0x408
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PONCE_REGISTER RRMT1H; //0x410
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PONCE_REGISTER RRMT1L; //0x418
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PONCE_REGISTER RRMT2H; //0x420
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PONCE_REGISTER RRMT2L; //0x428
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PONCE_REGISTER RRMT3H; //0x430
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PONCE_REGISTER RRMT3L; //0x438
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PONCE_REGISTER RRMT4H; //0x440
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PONCE_REGISTER RRMT4L; //0x448
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PONCE_REGISTER RRMT5H; //0x450
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PONCE_REGISTER RRMT5L; //0x458
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PONCE_REGISTER RRMT6H; //0x460
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PONCE_REGISTER RRMT6L; //0x468
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PONCE_REGISTER RRMT7H; //0x470
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PONCE_REGISTER RRMT7L; //0x478
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PONCE_REGISTER Reserveb[16]; //0x480
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PONCE_REGISTER HPT0; //0x500
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PONCE_REGISTER HPT1; //0x508
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PONCE_REGISTER HPT2; //0x510
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PONCE_REGISTER HPT3; //0x518
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PONCE_REGISTER HPT4; //0x520
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PONCE_REGISTER HPT5; //0x528
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PONCE_REGISTER HPT6; //0x530
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PONCE_REGISTER HPT7; //0x538
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PONCE_REGISTER HPT8; //0x540
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PONCE_REGISTER HPT9; //0x548
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PONCE_REGISTER Reservec[54]; //0x550
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PONCE_REGISTER ANRC; //0x700
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PONCE_REGISTER DNRC; //0x708
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PONCE_REGISTER ABRMT; //0x710
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PONCE_REGISTER Reserved; //0x718
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PONCE_REGISTER ANKRL2; //0x720
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PONCE_REGISTER DISN; //0x728
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PONCE_REGISTER Reserved2[26]; //0x730
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PONCE_REGISTER PAERR; //0x800
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PONCE_REGISTER PFERR; //0x808
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PONCE_REGISTER PERRM; //0x810
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PONCE_REGISTER PERRI; //0x818
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PONCE_REGISTER PERST; //0x820
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PONCE_REGISTER PTOL; //0x828
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PONCE_REGISTER Reservee; //0x830
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PONCE_REGISTER PNRT; //0x838
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PONCE_REGISTER PRCOL; //0x840
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PONCE_REGISTER PMDL; //0x848
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PONCE_REGISTER PRST; //0x850
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PONCE_REGISTER ERITTG[3]; //0x858,0x860,0x868
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PONCE_REGISTER ERITCD[3]; //0x870,0x878,0x880
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PONCE_REGISTER Reservef[0xf]; //0x888
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PONCE_REGISTER TRSM; //0x900
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PONCE_REGISTER TROM; //0x908
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PONCE_REGISTER TRAC; //0x910
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PONCE_REGISTER TRDS; //0x918
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PONCE_REGISTER TRDE; //0x920
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PONCE_REGISTER TRDO; //0x928
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PONCE_REGISTER Reserve10[2]; //0x930,0x938
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PONCE_REGISTER INTSM; //0x940
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}PONCE_REGISTERS,*PPONCE_REGISTERS;
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#define PONCE_ADDR_SHIFT 12
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#define PONCE_MAX 3 //R98[a-z] max Ponce is 3.
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#define PONCE_ADDR_MASK (PONCE_MAX << PONCE_ADDR_SHIFT)
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#define PONCE_IOADDR_SHIFT 22
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//
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// Ponce max pci device( Never PCI_MAX_DEVICES)
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//
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#define PONCE_PCI_MAX_DEVICES 21
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//
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// I/O TLB
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//
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#define PONCE_MAX_IOTLB_ENTRY 8
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//
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// PONCE Register Access
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//
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#define PONCE_CNTL_BASE_SHIFT 12
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#define PONCE_CNTL(Ponce) ((volatile PPONCE_REGISTERS) \
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(KSEG1_BASE | PONCE_PHYSICAL_BASE | \
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((Ponce) << PONCE_ADDR_SHIFT)))
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//
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// PAERR,PFERR,PERRM,PERRI,PERST Registers Bit Define
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// Bit31 - Bit21 only other is MBZ
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//
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#define PONCE_PXERR_PPERM 0x80000000
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#define PONCE_PXERR_PPERS 0x40000000
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#define PONCE_PXERR_PPERN 0x20000000
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#define PONCE_PXERR_PSERR 0x10000000
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#define PONCE_PXERR_PPCER 0x08000000
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#define PONCE_PXERR_PTOUT 0x04000000
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#define PONCE_PXERR_PROER 0x02000000
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#define PONCE_PXERR_PMDER 0x01000000
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#define PONCE_PXERR_PMABS 0x00800000
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#define PONCE_PXERR_PTABS 0x00400000
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#define PONCE_PXERR_PTABO 0x00200000
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#define PONCE_PXERR_MASK 0xFFE00000
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//
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// AERR,FERR,ERRM,ERRI,ERRST Registers Bit Define
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// Bit31 - Bit9 only other is RFU
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//
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#define PONCE_XERR_ACPBERR 0x80000000
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#define PONCE_XERR_RRIBERR 0x40000000
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#define PONCE_XERR_ZERO 0x20000000
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#define PONCE_XERR_SNDERR 0x10000000
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#define PONCE_XERR_ABTMOT 0x08000000
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#define PONCE_XERR_ABWTLT 0x04000000
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#define PONCE_XERR_ABRTYOV 0x02000000
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#define PONCE_XERR_ABRERTOV 0x01000000
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#define PONCE_XERR_NERRR 0x00800000
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#define PONCE_XERR_UNADER 0x00400000
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#define PONCE_XERR_UNCMDER 0x00200000
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#define PONCE_XERR_BWDPER 0x00100000
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#define PONCE_XERR_SLWDPER 0x00080000
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#define PONCE_XERR_BDRPER 0x00040000
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#define PONCE_XERR_SLDRPER 0x00020000
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#define PONCE_XERR_ADPER 0x00010000
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#define PONCE_XERR_CDPER 0x00008000
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#define PONCE_XERR_RRPER 0x00004000
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#define PONCE_XERR_CHICT 0x00002000
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#define PONCE_XERR_STATUMT 0x00001000
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#define PONCE_XERR_TUAER 0x00000800
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#define PONCE_XERR_TIVER 0x00000400
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#define PONCE_XERR_MOVER 0x00000200
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#define PONCE_XERR_MASK 0xDFFFFE00
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//
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// Dummy Read Registers Index
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//
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typedef enum _INTRG{
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PCIINTD,
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PCIINTC,
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PCIINTB,
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PCIINTA3,
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PCIINTA2,
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PCIINTA1,
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PCIINTA0,
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INTSB1,
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INTSB0,
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INTSA1,
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INTSA0,
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}INTRG,*PINTRG;
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|
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//
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// Dummy Read Registers
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//
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//
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typedef enum _DUMMY_ADDR{
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DUMMY_A0,
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DUMMY_A1,
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DUMMY_A2,
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DUMMY_A3,
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DUMMY_A4,
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DUMMY_A5
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}DUMMY_ADDR,*PDUMMY_ADDR;
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#define PONCE0 0x0
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#define PONCE1 0x1
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|
|
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//
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// Magellan registers
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//
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//
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typedef struct _MAGELLAN_REGISTER {
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ULONG Long;
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ULONG Fill;
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}MAGELLAN_REGISTER,*PMAGELLAN_REGISTER;
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//
|
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// PONCE Register define
|
|
//
|
|
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typedef volatile struct _MAGELLAN_REGISTERS{
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MAGELLAN_REGISTER ADEC0; //0x0000
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MAGELLAN_REGISTER ADEC1; //0x0008
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MAGELLAN_REGISTER ADEC2; //0x0010
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MAGELLAN_REGISTER ADEC3; //0x0018
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MAGELLAN_REGISTER Reserved0[0x1c]; //0x0020
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|
MAGELLAN_REGISTER EAADEC0; //0x0100
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MAGELLAN_REGISTER EAADEC1; //0x0108
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MAGELLAN_REGISTER Reserved1[0x1de]; //0x0110
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MAGELLAN_REGISTER INLC; //0x1000
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MAGELLAN_REGISTER RCFD; //0x1008
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MAGELLAN_REGISTER Reserved2; //0x1010
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MAGELLAN_REGISTER DTRG; //0x1018
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MAGELLAN_REGISTER Reserved4[0x5d]; //0x1020
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MAGELLAN_REGISTER DISN; //0x1308
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MAGELLAN_REGISTER REVR; //0x1310
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|
MAGELLAN_REGISTER Reserved5[0x3d]; //0x1318
|
|
MAGELLAN_REGISTER HPT0; //0x1500
|
|
MAGELLAN_REGISTER HPT1; //0x1508
|
|
MAGELLAN_REGISTER HPT2; //0x1510
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|
MAGELLAN_REGISTER HPT3; //0x1518
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|
MAGELLAN_REGISTER HPT4; //0x1520
|
|
MAGELLAN_REGISTER HPT5; //0x1528
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|
MAGELLAN_REGISTER HPT6; //0x1530
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|
MAGELLAN_REGISTER HPT7; //0x1538
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|
MAGELLAN_REGISTER HPT8; //0x1540
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|
MAGELLAN_REGISTER HPT9; //0x1548
|
|
MAGELLAN_REGISTER Reserved6[0x1b9]; //0x1550
|
|
MAGELLAN_REGISTER AERR; //0x2318
|
|
MAGELLAN_REGISTER FERR; //0x2320
|
|
MAGELLAN_REGISTER ERRM; //0x2328
|
|
MAGELLAN_REGISTER ERRI; //0x2330
|
|
MAGELLAN_REGISTER ERRST; //0x2338
|
|
MAGELLAN_REGISTER Reserved7; //0x2340
|
|
MAGELLAN_REGISTER EIFM; //0x2348
|
|
MAGELLAN_REGISTER EAHI; //0x2350
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|
MAGELLAN_REGISTER EALI; //0x2358
|
|
MAGELLAN_REGISTER Reserved8[2]; //0x2360
|
|
MAGELLAN_REGISTER CKE0; //0x2370
|
|
MAGELLAN_REGISTER Reserved9; //0x2378
|
|
MAGELLAN_REGISTER SECT; //0x2380
|
|
MAGELLAN_REGISTER STS1; //0x2388
|
|
MAGELLAN_REGISTER RSRG; //0x2390
|
|
MAGELLAN_REGISTER DATM; //0x2398
|
|
MAGELLAN_REGISTER DSRG; //0x23a0
|
|
MAGELLAN_REGISTER SDLM; //0x23a8
|
|
MAGELLAN_REGISTER Reserveda[0x18a]; //0x23b0
|
|
MAGELLAN_REGISTER SDCR; //0x3000
|
|
MAGELLAN_REGISTER Reservedb[0x27f]; //0x3008
|
|
MAGELLAN_REGISTER RRMTH0; //0x4400
|
|
MAGELLAN_REGISTER RRMTL0; //0x4408
|
|
MAGELLAN_REGISTER RRMTH1; //0x4410
|
|
MAGELLAN_REGISTER RRMTL1; //0x4418
|
|
MAGELLAN_REGISTER RRMTH2; //0x4420
|
|
MAGELLAN_REGISTER RRMTL2; //0x4428
|
|
MAGELLAN_REGISTER RRMTH3; //0x4430
|
|
MAGELLAN_REGISTER RRMTL3; //0x4438
|
|
MAGELLAN_REGISTER RRMTH4; //0x4440
|
|
MAGELLAN_REGISTER RRMTL4; //0x4448
|
|
MAGELLAN_REGISTER RRMTH5; //0x4450
|
|
MAGELLAN_REGISTER RRMTL5; //0x4458
|
|
MAGELLAN_REGISTER RRMTH6; //0x4460
|
|
MAGELLAN_REGISTER RRMTL6; //0x4468
|
|
MAGELLAN_REGISTER RRMTH7; //0x4470
|
|
MAGELLAN_REGISTER RRMTL7; //0x4478
|
|
MAGELLAN_REGISTER Reservedc[0x170]; //0x4480
|
|
MAGELLAN_REGISTER PCM; //0x5000
|
|
MAGELLAN_REGISTER PCH; //0x5008
|
|
MAGELLAN_REGISTER Reservedd[0x1e]; //0x5010
|
|
MAGELLAN_REGISTER TMOD; //0x5100
|
|
MAGELLAN_REGISTER TRA; //0x5108
|
|
MAGELLAN_REGISTER Reservede[0x1e]; //0x5110
|
|
MAGELLAN_REGISTER TRM0[0x20]; //0x5200
|
|
MAGELLAN_REGISTER TRM1[0x20]; //0x5300
|
|
MAGELLAN_REGISTER TRM2[0x20]; //0x5400
|
|
}MAGELLAN_REGISTERS,*PMAGELLAN_REGISTERS;
|
|
|
|
|
|
|
|
//
|
|
// How to Access Local Area
|
|
//
|
|
#define MAGELLAN_0_CNTL ((volatile PMAGELLAN_REGISTERS)(KSEG1_BASE | MAGELLAN_0_PHYSICAL_BASE))
|
|
#define MAGELLAN_1_CNTL ((volatile PMAGELLAN_REGISTERS)(KSEG1_BASE | MAGELLAN_1_PHYSICAL_BASE))
|
|
|
|
#define MAGELLAN_X_CNTL(x) ((volatile PMAGELLAN_REGISTERS)(KSEG1_BASE |\
|
|
((x) ? MAGELLAN_1_PHYSICAL_BASE : MAGELLAN_0_PHYSICAL_BASE)))
|
|
|
|
//
|
|
// Define LOCAL device Control register structure.
|
|
//
|
|
typedef struct _LOCAL_REGISTERS { // offset(H)
|
|
UCHAR LBCTL; // 0x0
|
|
UCHAR Reserved0[15];
|
|
UCHAR LBADL; // 0x10
|
|
UCHAR Reserved1[7];
|
|
UCHAR LBADH; // 0x18
|
|
UCHAR Reserved2[7];
|
|
UCHAR LBDT; // 0x20
|
|
}LOCAL_REGISTERS, *PLOCAL_REGISTERS;
|
|
|
|
|
|
//
|
|
// LBCTL Regiser Bit define
|
|
//
|
|
|
|
#define LBCTL_SWE 0x80
|
|
#define LBCTL_SEMAPHORE 0x40
|
|
#define LBCTL_CMD 0x10
|
|
#define LBCTL_READ 0x08
|
|
|
|
//
|
|
// MRC Register Offset
|
|
//
|
|
#define MRCINT 0x0200
|
|
#define MRCMODE 0x0208
|
|
#define MRC_SWPOWEROFF 0x0230
|
|
#define MRC_FDWRITEPROTECT 0x0250
|
|
|
|
|
|
//
|
|
// ALARM Register Offset
|
|
//
|
|
#define ALARM_LOW 0x410
|
|
#define ALARM_HIGH 0x411
|
|
#define ALMINH_LOW 0x414
|
|
#define ALMINH_HIGH 0x415
|
|
#define ALMSNS_LOW 0x418
|
|
#define ALMSNS_HIGH 0x419
|
|
|
|
//
|
|
// Define pointer to Local Device Control registers.
|
|
//
|
|
#define LOCAL_CNTL ((volatile PLOCAL_REGISTERS)(KSEG1_BASE | LOCALDEV_PHYSICAL_BASE))
|
|
|
|
|
|
#endif _R98BREG_
|