762 lines
14 KiB
C
762 lines
14 KiB
C
/*++
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Copyright (c) 1994 Kobe NEC Software
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Module Name:
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rxesm.c
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Abstract:
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This module implements the ESM service routine for R98B
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Author:
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "rxesm.h"
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#include "esmnvram.h"
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#include "bugcodes.h"
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#include "stdio.h"
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#include "halp.h"
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//
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// define offset.
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//
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#define NVRAM_STATE_FLG_OFFSET (USHORT)&(((pNVRAM_HEADER)0)->nvram_flag)
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#define NVRAM_MAGIC_NO_OFFSET (USHORT)&(((pNVRAM_HEADER)0)->system.magic)
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#define SYSTEM_ERROR_LOG_INFO_OFFSET (USHORT)&(((pNVRAM_HEADER)0)->system_err.offset_systemerr)
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#define SYSTEM_ERROR_LOG_INFO_LATEST_OFFSET (USHORT)&(((pNVRAM_HEADER)0)->system_err.offset_latest)
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#define STOP_ERR_LOG_AREA_HEADER_SIZE (USHORT)&(((pSTOP_ERR_REC)0)->err_description)
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//
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// Define global variable. This variable use in display string into nvram.
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//
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ULONG HalpNvramValid=FALSE;
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ULONG CallCountOfInitDisplay=0;
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USHORT ErrBufferLatest;
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USHORT ErrBufferArea;
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USHORT ErrBufferStart;
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USHORT ErrBufferEnd;
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USHORT ErrBufferCurrent;
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ULONG HalpPanicFlg=0;
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UCHAR HalpNvramStringBuffer[STRING_BUFFER_SIZE];
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ULONG HalpNvramStringBufferCounter=0;
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UCHAR KernelPanicMessage[]="*** STOP: 0x";
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extern ULONG HalpLogicalCPU2PhysicalCPU[R98B_MAX_CPU];
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extern ULONG HalpSvpEisaSlot;
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extern ULONG HalpSvpWindow0;
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extern ULONG HalpSvpWindow1;
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extern ULONG HalpSvpWindow2;
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extern ULONG HalpSvpGlobal;
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extern ULONG HalpSvpAlive ;
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#define GET_TIME(Buffer) { \
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TIME_FIELDS timeBuffer; \
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WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->MKSR,\
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63-(EIF_VECTOR-DEVICE_VECTORS ));\
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WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->MKSR,\
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63-(ECC_1BIT_VECTOR-DEVICE_VECTORS ));\
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HalQueryRealTimeClock( &timeBuffer ); \
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WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->MKRR,\
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63-(EIF_VECTOR-DEVICE_VECTORS ));\
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WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->MKRR,\
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63-(ECC_1BIT_VECTOR-DEVICE_VECTORS ));\
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sprintf( (Buffer), \
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"%04d%02d%02d%02d%02d%02d", \
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timeBuffer.Year, \
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timeBuffer.Month, \
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timeBuffer.Day, \
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timeBuffer.Hour, \
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timeBuffer.Minute, \
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timeBuffer.Second \
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); \
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}
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BOOLEAN
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HalNvramWrite(
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ULONG Offset, // Offset Of ESM NVRAM
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ULONG Count, // Write Byte Count
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PVOID Buffer // Pointer Of Buffer Write to NVRAM
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){
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// Write into NVRAM
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#if defined(DBG1)
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DbgPrint("NVRAM write start\n");
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#endif
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return HalpNvramReadWrite(Offset,Count,Buffer,1);
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#if defined(DBG1)
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DbgPrint("NVRAM write end\n");
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#endif
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}
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BOOLEAN
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HalNvramRead(
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ULONG Offset, // Offset Of ESM NVRAM
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ULONG Count, // Read Byte Count
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PVOID Buffer // Pointer Of Buffer Read From NVRAM
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){
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// Read From NVRAM
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#if defined(DBG1)
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DbgPrint("NVRAM read start\n");
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#endif
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return HalpNvramReadWrite(Offset,Count,Buffer,0);
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#if defined(DBG1)
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DbgPrint("NVRAM read end\n");
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#endif
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}
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BOOLEAN
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HalpNvramReadWrite(
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ULONG Offset, // Read/Write offset of ESM NVRAM
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ULONG Count, // Read/Write Byte Count
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PVOID Buffer, // read/Write Pointer
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ULONG Write // Operation
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){
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ENTRYLO SavedPte[2];
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KIRQL OldIrql;
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ULONG i;
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//
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// Check is addr . So decrement 1
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//
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if(
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Offset >=0 &&
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Count >=0 &&
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NVRAM_ESM_BASE+Offset <=NVRAM_ESM_END &&
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NVRAM_ESM_BASE+Offset+Count-1 <=NVRAM_ESM_END
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){
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if(Write){
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OldIrql = HalpMapNvram(&SavedPte[0]);
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for(i=0;i<Count;i++){
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WRITE_REGISTER_UCHAR((PUCHAR)(NVRAM_ESM_BASE+Offset+i),((PUCHAR)Buffer)[i]);
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}
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HalpUnmapNvram(&SavedPte[0], OldIrql);
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}else{
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for(i=0;i<Count;i++){
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((PUCHAR)Buffer)[i] =READ_REGISTER_UCHAR((PUCHAR)(NVRAM_ESM_BASE+Offset+i));
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}
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}
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return TRUE;
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}else{
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//
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// It is no ESM NVRAM Erea.
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return FALSE;
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}
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}
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#if 0
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int
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TmpInitNvram(void)
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{
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UCHAR buf[256];
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ULONG i;
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buf[0]=0x00;
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for(i=0; i<8*1024; i++)
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HalNvramWrite( i, 1, buf);
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//
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// Make nvram flg
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//
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buf[0]=0x03;
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HalNvramWrite( NVRAM_STATE_FLG_OFFSET, 1, buf);
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i = NVRAM_MAGIC;
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HalNvramWrite( NVRAM_MAGIC_NO_OFFSET, 4, (PUCHAR)&i);
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#if DBG
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DbgPrint("Hal: ESM setup = 0x%x\n",NVRAM_STATE_FLG_OFFSET);
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DbgPrint("Hal: ESM setup = 0x%x\n",NVRAM_MAGIC_NO_OFFSET);
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#endif
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//
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// Make system err log info
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//
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((pSYSTEM_ERR_AREA_INFO)buf)->offset_systemerr=1280;
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((pSYSTEM_ERR_AREA_INFO)buf)->size_rec=512;
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((pSYSTEM_ERR_AREA_INFO)buf)->num_rec=4;
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((pSYSTEM_ERR_AREA_INFO)buf)->offset_latest=1280;
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HalNvramWrite( SYSTEM_ERROR_LOG_INFO_OFFSET,
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sizeof(SYSTEM_ERR_AREA_INFO),
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buf);
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return(0);
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}
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#endif
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VOID
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HalpInitDisplayStringIntoNvram(
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VOID
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)
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/*++
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Routine Description:
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This routine is initialize variable of use when write display data in
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HalDisplayString into NVRAM.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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SYSTEM_ERR_AREA_INFO infoBuf;
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UCHAR recordFlg;
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UCHAR buf[8];
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UCHAR buf2[8];
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CallCountOfInitDisplay++;
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if(CallCountOfInitDisplay == 1){
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#if 0 //test only
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TmpInitNvram();
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#endif
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//
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// Check NVRAM status
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//
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HalNvramRead( NVRAM_STATE_FLG_OFFSET, 1, buf );
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HalNvramRead( NVRAM_MAGIC_NO_OFFSET, 4, buf2 );
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if( ((buf[0] & 0xff) != NVRAM_VALID) || (*(PULONG)buf2 != NVRAM_MAGIC) ){
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HalpNvramValid=FALSE;
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return;
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}
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HalpNvramValid=TRUE;
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//
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// Get log area infomation.
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//
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HalNvramRead(SYSTEM_ERROR_LOG_INFO_OFFSET,
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sizeof(SYSTEM_ERR_AREA_INFO),
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&infoBuf);
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ErrBufferLatest = infoBuf.offset_latest;
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HalNvramRead( infoBuf.offset_latest, 1, &recordFlg);
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//
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// Check current record flg.
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//
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if( (recordFlg & 0x01) == 1 ) {
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infoBuf.offset_latest += infoBuf.size_rec;
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if( infoBuf.offset_latest >=
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infoBuf.offset_systemerr + (infoBuf.size_rec * infoBuf.num_rec) ){
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infoBuf.offset_latest = infoBuf.offset_systemerr;
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}
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HalNvramWrite(SYSTEM_ERROR_LOG_INFO_LATEST_OFFSET,
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2,
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&infoBuf.offset_latest);
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}
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//
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// initialize variable. this value use log area access.
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//
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ErrBufferArea = infoBuf.offset_latest;
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ErrBufferStart = infoBuf.offset_latest + STOP_ERR_LOG_AREA_HEADER_SIZE;
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ErrBufferEnd = infoBuf.offset_latest + infoBuf.size_rec-1;
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ErrBufferCurrent = ErrBufferStart;
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//
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// status flg set.
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//
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HalpPanicFlg = 0;
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recordFlg = 0x11;
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HalNvramWrite( ErrBufferArea, 1, &recordFlg );
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//
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// buffer initialize.
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//
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buf[0]=0xff;
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buf[1]=0xff;
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HalNvramWrite( ErrBufferCurrent, 2, buf );
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} else {
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//
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// start Panic log.
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//
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HalpChangePanicFlag( 1, 1, 0);
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}
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}
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VOID
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HalpSetInitDisplayTimeStamp(
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VOID
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)
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{
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UCHAR buf[32];
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//
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// Set time stamp on initialize display.
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//
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if(HalpNvramValid == TRUE) {
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GET_TIME(buf);
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HalNvramWrite( ErrBufferArea+1, TIME_STAMP_SIZE, buf );
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}
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}
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VOID
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HalpSuccessOsStartUp(
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VOID
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)
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{
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UCHAR recordFlg;
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if(HalpNvramValid == TRUE) {
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recordFlg = 0;
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HalNvramWrite( ErrBufferArea, 1, &recordFlg );
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HalNvramWrite( SYSTEM_ERROR_LOG_INFO_LATEST_OFFSET, 2, &ErrBufferLatest );
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}
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}
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VOID
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HalpChangePanicFlag(
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IN ULONG NewPanicFlg,
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IN UCHAR NewLogFlg,
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IN UCHAR CurrentLogFlgMask
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)
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{
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UCHAR recordFlg;
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UCHAR buf[32];
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// For WDT STOP and NVRAM set
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volatile ULONG CpuCount=0;
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ULONG PhysicalCpuNumber;
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ULONG CpuNumber;
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PUCHAR FwNvram;
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UCHAR Bootflag;
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PCOLUMNBUS_REGISTER ColumnbusRegister;
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CpuCount=**((PULONG *)(&KeNumberProcessors));
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if((NewPanicFlg>HalpPanicFlg)&(NewPanicFlg>0)){
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for(CpuNumber = 0; CpuNumber < CpuCount; CpuNumber++){
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PhysicalCpuNumber = HalpLogicalCPU2PhysicalCPU[CpuNumber];
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ColumnbusRegister = (PCOLUMNBUS_REGISTER)&COLUMNBS_GCNTL(4+PhysicalCpuNumber)->WDTCR;
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WRITE_REGISTER_ULONG( (PULONG)ColumnbusRegister,0x00000001);
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}
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(ULONG)FwNvram=0xbf081c00;
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Bootflag=(*FwNvram);
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*FwNvram=Bootflag|0x10;
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// SVP EIF MASK
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if(HalpSvpAlive){
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WRITE_PORT_UCHAR(HalpSvpGlobal + 0x49,0x00 );
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}
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}
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if( (HalpNvramValid == FALSE) || (NewPanicFlg <= HalpPanicFlg) ) {
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return;
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}
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HalNvramWrite(SYSTEM_ERROR_LOG_INFO_LATEST_OFFSET,
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2,
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&ErrBufferArea);
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//
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// initialize currernt buffer address
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//
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ErrBufferCurrent = ErrBufferStart;
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//
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// set panic flag
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//
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HalNvramRead( ErrBufferArea, 1, &recordFlg );
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recordFlg = (recordFlg & CurrentLogFlgMask) | NewLogFlg;
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HalNvramWrite( ErrBufferArea, 1, &recordFlg );
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GET_TIME(buf);
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HalNvramWrite( ErrBufferArea+1, TIME_STAMP_SIZE, buf );
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//
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// set new flag of panic level
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//
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HalpPanicFlg = NewPanicFlg;
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//
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// initialize log buffer.
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//
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buf[0]=0xff;
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buf[1]=0xff;
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HalNvramWrite( ErrBufferCurrent, 2, buf );
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}
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// S002 vvv
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VOID
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HalStringIntoBuffer(
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IN UCHAR Character
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)
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{
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if( (HalpNvramStringBufferCounter + 1) < STRING_BUFFER_SIZE - 1 ) {
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HalpNvramStringBuffer[HalpNvramStringBufferCounter++]=Character;
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}
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}
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VOID
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HalStringIntoBufferStart(
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IN ULONG Column,
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IN ULONG Row
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)
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{
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ULONG i;
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//
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// Initialize buffer
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//
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for(i=0; i<STRING_BUFFER_SIZE; i++) {
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HalpNvramStringBuffer[i] = 0;
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}
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HalpNvramStringBufferCounter=0;
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//
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// set string position
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//
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HalpNvramStringBuffer[HalpNvramStringBufferCounter++]=(UCHAR)Column;
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HalpNvramStringBuffer[HalpNvramStringBufferCounter++]=(UCHAR)Row;
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}
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VOID
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HalpStringBufferCopyToNvram(
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VOID
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)
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{
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UCHAR buf[4];
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USHORT count;
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//
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// check nvram status.
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//
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if(HalpNvramValid == FALSE) {
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return;
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}
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//
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// if data size is zero, when return
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//
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if( HalpNvramStringBufferCounter <= 2 ) {
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return;
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}
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HalpNvramStringBuffer[HalpNvramStringBufferCounter++]='\0';
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//
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// check panic message
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//
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for( count=0; ; count++) {
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if( KernelPanicMessage[count] == '\0' ){
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HalpChangePanicFlag( 8, 0x01, 0x10);
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break;
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}
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if( KernelPanicMessage[count] != HalpNvramStringBuffer[count+2] ){
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break;
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}
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}
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//
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// check message length
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//
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for( count=2; ; count++) {
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if( HalpNvramStringBuffer[count] == '\0' ){
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count++;
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break;
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}
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}
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loop:
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if( ErrBufferCurrent + count + 2 < ErrBufferEnd ) {
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HalNvramWrite( ErrBufferCurrent, count, HalpNvramStringBuffer );
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ErrBufferCurrent += count;
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buf[0]=0xff;
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buf[1]=0xff;
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HalNvramWrite( ErrBufferCurrent, 2, buf );
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} else if( (count + 2 > ErrBufferEnd - ErrBufferStart) && (HalpPanicFlg == 0) ) {
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return;
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} else {
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if( HalpPanicFlg == 0 ) {
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ErrBufferCurrent = ErrBufferStart;
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goto loop;
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} else if(ErrBufferCurrent >= ErrBufferEnd){
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return;
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}
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for(count=0;;count++) {
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if(ErrBufferCurrent < ErrBufferEnd) {
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HalNvramWrite( ErrBufferCurrent, 1, HalpNvramStringBuffer+count );
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}
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ErrBufferCurrent++;
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if( (HalpNvramStringBuffer[count]=='\0') && (count>=2) ) {
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break;
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}
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}
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buf[0]=0xff;
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if(ErrBufferCurrent < ErrBufferEnd) {
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HalNvramWrite( ErrBufferCurrent++, 1, buf );
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}
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if(ErrBufferCurrent < ErrBufferEnd) {
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HalNvramWrite( ErrBufferCurrent++, 1, buf );
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}
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}
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}
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VOID
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HalpLocalDeviceReadWrite(
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IN ULONG Offset,
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IN OUT PUCHAR Data,
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IN ULONG ReadOp
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)
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/*++
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Routine Description:
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This routine is Access Local Device
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Arguments:
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Offset Register Offset of Local Device
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Data Pointer of read or write data
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ReadOp 1 is Read.
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Return Value:
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None
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--*/
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{
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ULONG stsr;
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KIRQL oldirql;
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#if DBG0
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DbgPrint("LOCAL: 1 \n");
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#endif
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// NMI and EIF mask
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WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->STSR,0x08080000) ;
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KeRaiseIrql(HIGH_LEVEL, &oldirql);
|
|
|
|
//
|
|
// Get H/W Semaphore
|
|
//
|
|
while (READ_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBCTL) & LBCTL_SEMAPHORE )
|
|
;
|
|
|
|
#if DBG0
|
|
DbgPrint("LOCAL: 2\n");
|
|
#endif
|
|
|
|
//
|
|
// Set register Offset Hi Byte
|
|
//
|
|
WRITE_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBADH, (UCHAR)(Offset >> 8) );
|
|
|
|
#if DBG0
|
|
DbgPrint("LOCAL: 3\n");
|
|
#endif
|
|
|
|
|
|
//
|
|
// Set register Offset Lo Byte
|
|
//
|
|
WRITE_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBADL, (UCHAR)(Offset & 0xFF));
|
|
|
|
#if DBG0
|
|
DbgPrint("LOCAL: 4\n");
|
|
#endif
|
|
|
|
if(ReadOp){
|
|
//
|
|
// LBCTL Device read command Set.
|
|
//
|
|
WRITE_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBCTL, LBCTL_CMD|LBCTL_READ);
|
|
|
|
}else{
|
|
//
|
|
// Write data Set
|
|
//
|
|
WRITE_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBDT,*Data);
|
|
//
|
|
// LBCTL Device Write command Set.
|
|
//
|
|
WRITE_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBCTL, LBCTL_CMD);
|
|
|
|
}
|
|
#if DBG0
|
|
DbgPrint("LOCAL: 5\n");
|
|
#endif
|
|
|
|
//
|
|
// pooling LBCTL cmmand bit
|
|
//
|
|
while (READ_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBCTL) & LBCTL_CMD )
|
|
;
|
|
|
|
#if DBG0
|
|
DbgPrint("LOCAL: 6\n");
|
|
#endif
|
|
|
|
|
|
//
|
|
// If Read Operation Data Get
|
|
//
|
|
if(ReadOp)
|
|
*Data = READ_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBDT);
|
|
|
|
#if DBG0
|
|
DbgPrint("LOCAL: 7\n");
|
|
#endif
|
|
|
|
//
|
|
// Finish!!
|
|
//
|
|
WRITE_REGISTER_UCHAR( (PUCHAR)&(LOCAL_CNTL)->LBCTL,LBCTL_SWE );
|
|
|
|
// EIF NMI enable
|
|
WRITE_REGISTER_ULONG( (PULONG)&(COLUMNBS_LCNTL)->STSR,0x00080000) ;
|
|
KeLowerIrql(oldirql);
|
|
|
|
}
|
|
|
|
VOID
|
|
HalLocalDeviceReadWrite(
|
|
IN ULONG Offset,
|
|
IN OUT PUCHAR Data,
|
|
IN ULONG ReadOp
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is Access Local Device for Driver
|
|
|
|
Arguments:
|
|
Offset Register Offset of Local Device
|
|
Data Pointer of read or write data
|
|
ReadOp 1 is Read.
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
{
|
|
HalpLocalDeviceReadWrite(Offset,Data,ReadOp);
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpMrcModeChange(
|
|
UCHAR Mode
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is change Mode bit on MRC Controller.
|
|
|
|
Arguments:
|
|
|
|
Mode - Parameter for setting Mode bit on MRC
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
{
|
|
|
|
|
|
UCHAR ModeNow;
|
|
//
|
|
// Read MRC Mode Register
|
|
//
|
|
HalpLocalDeviceReadWrite(MRCMODE,&ModeNow,LOCALDEV_OP_READ);
|
|
|
|
#if DBG0
|
|
DbgPrint("MRC Read : 1 = 0x%x\n",(UCHAR)ModeNow);
|
|
#endif
|
|
|
|
//
|
|
// Write MRC Mode bit
|
|
//
|
|
|
|
ModeNow = ((ModeNow & 0x02) | (Mode << 7));
|
|
#if DBG0
|
|
DbgPrint("MRC WRITE : 2 = 0x%x\n",(UCHAR)ModeNow);
|
|
#endif
|
|
|
|
HalpLocalDeviceReadWrite(MRCMODE,&ModeNow,LOCALDEV_OP_WRITE);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|