705 lines
15 KiB
C
705 lines
15 KiB
C
#ident "@(#) NEC r98dspt.c 1.14 95/03/17 11:55:28"
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/*++
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Copyright (c) 1994 Kobe NEC Software
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Module Name:
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r98dspt.c
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Abstract:
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This module implements the interrupt dispatch routines for R98
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Author:
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Environment:
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Kernel mode
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Revision History:
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--*/
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/*
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***********************************************************************
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*
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* S001 7/7 T.Samezima
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*
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* Chg all alteration Int0-2 dispach routine
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*
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* Del move some define in r98def.h
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*
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***********************************************************************
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*
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* S002 8/22 T.Samezima on SNES
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*
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* Add Buffer for register save when unknown interrupt
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* Count up at loop counter
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*
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* Chg Modify loop logic
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*
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***********************************************************************
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*
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* S003 9/30 T.Samezima
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*
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* Bug define miss on Int1 dispatch table.
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*
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* S004 '94.10/14 T.Samezima
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* Chg Display IPR and iRSF register on bugcheck
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*
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* S005 '94.11/8 T.Samezima
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* Del Delete call of KeBugCheck. because of wrong interrupt ocure
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* of LR4360 bug
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*
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* S006 '94.11/21 T.Samezima
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* Chg Change size of dummy read
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*
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* S007 '94.12/28 T.Samezima
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* Add interrupt clear Broadcast in Unknown interrupt
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*
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* S009 '95.01/11 T.Samezima
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* Add Dummy single read on EIF interrupt.
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*
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* S00a '95.03/13 T.Samezima
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* Del PIO interrupt check.
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* Add LR4360 error check.
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* check dummy single read
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*
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*/
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#include "halp.h"
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//#include "halmips.h"
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#include "bugcodes.h"
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/* Start S001 */
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//
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// Define table in use interrupt dispatch routine
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//
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#define INT2_DATA_TABLE_SIZE 5
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#define INT1_DATA_TABLE_SIZE 6
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enum _INT_DISP_TABLE {
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iRSF_BIT=0,
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IPR_BIT,
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IDT_VECTOR,
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DUMMY_READ_ADDR,
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DUMMY_READ_SIZE,
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NA_CODE
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};
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typedef struct _DISPATCH_DATA_TABLE {
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ULONG IrsfMask;
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ULONG IprMask;
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ULONG IdtVector;
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ULONG DummyReadAddr;
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ULONG DummyReadSize;
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ULONG NaCode;
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} DISPATCH_DATA_TABLE, *PDISPATCH_DATA_TABLE;
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DISPATCH_DATA_TABLE HalpInt2DispatchDataTable[] = {
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{iRSF_KBMS_BIT, IPR_KB_MS_BIT_LOW, KBMS_VECTOR,
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KBMS_DUMMY_READ_ADDR, 1, NACODE_KB_MS},
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// {iRSF_PIO_BIT, IPR_FDC_PIO_BIT_LOW, PIO_VECTOR,
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// PIO_DUMMY_READ_ADDR, 1, NACODE_FDC_PIO}, // S00a
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{iRSF_LR_ERR_BIT,IPR_DMA_BIT_LOW, LR_ERR_VECTOR,
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DMA_DUMMY_READ_ADDR, 4, NACODE_DMA}, // S00a
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{iRSF_FDC_BIT, IPR_FDC_PIO_BIT_LOW, FDC_VECTOR,
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FDC_DUMMY_READ_ADDR, 1, NACODE_FDC_PIO}, // S00a
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{iRSF_SIO_BIT, IPR_SIO_BIT_LOW, SIO_VECTOR,
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SIO_DUMMY_READ_ADDR, 1, NACODE_SIO},
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{iRSF_DMA_BIT, IPR_DMA_BIT_LOW, DMA_VECTOR,
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DMA_DUMMY_READ_ADDR, 4, NACODE_DMA}
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};
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DISPATCH_DATA_TABLE HalpInt1DispatchDataTable[] = {
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{iRSF_EISA_BIT, IPR_EISA_BIT_LOW, EISA_DEVICE_VECTOR,
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EISA_DUMMY_READ_ADDR, 1, NACODE_EISA},
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{iRSF_SCSI1_BIT, IPR_SCSI_BIT_LOW, SCSI1_VECTOR,
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SCSI1_DUMMY_READ_ADDR, 4, NACODE_SCSI}, // S006
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{iRSF_ETHER_BIT, IPR_ETHER_BIT_LOW, ETHER_VECTOR,
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ETHER_DUMMY_READ_ADDR, 2, NACODE_ETHER},
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{iRSF_PCI_BIT, IPR_PCI_BIT_LOW, PCI_DEVICE_VECTOR,
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PCI_DUMMY_READ_ADDR, 4, NACODE_PCI}, // S003
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{iRSF_SCSI0_BIT, IPR_SCSI_BIT_LOW, SCSI0_VECTOR,
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SCSI0_DUMMY_READ_ADDR, 4, NACODE_SCSI}, // S006, S00a
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{iRSF_ERRPCI_BIT,IPR_PCI_BIT_LOW, PCI_ERR_VECTOR,
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PCI_DUMMY_READ_ADDR, 4, NACODE_PCI} // S003
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};
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// DISPATCH_DATA_TABLE HalpInt0DispatchDataTable[];
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enum _INT_TABLE_DATA{
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TABLE_SIZE=0,
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MKR_MASK,
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INT_LEVEL
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};
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ULONG HalpIntData[3][3] = {
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{0, MKR_INT0_ENABLE_LOW, INT0_LEVEL},
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{INT1_DATA_TABLE_SIZE, MKR_INT1_ENABLE_LOW, INT1_LEVEL},
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{INT2_DATA_TABLE_SIZE, MKR_INT2_ENABLE_LOW, INT2_LEVEL}
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};
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//
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// Define pointer of interrupt arbitration
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//
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ULONG HalpInt2ArbitrationPoint = 0;
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ULONG HalpInt1ArbitrationPoint = 0;
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ULONG HalpInt0ArbitrationPoint = 0;
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/* End S001 */
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#if DBG
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//
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// Register buffer
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//
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ULONG HalpUnknownCause = 0; // S002
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ULONG HalpUnknownIPRUpper = 0;
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ULONG HalpUnknownIPRLower = 0;
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ULONG HalpUnknownMKRUpper = 0;
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ULONG HalpUnknownMKRLower = 0;
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ULONG HalpUnknowniRRE = 0; // S002
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ULONG HalpUnknowniREN = 0; // S002
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ULONG HalpUnknowniRSF = 0; // S002
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ULONG HalpUnknownIprUpperBuf = 0; // S002
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ULONG HalpUnknownIprLowerBuf = 0; // S002
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ULONG HalpIoIntLoopCounter; // S002
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#endif
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//
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// Define the context structure for use by the interrupt routine.
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//
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typedef BOOLEAN (*PSECONDARY_DISPATCH)(
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PVOID InterruptRoutine
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);
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typedef BOOLEAN (*PTIMER_DISPATCH)(
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ULONG TrapFrame
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);
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VOID
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HalpUnknownInterrupt(
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IN ULONG IprUpper,
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IN ULONG IprLower
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)
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/*++
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Routine Description:
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This function is reset of unknown interrupt.
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Argments:
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IprUpper (a0) - Supplies upper 32bit of result of "IPR & MKR" in present INT level.
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IprLower (a1) - Supplies lower 32bit of result of "IPR & MKR" in present INT level.
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Return Value:
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None.
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--*/
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{
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ULONG i;
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// Start S002
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#if DBG
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HalpUnknownCause = HalpGetCause();
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
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&HalpUnknownIPRUpper,
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&HalpUnknownIPRLower
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);
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->MKR ),
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&HalpUnknownMKRUpper,
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&HalpUnknownMKRLower
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);
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HalpUnknownIprUpperBuf = IprUpper;
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HalpUnknownIprLowerBuf = IprLower;
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HalpUnknowniRRE = READ_REGISTER_ULONG( &( LR_CONTROL2 )->iRRE );
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HalpUnknowniREN = READ_REGISTER_ULONG( &( LR_CONTROL2 )->iREN );
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HalpUnknowniRSF = READ_REGISTER_ULONG( &( LR_CONTROL2 )->iRSF );
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#if 0 // S005 vvv
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KeBugCheckEx(INTERRUPT_EXCEPTION_NOT_HANDLED,
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IprUpper,
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IprLower,
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HalpUnknowniRSF,
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HalpUnknowniRRE
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); // S004
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#endif // S005 ^^^
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#endif
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// End S002
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//
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// clear interrupt pending bit
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//
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HalpWriteLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPRR ),
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&IprUpper,
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&IprLower
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);
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// S007 vvv
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//
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// issue broadcast of unknown interrupt clear
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//
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if( IprLower != 0 ) {
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PDISPATCH_DATA_TABLE dataTable;
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ULONG tableSize;
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if( IprLower & MKR_INT2_ENABLE_LOW ) {
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dataTable = HalpInt2DispatchDataTable;
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tableSize = INT2_DATA_TABLE_SIZE;
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} else if( IprLower & MKR_INT1_ENABLE_LOW ) {
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dataTable = HalpInt1DispatchDataTable;
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tableSize = INT1_DATA_TABLE_SIZE;
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}
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for( i=0; i<tableSize; i++) {
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if( i == 1 )
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continue;
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if( (IprLower & dataTable[i].IprMask) != 0 ) {
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WRITE_REGISTER_ULONG( (ULONG)( &(IOB_CONTROL)->AIMR ),
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dataTable[i].NaCode );
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}
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}
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}
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// S007 ^^^
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//
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// count up unknown interrupt
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//
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for ( i=0 ; i < 32 ; i++ ) {
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HalpUnknownInterruptCount[i] += (IprUpper >> i) & 1;
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HalpUnknownInterruptCount[i+32] += (IprLower >> i) & 1;
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}
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}
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VOID
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HalpEifDispatch(
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VOID
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)
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/*++
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Routine Description:
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This routine is enterd as the result of an eif interrupt.
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Argments:
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None.
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Return Value:
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None.
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--*/
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{
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ULONG pmcRegisterUpperPart;
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ULONG pmcRegisterLowerPart;
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ULONG pmcIPRRegisterUpperPart;
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ULONG pmcIPRRegisterLowerPart;
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ULONG zero=0;
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ULONG buffer;
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//
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// Get interrpt pending bit
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//
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
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&pmcIPRRegisterUpperPart,
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&pmcIPRRegisterLowerPart );
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Loop:
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->MKR ),
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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pmcRegisterUpperPart &= pmcIPRRegisterUpperPart;
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//
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// Check eif interrupt
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//
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buffer=pmcRegisterUpperPart & IPR_EIF_BIT_HIGH;
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if( buffer ){
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//
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// issue dummy single read
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//
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READ_REGISTER_ULONG( &( IOB_CONTROL )->EIFR.Long );
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READ_REGISTER_ULONG( &( IOB_CONTROL )->EIFR.Long );
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HalpHandleEif();
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HalpWriteLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPRR ),
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&buffer,
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&zero );
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} else {
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HalpUnknownInterrupt( pmcIPRRegisterUpperPart & MKR_INT5_ENABLE_HIGH,
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0 );
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}
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//
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// Check new interrupt
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//
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do {
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
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&pmcIPRRegisterUpperPart,
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&pmcIPRRegisterLowerPart );
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if( pmcIPRRegisterUpperPart & MKR_INT5_ENABLE_HIGH ){
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goto Loop;
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}
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} while( HalpGetCause() & (1 << (CAUSE_INT_PEND_BIT + EIF_LEVEL - 1)) );
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return;
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}
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VOID
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HalpTimerScDispatch(
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IN ULONG TrapFrame
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)
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/*++
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Routine Description:
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This routine is enterd as the result of an timer interrupt.
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Argments:
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TrapFrame - Supplies a pointer to a trap frame.
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Return Value:
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None.
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--*/
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{
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ULONG pmcRegisterUpperPart;
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ULONG pmcRegisterLowerPart;
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ULONG pmcIPRRegisterUpperPart;
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ULONG pmcIPRRegisterLowerPart;
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ULONG zero=0;
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ULONG buffer;
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//
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// read IPR register
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//
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
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&pmcIPRRegisterUpperPart,
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&pmcIPRRegisterLowerPart );
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//
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// read MKR register
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//
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Loop:
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->MKR ),
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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pmcRegisterUpperPart &= pmcIPRRegisterUpperPart;
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//
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// check profile and clock interrupt
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//
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buffer=pmcRegisterUpperPart & IPR_PROFILE_BIT_HIGH;
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if( buffer ){
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HalpWriteLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPRR ),
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&buffer,
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&zero );
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WRITE_REGISTER_ULONG( (ULONG)( &(PMC_CONTROL1)->TOVCT2.Long), 0x0 ); // S002
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((PTIMER_DISPATCH) PCR->InterruptRoutine[PROFILE_VECTOR])(TrapFrame);
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} else {
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buffer=pmcRegisterUpperPart & IPR_CLOCK_BIT_HIGH;
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HalpWriteLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPRR ),
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&buffer,
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&zero );
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WRITE_REGISTER_ULONG( (ULONG)( &(PMC_CONTROL1)->TOVCT1.Long), 0x0 ); // S002
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((PTIMER_DISPATCH) PCR->InterruptRoutine[CLOCK_VECTOR])(TrapFrame);
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}
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//
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// Check new interrupt
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//
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do {
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
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&pmcIPRRegisterUpperPart,
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&pmcIPRRegisterLowerPart );
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if( pmcIPRRegisterUpperPart & MKR_INT3_ENABLE_HIGH ){
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goto Loop;
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}
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} while( HalpGetCause() & (1 << (CAUSE_INT_PEND_BIT + TIMER_LEVEL - 1)) );
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return;
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}
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/* Start S001 */
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VOID
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HalpIoIntDispatch(
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IN PDISPATCH_DATA_TABLE DataTable,
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IN OUT PULONG ArbitrationPoint,
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IN ULONG IntNo
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)
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/*++
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Routine Description:
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This routine is enterd as the result of an int0, int1, and int2 interrupt.
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Argments:
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DataTable - Supplies a table useing judge interrupt factor.
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ArbitrationPoint - Supplies a start point of checking interrupt.
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IntNo - Supplies interrupt level.
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Return Value:
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None.
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--*/
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{
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ULONG pmcRegisterUpperPart;
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ULONG pmcRegisterLowerPart;
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ULONG pmcIPRRegisterUpperPart;
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ULONG pmcIPRRegisterLowerPart;
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ULONG buffer;
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ULONG counter;
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ULONG position;
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ULONG zero=0;
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ULONG flag;
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// Start S002
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#if DBG
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HalpIoIntLoopCounter = 0;
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#endif
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// End S002
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//
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// Get interrpt pending bit
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//
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
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&pmcIPRRegisterUpperPart,
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&pmcIPRRegisterLowerPart );
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//Loop: // S002
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HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->MKR ),
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&pmcRegisterUpperPart,
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&pmcRegisterLowerPart );
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pmcRegisterLowerPart &= pmcIPRRegisterLowerPart;
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Loop: // S002
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buffer = READ_REGISTER_ULONG( (ULONG)(&(LR_CONTROL2)->iRSF) );
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(*ArbitrationPoint)++;
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flag = FALSE;
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for(counter = 0; counter < HalpIntData[IntNo][TABLE_SIZE] ; counter++){
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position = ( (*ArbitrationPoint + counter) % HalpIntData[IntNo][TABLE_SIZE]);
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//
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// check interrupt
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//
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if( ((buffer & DataTable[position].IrsfMask) == 0) ||
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((pmcRegisterLowerPart & DataTable[position].IprMask) == 0) ) {
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continue;
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}
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flag = TRUE;
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HalpWriteLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPRR ),
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&zero,
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&(DataTable[position].IprMask)
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);
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((PSECONDARY_DISPATCH)PCR->InterruptRoutine[DataTable[position].IdtVector])(
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PCR->InterruptRoutine[DataTable[position].IdtVector]
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);
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// Start S002
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//
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// Clear Interrupt pending bit in iRSF register
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//
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WRITE_REGISTER_ULONG( (ULONG)(&(LR_CONTROL2)->iRSF),
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DataTable[position].IrsfMask );
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// End S002
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//
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// issue dummy single read
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//
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switch(DataTable[position].DummyReadSize){
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case 1:
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READ_REGISTER_UCHAR( DataTable[position].DummyReadAddr );
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READ_REGISTER_UCHAR( DataTable[position].DummyReadAddr );
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break;
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case 2:
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READ_REGISTER_USHORT( DataTable[position].DummyReadAddr );
|
|
READ_REGISTER_USHORT( DataTable[position].DummyReadAddr );
|
|
break;
|
|
case 4:
|
|
READ_REGISTER_ULONG( DataTable[position].DummyReadAddr );
|
|
READ_REGISTER_ULONG( DataTable[position].DummyReadAddr );
|
|
break;
|
|
}
|
|
|
|
//
|
|
// issue broadcast of interrupt clear
|
|
//
|
|
|
|
WRITE_REGISTER_ULONG( (ULONG)( &(IOB_CONTROL)->AIMR ),
|
|
DataTable[position].NaCode );
|
|
|
|
break; // S006
|
|
}
|
|
|
|
if (flag == FALSE){
|
|
HalpUnknownInterrupt( 0,
|
|
pmcIPRRegisterLowerPart & HalpIntData[IntNo][MKR_MASK]
|
|
);
|
|
}
|
|
|
|
//
|
|
// check new interrupt
|
|
//
|
|
|
|
do {
|
|
HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->IPR ),
|
|
&pmcIPRRegisterUpperPart,
|
|
&pmcIPRRegisterLowerPart );
|
|
|
|
// Start S002
|
|
HalpReadLargeRegister( (ULONG)( &(PMC_CONTROL1)->MKR ),
|
|
&pmcRegisterUpperPart,
|
|
&pmcRegisterLowerPart );
|
|
|
|
pmcRegisterLowerPart &= pmcIPRRegisterLowerPart;
|
|
// end S002
|
|
|
|
if( pmcIPRRegisterLowerPart & HalpIntData[IntNo][MKR_MASK] ){
|
|
// Start S002
|
|
#if DBG
|
|
HalpIoIntLoopCounter++;
|
|
#endif
|
|
// End S002
|
|
goto Loop;
|
|
}
|
|
} while(HalpGetCause() & (1 << CAUSE_INT_PEND_BIT+HalpIntData[IntNo][INT_LEVEL]-1));
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpInt2Dispatch(
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is enterd as the result of an int2 interrupt.
|
|
|
|
Argments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
HalpIoIntDispatch( HalpInt2DispatchDataTable,
|
|
&HalpInt2ArbitrationPoint,
|
|
2
|
|
);
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpInt1Dispatch(
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is enterd as the result of an int1 interrupt.
|
|
|
|
Argments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
HalpIoIntDispatch( HalpInt1DispatchDataTable,
|
|
&HalpInt1ArbitrationPoint,
|
|
1
|
|
);
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpInt0Dispatch(
|
|
VOID
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine is enterd as the result of an int0 interrupt.
|
|
|
|
Argments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
{
|
|
HalpIoIntDispatch( (PDISPATCH_DATA_TABLE)NULL,
|
|
&HalpInt0ArbitrationPoint,
|
|
0
|
|
);
|
|
}
|
|
/* End S001 */
|