802 lines
24 KiB
C
802 lines
24 KiB
C
#ident "@(#) NEC r98eif.c 1.16 95/03/17 11:56:21"
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/*++
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Copyright (c) 1994 Kobe NEC Software
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Module Name:
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r98eif.c
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Abstract:
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This module implements the Eif interrupt service routine for R98
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Author:
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Environment:
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Kernel mode
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Revision History:
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--*/
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/*
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***********************************************************************
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*
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* S001 6/10 T.Samezima
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*
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* Del Compile err
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*
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***********************************************************************
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*
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* S002 7/5 T.Samezima
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*
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* Chg CPU No set miss
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*
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***********************************************************************
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*
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* S003 7/22 T.Samezima
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*
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* Add give the dummy read after IOB and SIC register read
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* for PMC3 bug
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*
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***********************************************************************
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*
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* S004 8/23 T.Samezima
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*
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* Chg Condition change
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*
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***********************************************************************
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*
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* S005 8/24 T.Samezima
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*
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* Chg Change a form of display on eif status
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* Define buffer name
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*
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***********************************************************************
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*
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* S006 9/22 T.Samezima
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*
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* Add Execution owner flag
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* Lower the Irql level to TIMER_LEVEL. Because KdPrint
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* use to inter processor interrupt.
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*
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* Chg buffer size
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*
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***********************************************************************
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*
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* S007 9/27 T.Samezima
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*
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* Chg Arg miss
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*
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***********************************************************************
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*
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* S008 9/27 T.Samezima
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*
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* Chg Init value
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*
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* S009 10/25 T.Samezima
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* Add Variable of KeBugCheckEx()
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*
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* S00a 11/29 T.Samezima
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* Add Enable _R98DBG_
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*
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* S00b 12/07 T.Samezima
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* Chg print format.
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*
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* S00c 12/24 T.Samezima
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* Add ESM logic.
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* Del move EIFR_REGISTER define to r98reg.h
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*
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* S00d '95.01/11 T.Samezima
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* Add Disable EIF interrupt in wait loop.
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*
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* S00e '95.01/13 T.Samezima
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* Add Wait for all processers in wait loop.
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*
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* S00f '95.01/16-25 T.Samezima
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* Add Check ECC 1bit flag.
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*
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* S010 '95.03/10 T.Samezima
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* Add NMI switch check.
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*
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* S011 '95.03/14 T.Samezima
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* Add HalpLRErrorInterrupt()
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*
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*/
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#include "halp.h"
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/* Start S001 */
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#include "bugcodes.h"
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#include "eisa.h"
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#include "stdio.h"
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/* End S001 */
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#define _R98DBG_ 1 // S00a
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// Start S005
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//
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// define buffer name
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//
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enum _EIF_BUFFER {
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PMC0_ERR=0, // 0
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PMC0_AERR,
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PMC1_ERR,
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PMC1_AERR,
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PMC2_ERR,
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PMC2_AERR, // 5
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PMC3_ERR,
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PMC3_AERR,
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PMC_EADRH,
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PMC_EADRL,
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IOB_IERR, // 10
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IOB_AMAH,
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IOB_AMAL,
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IOB_ANAH,
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IOB_ANAL,
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IOB_MPER, // 15
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IOB_EIFR,
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SIC_N0_EIF0,
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SIC_N1_EIF0,
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SIC_N0_EIF1,
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SIC_N1_EIF1, // 20
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SIC_N0_STS1,
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SIC_N1_STS1,
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SIC_N0_STS2,
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SIC_N1_STS2,
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SIC_N0_DSRG, // 25
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SIC_N1_DSRG,
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SIC_N2_EIF0,
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SIC_N3_EIF0,
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SIC_N2_EIF1,
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SIC_N3_EIF1, // 30
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SIC_N2_STS1,
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SIC_N3_STS1,
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SIC_N2_STS2,
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SIC_N3_STS2,
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SIC_N2_DSRG, // 35
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SIC_N3_DSRG,
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LR_ERRS,
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LR_PEAR,
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LR_AEAR,
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EISA_NMI, // 40
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MAXMUM_EIF_BUFFER
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};
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#if 0 // S00c
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typedef struct _EIFR_REGISTER {
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ULONG Reserved : 21;
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ULONG MPDISCN : 1;
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ULONG IOBERR : 1;
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ULONG Reserved2 : 1;
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ULONG EISANMI : 1;
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ULONG LRERR : 1;
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ULONG SIC1ERR : 1;
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ULONG SIC0ERR : 1;
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ULONG PMC3ERR : 1;
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ULONG PMC2ERR : 1;
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ULONG PMC1ERR : 1;
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ULONG PMC0ERR : 1;
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} EIFR_REGISTER, *PEIFR_REGISTER;
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#endif
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// End S005
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//
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// define buffer size
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//
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#define REG_BUFFER_SIZE MAXMUM_EIF_BUFFER // S005
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//
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// buffer
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//
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ULONG HalpEifRegisterBuffer[REG_BUFFER_SIZE];
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// Start S006
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//
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// Owner flag
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//
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volatile ULONG EifOwnFlg=0;
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// End S006
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volatile ULONG CpuCount=0; // S00e
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volatile ULONG EccOccurFlag[4]={0,0,0,0}; // S00f
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// S010 vvv
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#define NMI_BUFFER_SIZE 32
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volatile ULONG HalpNMIFlag=0;
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ULONG HalpNMIBuf[NMI_BUFFER_SIZE*4];
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// S010 ^^^
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// S011 vvv
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ULONG HalpLRErrorFlag=0;
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BOOLEAN
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HalpLRErrorInterrupt(
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VOID
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)
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{
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//
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// LR4360 error flag set.
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//
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HalpLRErrorFlag=1;
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//
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// Issue EIF interrupt.
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//
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WRITE_REGISTER_ULONG( 0xb9980100, 0x0082f000 );
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return TRUE;
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}
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// S011 ^^^
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VOID
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HalpHandleEif(
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VOID
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)
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/*++
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Routine Description:
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This routine manage the eif interrupt
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR charBuffer; // S001
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ULONG buffer;
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ULONG errsBuffer;
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UCHAR messageBuffer[REG_BUFFER_SIZE*12+16]; // S006
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ULONG counter;
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UCHAR EisaPort;
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ULONG port;
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ULONG cpuNo; // S006
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ULONG EifFlg=0; // S006, S007
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KIRQL oldIrql; // S006
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ULONG i; // S00f
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// Start S005
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#if defined(_R98DBG_)
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PEIFR_REGISTER eifrbuf;
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#endif
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// End S005
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//
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// Acquire eif interrupt spin lock.
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//
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KiAcquireSpinLock(&HalpEifInterruptLock);
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// Start S006
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//
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// Get CPU Number.
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//
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cpuNo=(PCR->Prcb)->Number;
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if(EifOwnFlg == 0) {
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// CpuCount=**((PULONG *)(&KeNumberProcessors)); // S00e, S00f
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EifOwnFlg = 1;
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EifFlg = 1;
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}
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// CpuCount--; // S00e, S00f
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KiReleaseSpinLock(&HalpEifInterruptLock);
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if(EifFlg == 0) {
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//#ifdef DBG
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WRITE_REGISTER_ULONG( &(PMC_CONTROL1)->MKRR.Long,
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63-IPR_EIF_BIT_NO ); // S00d
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KeRaiseIrql(TIMER_LEVEL, &oldIrql);
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while( EifOwnFlg == 1 );
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KeLowerIrql(oldIrql);
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WRITE_REGISTER_ULONG( &(PMC_CONTROL1)->MKSR.Long,
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63-IPR_EIF_BIT_NO ); // S00d
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//#else
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// while( EifOwnFlg == 1 );
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//#endif
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EccOccurFlag[cpuNo]=0; // S00f
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return;
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}
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// S00c vvv
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buffer = READ_REGISTER_ULONG( &( IOB_CONTROL )->EIFR.Long );
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if( (HalpNMIFlag == 0) && (HalpLRErrorFlag == 0) && // S010, S011
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((((PEIFR_REGISTER)&buffer)->SIC0ERR == 1) ||
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(((PEIFR_REGISTER)&buffer)->SIC1ERR == 1)) ){
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buffer = HalpEccError(buffer);
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if(buffer == 1){
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// while( CpuCount != 0 ); // S00e
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// S00f vvv
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for( i=0; i<4; i++) {
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EccOccurFlag[i]=1;
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}
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EccOccurFlag[cpuNo]=0;
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// S00f ^^^
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EifOwnFlg = 0;
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return;
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}
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}
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// S00c ^^^
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// S00f vvv
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else if( (HalpNMIFlag == 0) && (HalpLRErrorFlag == 0) &&
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((buffer & 0xff600000) == 0) && (EccOccurFlag[cpuNo] == 1) ){ // S010, S011
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EccOccurFlag[cpuNo]=0;
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EifOwnFlg = 0;
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return;
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}
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// S00f ^^^
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// S010 vvv
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if( HalpNMIFlag == 0 ) {
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HalDisplayString("\nEIF interrupt status: "); // S005
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#ifdef DBG
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sprintf( (char *)messageBuffer, "Exe CPU=No.%1d\n", cpuNo ); // S007
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#else
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sprintf( (char *)messageBuffer, "\n" ); // S007
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#endif
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HalDisplayString( (char *)messageBuffer );
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} else {
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HalDisplayString("\nNMI occur: \n");
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}
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// S010 ^^^
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// End S006
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//
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// Check LR4360 status.
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//
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errsBuffer = READ_REGISTER_ULONG( &( LR_CONTROL1 )->ERRS );
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if( (errsBuffer & ERRS_ERROR_BIT) != 0 ) {
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WRITE_REGISTER_ULONG( &( LR_CONTROL1 )->ERRS,
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ERRS_ERROR_BIT );
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}
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buffer = READ_REGISTER_ULONG( &( IOB_CONTROL )->SCFR.Long );
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IOB_DUMMY_READ; // S003
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//
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// get register value on ERR, AERR, EADRH and EADRL registers of PMC
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//
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for(counter=0 ; counter<REG_BUFFER_SIZE ; counter++) {
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HalpEifRegisterBuffer[counter]=0;
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}
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if( (buffer & SCFR_CPU0_CONNECT) == 0 ) { // S004
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/* Start S001 */
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HalpEifRegisterBuffer[PMC0_ERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 0<<PMC_CPU_SHIFT ) )->ERR.Long
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);
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HalpEifRegisterBuffer[PMC0_AERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 0<<PMC_CPU_SHIFT ) )->AERR.Long
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);
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/* End S001 */
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}
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if( (buffer & SCFR_CPU1_CONNECT) == 0 ) { // S004
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/* Start S001,S002 */
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HalpEifRegisterBuffer[PMC1_ERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 1<<PMC_CPU_SHIFT ) )->ERR.Long
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);
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HalpEifRegisterBuffer[PMC1_AERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 1<<PMC_CPU_SHIFT ) )->AERR.Long
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);
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/* End S001,S002 */
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}
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if( (buffer & SCFR_CPU2_CONNECT) == 0 ) { // S004
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/* Start S001,S002 */
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HalpEifRegisterBuffer[PMC2_ERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 2<<PMC_CPU_SHIFT ) )->ERR.Long
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);
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HalpEifRegisterBuffer[PMC2_AERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 2<<PMC_CPU_SHIFT ) )->AERR.Long
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);
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/* End S001,S002 */
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}
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if( (buffer & SCFR_CPU3_CONNECT) == 0 ) { // S004
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/* Start S001,S002 */
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HalpEifRegisterBuffer[PMC3_ERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 3<<PMC_CPU_SHIFT ) )->ERR.Long
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);
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HalpEifRegisterBuffer[PMC3_AERR] = READ_REGISTER_ULONG( // S005
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&( PMC_GLOBAL_CONTROL1_OR( 3<<PMC_CPU_SHIFT ) )->AERR.Long
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);
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/* End S001,S002 */
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}
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/* Start S001 */
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HalpEifRegisterBuffer[PMC_EADRH] = READ_REGISTER_ULONG( // S005
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&( PMC_CONTROL2 )->EADRH.Long
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);
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HalpEifRegisterBuffer[PMC_EADRL] = READ_REGISTER_ULONG( // S005
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&( PMC_CONTROL2 )->EADRL.Long
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);
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/* End S001 */
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//
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// get register value on IERR, AMAH, AMAL, ANAH, ANAL,MPER and EIFR
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// registers of IOB.
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//
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HalpEifRegisterBuffer[IOB_IERR] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->IERR.Long,
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);
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IOB_DUMMY_READ; // S003
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HalpEifRegisterBuffer[IOB_AMAH] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->AMAH.Long,
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);
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IOB_DUMMY_READ; // S003
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HalpEifRegisterBuffer[IOB_AMAL] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->AMAL.Long,
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);
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IOB_DUMMY_READ; // S003
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HalpEifRegisterBuffer[IOB_ANAH] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->ANAH.Long,
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);
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IOB_DUMMY_READ; // S003
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HalpEifRegisterBuffer[IOB_ANAL] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->ANAL.Long,
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);
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IOB_DUMMY_READ; // S003
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HalpEifRegisterBuffer[IOB_MPER] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->MPER.Long,
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);
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IOB_DUMMY_READ; // S003
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HalpEifRegisterBuffer[IOB_EIFR] = READ_REGISTER_ULONG( // S005
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&( IOB_CONTROL )->EIFR.Long,
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);
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IOB_DUMMY_READ; // S003
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//
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// get register value on EIF0, EIF1, STS1, STS2 and DSRG registers of SIC.
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//
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if( (buffer & SCFR_SIC_SET0_CONNECT) == 0 ) { // S004
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/* Start S001 */
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HalpEifRegisterBuffer[SIC_N0_EIF0] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO0_OFFSET ) )->EIF0.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N1_EIF0] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO1_OFFSET ) )->EIF0.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N0_EIF1] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO0_OFFSET ) )->EIF1.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N1_EIF1] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO1_OFFSET ) )->EIF1.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N0_STS1] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO0_OFFSET ) )->STS1.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N1_STS1] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO1_OFFSET ) )->STS1.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N0_STS2] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO0_OFFSET ) )->STS2.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N1_STS2] = READ_REGISTER_ULONG( // S005
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&( SIC_ERR_CONTROL_OR( SIC_NO1_OFFSET ) )->STS2.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N0_DSRG] = READ_REGISTER_ULONG( // S005
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&( SIC_DATA_CONTROL_OR( SIC_NO0_OFFSET ) )->DSRG.Long,
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);
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SIC_DUMMY_READ; // S003
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HalpEifRegisterBuffer[SIC_N1_DSRG] = READ_REGISTER_ULONG( // S005
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&( SIC_DATA_CONTROL_OR( SIC_NO1_OFFSET ) )->DSRG.Long,
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);
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SIC_DUMMY_READ; // S003
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/* End S001 */
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}
|
|
|
|
if( (buffer & SCFR_SIC_SET1_CONNECT) == 0 ) { // S004
|
|
/* Start S001 */
|
|
HalpEifRegisterBuffer[SIC_N2_EIF0] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO2_OFFSET ) )->EIF0.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N3_EIF0] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO3_OFFSET ) )->EIF0.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N2_EIF1] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO2_OFFSET ) )->EIF1.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N3_EIF1] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO3_OFFSET ) )->EIF1.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N2_STS1] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO2_OFFSET ) )->STS1.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N3_STS1] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO3_OFFSET ) )->STS1.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N2_STS2] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO2_OFFSET ) )->STS2.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N3_STS2] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_ERR_CONTROL_OR( SIC_NO3_OFFSET ) )->STS2.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N2_DSRG] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_DATA_CONTROL_OR( SIC_NO2_OFFSET ) )->DSRG.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
HalpEifRegisterBuffer[SIC_N3_DSRG] = READ_REGISTER_ULONG( // S005
|
|
&( SIC_DATA_CONTROL_OR( SIC_NO3_OFFSET ) )->DSRG.Long,
|
|
);
|
|
SIC_DUMMY_READ; // S003
|
|
/* End S001 */
|
|
}
|
|
|
|
//
|
|
// get register value on ERRS, PEAR and AEAR registers of LR4360.
|
|
//
|
|
|
|
HalpEifRegisterBuffer[LR_ERRS] = errsBuffer; // S005
|
|
HalpEifRegisterBuffer[LR_PEAR] = READ_REGISTER_ULONG( // S005
|
|
&( LR_PCI_DEV_REG_CONTROL )->PEAR,
|
|
);
|
|
HalpEifRegisterBuffer[LR_AEAR] = READ_REGISTER_ULONG( // S005
|
|
&( LR_PCI_DEV_REG_CONTROL )->AEAR,
|
|
);
|
|
|
|
//
|
|
// Display EISA Nmi status.
|
|
//
|
|
|
|
charBuffer = READ_REGISTER_UCHAR( &((PEISA_CONTROL)HalpEisaControlBase )->NmiStatus);
|
|
HalpEifRegisterBuffer[EISA_NMI] = charBuffer << 24; // S001, S005
|
|
|
|
charBuffer = READ_REGISTER_UCHAR(
|
|
&( (PEISA_CONTROL)HalpEisaControlBase )->ExtendedNmiResetControl
|
|
);
|
|
HalpEifRegisterBuffer[EISA_NMI] |= charBuffer << 16; // S001, S005
|
|
|
|
//
|
|
// Look for any Eisa expansion board. See if it asserted NMI.
|
|
//
|
|
|
|
for (EisaPort = 0; EisaPort <= 0xf; EisaPort++) {
|
|
port = (EisaPort << 12) + 0xC80;
|
|
port += (ULONG) HalpEisaControlBase;
|
|
WRITE_PORT_UCHAR ((PUCHAR) port, 0xff);
|
|
charBuffer = READ_PORT_UCHAR ((PUCHAR) port);
|
|
|
|
if ((charBuffer & 0x80) == 0) {
|
|
//
|
|
// Found valid Eisa board, Check to see if it's
|
|
// if IOCHKERR is asserted.
|
|
//
|
|
charBuffer = READ_PORT_UCHAR ((PUCHAR) port+4);
|
|
if (charBuffer & 0x2) {
|
|
HalpEifRegisterBuffer[EISA_NMI] |= EisaPort; // S005
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef DBG // R98TEMP
|
|
KdPrint(("HAL: EIF Interrupt\n"));
|
|
#endif // R98TEMP
|
|
|
|
// Start S005
|
|
for( counter=0 ; counter<REG_BUFFER_SIZE ; counter++) {
|
|
sprintf( (char *)messageBuffer, "0x%08lX,", HalpEifRegisterBuffer[counter] );
|
|
HalDisplayString( (char *)messageBuffer );
|
|
#ifdef DBG // R98TEMP
|
|
KdPrint(( (char *)messageBuffer ));
|
|
#endif // R98TEMP
|
|
if( (counter % 7) == 6 ) {
|
|
sprintf( (char *)messageBuffer, "\n");
|
|
HalDisplayString( (char *)messageBuffer );
|
|
#ifdef DBG // R98TEMP
|
|
KdPrint(( (char *)messageBuffer ));
|
|
#endif // R98TEMP
|
|
}
|
|
}
|
|
|
|
#if defined(_R98DBG_)
|
|
sprintf( (char *)messageBuffer, "\n");
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
|
|
HalpChangePanicFlag( 16, 0x01, 0x10); // S00c
|
|
|
|
eifrbuf = (PEIFR_REGISTER)(&(HalpEifRegisterBuffer[IOB_EIFR]));
|
|
|
|
if( eifrbuf->PMC0ERR == 1){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from PMC0: ERR=0x%08lX, AERR=0x%08lX\n"
|
|
" EADRH=0x%08lX, EADRL=0x%08lX\n",
|
|
HalpEifRegisterBuffer[PMC0_ERR],
|
|
HalpEifRegisterBuffer[PMC0_AERR],
|
|
HalpEifRegisterBuffer[PMC_EADRH],
|
|
HalpEifRegisterBuffer[PMC_EADRL]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( eifrbuf->PMC1ERR == 1){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from PMC1: ERR=0x%08lX, AERR=0x%08lX\n"
|
|
" EADRH=0x%08lX, EADRL=0x%08lX\n",
|
|
HalpEifRegisterBuffer[PMC1_ERR],
|
|
HalpEifRegisterBuffer[PMC1_AERR],
|
|
HalpEifRegisterBuffer[PMC_EADRH],
|
|
HalpEifRegisterBuffer[PMC_EADRL]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( eifrbuf->PMC2ERR == 1){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from PMC2: ERR=0x%08lX, AERR=0x%08lX\n"
|
|
" EADRH=0x%08lX, EADRL=0x%08lX\n",
|
|
HalpEifRegisterBuffer[PMC2_ERR],
|
|
HalpEifRegisterBuffer[PMC2_AERR],
|
|
HalpEifRegisterBuffer[PMC_EADRH],
|
|
HalpEifRegisterBuffer[PMC_EADRL]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( eifrbuf->PMC3ERR == 1){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from PMC3: ERR=0x%08lX, AERR=0x%08lX\n"
|
|
" EADRH=0x%08lX, EADRL=0x%08lX\n",
|
|
HalpEifRegisterBuffer[PMC3_ERR],
|
|
HalpEifRegisterBuffer[PMC3_AERR],
|
|
HalpEifRegisterBuffer[PMC_EADRH],
|
|
HalpEifRegisterBuffer[PMC_EADRL]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( eifrbuf->SIC0ERR == 1){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from SIC SET0\n"
|
|
" No0 Status: EIF0=0x%08lX, EIF1=0x%08lX, DSRG=0x%08lX\n"
|
|
" STS1=0x%08lX, STS2=0x%08lX\n"
|
|
" No1 Status: EIF0=0x%08lX, EIF1=0x%08lX, DSRG=0x%08lX\n"
|
|
" STS1=0x%08lX, STS2=0x%08lX\n",
|
|
HalpEifRegisterBuffer[SIC_N0_EIF0],
|
|
HalpEifRegisterBuffer[SIC_N0_EIF1],
|
|
HalpEifRegisterBuffer[SIC_N0_DSRG],
|
|
HalpEifRegisterBuffer[SIC_N0_STS1],
|
|
HalpEifRegisterBuffer[SIC_N0_STS2],
|
|
HalpEifRegisterBuffer[SIC_N1_EIF0],
|
|
HalpEifRegisterBuffer[SIC_N1_EIF1],
|
|
HalpEifRegisterBuffer[SIC_N1_DSRG],
|
|
HalpEifRegisterBuffer[SIC_N1_STS1],
|
|
HalpEifRegisterBuffer[SIC_N1_STS2]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( eifrbuf->SIC1ERR == 1){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from SIC SET1\n"
|
|
" No2 Status: EIF0=0x%08lX, EIF1=0x%08lX, DSRG=0x%08lX\n"
|
|
" STS1=0x%08lX, STS2=0x%08lX\n"
|
|
" No3 Status: EIF0=0x%08lX, EIF1=0x%08lX, DSRG=0x%08lX\n"
|
|
" STS1=0x%08lX, STS2=0x%08lX\n",
|
|
HalpEifRegisterBuffer[SIC_N2_EIF0],
|
|
HalpEifRegisterBuffer[SIC_N2_EIF1],
|
|
HalpEifRegisterBuffer[SIC_N2_DSRG],
|
|
HalpEifRegisterBuffer[SIC_N2_STS1],
|
|
HalpEifRegisterBuffer[SIC_N2_STS2],
|
|
HalpEifRegisterBuffer[SIC_N3_EIF0],
|
|
HalpEifRegisterBuffer[SIC_N3_EIF1],
|
|
HalpEifRegisterBuffer[SIC_N3_DSRG],
|
|
HalpEifRegisterBuffer[SIC_N3_STS1],
|
|
HalpEifRegisterBuffer[SIC_N3_STS2]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( HalpLRErrorFlag == 1 ){ // S011
|
|
sprintf( (char *)messageBuffer,
|
|
"LR4360 Error Acknowledge Interrupt:\n" // S011
|
|
" ERRS=0x%08lX, PEAR=0x%08lX, AEAR=0x%08lX\n", // S011
|
|
HalpEifRegisterBuffer[LR_ERRS],
|
|
HalpEifRegisterBuffer[LR_PEAR],
|
|
HalpEifRegisterBuffer[LR_AEAR]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( (eifrbuf->IOBERR == 1) || (eifrbuf->MPDISCN == 1) ){
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from IOB: IERR=0x%08lX, AMAH=0x%08lX, AMAL=0x%08lX\n"
|
|
" ANAH=0x%08lX, ANAL=0x%08lX, EIFR=0x%08lX, MPER=0x%08lX\n",
|
|
HalpEifRegisterBuffer[IOB_IERR],
|
|
HalpEifRegisterBuffer[IOB_AMAH],
|
|
HalpEifRegisterBuffer[IOB_AMAL],
|
|
HalpEifRegisterBuffer[IOB_ANAH],
|
|
HalpEifRegisterBuffer[IOB_ANAL],
|
|
HalpEifRegisterBuffer[IOB_EIFR],
|
|
HalpEifRegisterBuffer[IOB_MPER]
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
if( eifrbuf->EISANMI == 1){
|
|
|
|
sprintf( (char *)messageBuffer,
|
|
"EIF Interrupt from EISA NMI: NmiStatus=0x%02lX\n"
|
|
" ExtendedNmiResetControl=0x%02lX, Port=%d\n",
|
|
((HalpEifRegisterBuffer[EISA_NMI] >> 24) & 0xff),
|
|
((HalpEifRegisterBuffer[EISA_NMI] >> 16) & 0xff),
|
|
(HalpEifRegisterBuffer[EISA_NMI] & 0xff)
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
|
|
// S010 vvv
|
|
if( (HalpNMIFlag & 0x0000008) != 0 ) {
|
|
sprintf( (char *)messageBuffer,
|
|
"NMI from MRC\n"
|
|
);
|
|
HalDisplayString( (char *)messageBuffer );
|
|
KdPrint(( (char *)messageBuffer ));
|
|
}
|
|
// S010 ^^^
|
|
#endif
|
|
// End S005
|
|
|
|
EifOwnFlg == 0;
|
|
|
|
KeBugCheckEx(NMI_HARDWARE_FAILURE,
|
|
HalpEifRegisterBuffer[IOB_EIFR],
|
|
HalpNMIFlag, // S010
|
|
HalpLRErrorFlag ? HalpEifRegisterBuffer[LR_ERRS] : 0, // S011
|
|
0
|
|
); // S009
|
|
}
|