732 lines
20 KiB
C
732 lines
20 KiB
C
/*++
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Copyright (c) 1993-1995 Digital Equipment Corporation
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Module Name:
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iodaddr.c
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Abstract:
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This module contains the platform dependent code to create bus addreses
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and QVAs for the Rawhide system.
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Author:
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Eric Rehm 10-Apr-1995
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "halp.h"
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#include "eisa.h"
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#include "pci.h"
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#include "pcip.h"
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typedef PVOID QUASI_VIRTUAL_ADDRESS;
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QUASI_VIRTUAL_ADDRESS
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HalCreateQva(
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IN PHYSICAL_ADDRESS PA,
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IN PVOID VA
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);
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BOOLEAN
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HalpTranslateSystemBusAddress(
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IN PBUS_HANDLER BusHandler,
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IN PBUS_HANDLER RootHandler,
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IN PHYSICAL_ADDRESS BusAddress,
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IN OUT PULONG AddressSpace,
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OUT PPHYSICAL_ADDRESS TranslatedAddress
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)
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/*++
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Routine Description:
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This function returns the system physical address for a specified I/O bus
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address. The return value is suitable for use in a subsequent call to
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MmMapIoSpace.
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Arguments:
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BusHandler - Registered BUSHANDLER for the target configuration space
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Supplies the bus handler (bus no, interface type).
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RootHandler - Registered BUSHANDLER for the orginating
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HalTranslateBusAddress request.
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BusAddress - Supplies the bus relative address.
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AddressSpace - Supplies the address space number for the device: 0 for
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memory and 1 for I/O space. If the desired access mode is user mode,
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then bit 1 must be TRUE.
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TranslatedAddress - Supplies a pointer to return the translated address
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Notes:
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This is a variation of what began in the MIPS code. The intel code often
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assumes that if an address is in I/O space, the bottom 32 bits of the
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physical address can be used "like" a virtual address, and are returned
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to the user. This doesn't work on Alpha and MIPS machines where physical
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addresses can be larger than 32 bits.
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Since we are using superpage addresses for I/O on Alpha, we can do
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almost what is done on intel. If AddressSpace is equal to 0 or 1, then
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we assume the user is doing kernel I/O and we use the macro
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HAL_MAKE_IOD_SPARSE_QVA to build a Quasi Virtual address and return
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that to the caller. We then set AddressSpace to a 1, so that the caller
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will not call MmMapIoSpace. The Caller will use the low 32 bits of the
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physical address we return as the VA. (Which we built a QVA in).
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Note that KernelPciDenseMemory *is* mapped via MmMapIoSpace.
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If the caller wants to access EISA I/O or Memory through user mode, then
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the caller must set bit 1 in AddressSpace to a 1 (AddressSpace=2 or 3,
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depending on whether EISA I/O or Memory), then the caller is returned the
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40 bit Physical address. The caller will then call MmMapIoSpace, or
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ZwMapViewOfSection which in turn calls HalCreateQva to build a QVA out
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of a VA mapped through the page tables.
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**** Note ****
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The QVA in user mode can only be used via the user-mode access macros.
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Rawhide notes:
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QVA's on Rawhide encode a BusNumber and an offset on that bus, i.e.,
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the physical address is not directly coded in the QVA. The actual
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superpage physical address is constructed at the time of access.
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Sparse QVA space from A000.0000 - C000.0000 is separate for I/O
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and memory space. For example, sparse memory address 0 on BusNumber
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0 has QVA = A000.0000 and sparse I/O address 0 on BusNumber 0 also
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has QVA = A000.0000. The user of a QVA must know what they're
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doing, and properly call the correct access routine for the
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address space that they desire.
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Finally, sparse and dense memory QVA's must coexist with the
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same memory access routines (READ/WRITE_REGISTER_*). Since
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Rawhide has 4 I/O buses, supporting 4 * 1 Gb dense spaces +
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4 * 128 Mb sparse spaces is not possible using a 32 bit QVA.
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Therefore, we arbitrarily "short sheet" the dense address space
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of BusNumber 2 to 512 Mb to make room for the sparse space QVAs.
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Return Value:
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A return value of TRUE indicates that a system physical address
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corresponding to the supplied bus relative address and bus address
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number has been returned in TranslatedAddress.
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A return value of FALSE occurs if the translation for the address was
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not possible
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--*/
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{
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INTERFACE_TYPE InterfaceType = BusHandler->InterfaceType;
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ULONG BusNumber = BusHandler->BusNumber;
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MC_DEVICE_ID McDeviceId;
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PPCIPBUSDATA BusData;
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ULONG HwBusNumber;
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PVOID va = 0; // note, this is used for a placeholder
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//
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// Check InterfaceType:
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// The only buses available on Rawhide are an EISA bus and a PCI bus.
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// We support any translations for EISA devices as well, though
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// if they are true EISA devices they won't even be able to plug into
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// the connectors!
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//
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if ( (InterfaceType != Isa) &&
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(InterfaceType != Eisa) &&
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(InterfaceType != PCIBus) ) {
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//
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// Not on this system return nothing.
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//
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#if HALDBG
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DbgPrint( "HalTBA: Unhandled interface type = %x\n", InterfaceType );
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#endif //HALDBG
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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//
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// Next, generate the IOD number (HwBusNumber).
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//
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// If it's ISA or EISA, BusNumber and HwBusNumber = 0.
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// If it's PCI, we get HwBusNumber from PCI-specific bus data.
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//
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HwBusNumber = 0; // Isa, Eisa
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if (InterfaceType == PCIBus ) {
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//
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// Get a pointer to the PCIBus-specific data.
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//
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BusData = (PPCIPBUSDATA)BusHandler->BusData;
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//
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// In particular, what root PCI bus (IOD) are we on?
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//
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HwBusNumber = BusData->HwBusNumber;
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}
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//
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// Build MC Bus device id for this bus using HwBusNumber.
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// Currently, only the Primary Global Id (0x7) is supported.
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//
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McDeviceId.all = 0;
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McDeviceId.Gid = GidPrimary;
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McDeviceId.Mid = MidPci0 + HwBusNumber;
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//
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// Determine the address based on whether the bus address is in I/O space
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// or bus memory space.
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//
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switch ( (ADDRESS_SPACE_TYPE)(*AddressSpace) ) {
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case BusMemory: {
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//
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// The address is in PCI memory space, kernel mode.
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//
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switch( InterfaceType ) {
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case Isa: {
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//
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// Can't go above 16MB (24 Bits) for Isa Buses
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//
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if( BusAddress.LowPart >= __16MB ){
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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break;
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} // case Isa
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case Eisa:
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//
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// Eisa is the same as PCI, with respect to kernel mode
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// sparse and dense space memory support, i.e., its a full 32 bit space,
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// supports dense memory access.
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//
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case PCIBus: {
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//
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// Don't allow accesses to PCI/EISA addresses below
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// 1 Mb on root buses other than PCI-0.
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//
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#if 1 // ecrfix - needed for WINT3.51 !!!
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if ( BusAddress.LowPart < __1MB &&
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HwBusNumber > 0 ) {
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#if HALDBG
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DbgPrint ("Unsupported PCI-%d (ISA legacy) address %x:%x\n",
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HwBusNumber,
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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#endif
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//
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// Check legal PCI bus address ranges
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//
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if ( BusAddress.LowPart > PCI_MAX_DENSE_MEMORY_ADDRESS ) {
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//
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// Unsupported dense PCI bus address.
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//
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#if HALDBG
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DbgPrint ("Unsupported PCI address %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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else if( BusAddress.LowPart >= PCI_MIN_DENSE_MEMORY_ADDRESS &&
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BusAddress.LowPart <= PCI_MAX_DENSE_MEMORY_ADDRESS ) {
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#if HALDBG
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DbgPrint ("Translating PCI kernel dense address %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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//
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// Bus Address is in dense PCI memory space
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//
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//
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// QVA, as such, is simply PCI bus address offset
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// from the base dense memory address for that bus.
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// The bus number is encoded in bits <31:30>.
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//
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TranslatedAddress->LowPart = (ULONG)
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HAL_MAKE_IOD_DENSE_QVA(HwBusNumber, BusAddress.LowPart);
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//
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// clear high longword for QVA
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//
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TranslatedAddress->HighPart = 0;
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//
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// dont let the user call MmMapIoSpace
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//
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*AddressSpace = 1;
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return (TRUE);
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}
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//
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// Bus Address is in sparse PCI memory space
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//
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#if HALDBG
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DbgPrint ("Translating PCI kernel sparse address %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart);
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#endif
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break;
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} // case PCIBus
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} // switch( InterfaceType )
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//
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// Now create the QVA from the HwBusNumber and BusAddress.
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//
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// Unlike many other Alpha platfroms, the QVA is *not* an
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// encoding of the physical address. The full physical address
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// will can be constructed at the time of the I/O access with the
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// information encoded here in the QVA: HwBusNumber and BusAddress.
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// (The bus number is encoded in bits <28:27> of the QVA.)
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//
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TranslatedAddress->LowPart = (ULONG)
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HAL_MAKE_IOD_SPARSE_QVA(HwBusNumber, BusAddress.LowPart);
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//
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// clear high longword for QVA
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//
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TranslatedAddress->HighPart = 0;
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//
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// don't let the user call MmMapIoSpace
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//
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*AddressSpace = 1;
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return(TRUE);
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} // case BusMemory
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case BusIo: {
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//
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// The address is in PCI I/O space, kernel mode.
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//
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switch( InterfaceType ) {
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case Eisa:
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//
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// Eisa is the same as ISA, with respect to kernel mode
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// sparse I/O space support, i.e., it is a 16 bit sparse
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// space.
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//
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case Isa: {
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//
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// Can't go above 64KB (16 Bits) for Isa Buses
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//
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if( BusAddress.LowPart >= __64K ){
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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break;
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} // case Isa
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case PCIBus: {
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//
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// PCI IO space is always below 32MB (25 Bits) BusAddress
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// If the address cannot be mapped, just return FALSE.
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//
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if( BusAddress.LowPart >= __32MB ){
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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//
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// if the BusAddress.LowPart is > 64K then we use the HAER2
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// register.
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//
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break;
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} // case PCIBus
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} // switch( InterfaceType )
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//
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// Now create the QVA from the HwBusNumber and BusAddress.
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//
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// Unlike many other Alpha platfroms, the QVA is *not* an
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// encoding of the physical address. The full physical address
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// will can be constructed at the time of the I/O access with the
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// information encoded here in the QVA: HwBusNumber and BusAddress.
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// (The bus number is encoded in bits <28:27> of the QVA.)
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//
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TranslatedAddress->LowPart = (ULONG)
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HAL_MAKE_IOD_SPARSE_QVA(HwBusNumber, BusAddress.LowPart);
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//
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// clear high longword for QVA
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//
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TranslatedAddress->HighPart = 0;
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//
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// don't let the user call MmMapIoSpace
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//
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*AddressSpace = 1;
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return(TRUE);
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} // case BusIo
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case UserBusMemory: {
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//
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// The address is in PCI memory space, user mode.
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//
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = IOD_SPARSE_MEM_OFFSET;
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TranslatedAddress->QuadPart |= MCDEVID_TO_PHYS_ADDR( McDeviceId.all );
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TranslatedAddress->QuadPart |= EV5_USER_IO_ADDRESS_SPACE;
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TranslatedAddress->QuadPart += (((ULONGLONG)BusAddress.LowPart) << IO_BIT_SHIFT);
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#if HALDBG
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DbgPrint ("Translating PCI user mem sparse address %x:%x to %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart,
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TranslatedAddress->HighPart,
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TranslatedAddress->LowPart);
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#endif
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*AddressSpace = 0; // Let the user call MmMapIoSpace
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return(TRUE);
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}
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case UserBusIo: {
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//
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// The address is in PCI I/O space, user mode.
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//
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = IOD_SPARSE_IO_OFFSET;
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TranslatedAddress->QuadPart |= MCDEVID_TO_PHYS_ADDR( McDeviceId.all );
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TranslatedAddress->QuadPart |= EV5_USER_IO_ADDRESS_SPACE;
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TranslatedAddress->QuadPart += (((ULONGLONG)BusAddress.LowPart) << IO_BIT_SHIFT);
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#if HALDBG
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DbgPrint ("Translating PCI user I/O sparse address %x:%x to %x:%x\n",
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BusAddress.HighPart,
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BusAddress.LowPart,
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TranslatedAddress->HighPart,
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TranslatedAddress->LowPart);
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#endif
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*AddressSpace = 0; // Make sure user can call
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// MmMapIoSpace.
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return(TRUE);
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}
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case KernelPciDenseMemory:
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case UserPciDenseMemory:
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{
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//
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// The address is in PCI dense memory space, user mode.
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//
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//
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// Start with the base physical address and add the
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// bus address by converting it to the physical address.
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//
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TranslatedAddress->QuadPart = IOD_DENSE_MEM_OFFSET;
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TranslatedAddress->QuadPart |= MCDEVID_TO_PHYS_ADDR( McDeviceId.all );
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TranslatedAddress->QuadPart |= EV5_USER_IO_ADDRESS_SPACE;
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TranslatedAddress->QuadPart += BusAddress.LowPart;
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*AddressSpace = 0; // Let the user call MmMapIoSpace
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#if HALDBG
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DbgPrint("HTBA: UserPciDenseMemory %x to %x;%x\n",
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BusAddress.LowPart,
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TranslatedAddress->HighPart,
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TranslatedAddress->LowPart);
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#endif // HALDBG
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return(TRUE);
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}
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default: {
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//
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// Unsupported address space.
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//
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*AddressSpace = 0;
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TranslatedAddress->LowPart = 0;
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return(FALSE);
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}
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}
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}
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PVOID
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HalCreateQva(
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IN PHYSICAL_ADDRESS PA,
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IN PVOID VA
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)
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|
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/*++
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|
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Routine Description:
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This function is only available to a caller constructing a QVA
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as a result of a page table mapping via ZwMapViewOfSection or
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MmMapIoSpace.
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N.B. HalTranslateBusAddress, or other HAL routines MUST NOT
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CALL THIS ROUTINE. This is because on Rawhide, a kernel-mode
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dense or sparse superpage QVA cannot be contructed without
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knowledge of the BusNumber, which is not passed into this routine.
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If the input parameter VA is zero, then we assume the caller
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was incorrectly attempting to create a super page and build
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a QUASI virtual address, and results in an error.
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If the input parameter VA is non-zero, we assume the user has either
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called MmMapIoSpace or ZwMapViewOfSection and will use the user mode
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access macros.
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If the PA is not an I/O space address (PCI I/O, PCI Memory),
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then return the VA as the QVA.
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Arguments:
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PA - the physical address generated by HalTranslateBusAddress
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VA - the virtual address returned by MmMapIoSpace
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Return Value:
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The returned value is a quasi virtual address in that it can be
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added to and subtracted from, but it cannot be used to access the
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bus directly. The top bits are set so that we can trap invalid
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accesses in the memory management subsystem. All access should be
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done through the Hal Access Routines in *ioacc.s if it was a superpage
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kernel mode access. If it is usermode, then the user mode access
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macros must be used.
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|
||
--*/
|
||
{
|
||
|
||
PHYSICAL_ADDRESS PhysicalOffset;
|
||
PVOID qva;
|
||
|
||
PhysicalOffset.QuadPart = PHYS_ADDR_TO_OFFSET( PA.QuadPart );
|
||
|
||
#if HALDBG
|
||
DbgPrint("HalCreateQva: PhysicalOffset = %x;%x\n",
|
||
PhysicalOffset.HighPart,
|
||
PhysicalOffset.LowPart);
|
||
#endif
|
||
|
||
|
||
if (VA == 0) {
|
||
|
||
//
|
||
// Error - HalCreateQva should not be called to create
|
||
// a superpage QVA.
|
||
//
|
||
|
||
#if HALDBG
|
||
|
||
DbgPrint( "HalCreateQva: Should not be called to create a superpage QVA from %x:%x\n", PA.HighPart, PA.LowPart );
|
||
DbgBreakPoint();
|
||
|
||
#endif //HALDBG
|
||
|
||
return (VA);
|
||
|
||
} else if( (PhysicalOffset.QuadPart >= IOD_DENSE_MEM_OFFSET) &&
|
||
(PhysicalOffset.QuadPart <= (IOD_DENSE_MEM_OFFSET +
|
||
PCI_MAX_DENSE_MEMORY_ADDRESS)) ){
|
||
|
||
//
|
||
// Physical dense address, return VA.
|
||
//
|
||
|
||
#if HALDBG
|
||
DbgPrint("HalCreateQva: User Mode Dense QVA = VA = %x\n", VA);
|
||
#endif
|
||
return(VA);
|
||
|
||
} else {
|
||
|
||
//
|
||
// The physical address is within one of the sparse I/O spaces.
|
||
//
|
||
|
||
qva = (PVOID)((ULONG)VA >> IO_BIT_SHIFT);
|
||
|
||
qva = (PVOID)((ULONG)qva | QVA_ENABLE);
|
||
|
||
#if HALDBG
|
||
DbgPrint("HalCreateQva: User Mode Sparse QVA = %x\n", qva);
|
||
#endif
|
||
return(qva);
|
||
}
|
||
}
|
||
|
||
PVOID
|
||
HalDereferenceQva(
|
||
PVOID Qva,
|
||
INTERFACE_TYPE InterfaceType,
|
||
ULONG BusNumber
|
||
)
|
||
/*++
|
||
|
||
Routine Description:
|
||
|
||
This function performs the inverse of the HalCreateQva for I/O addresses
|
||
that are memory-mapped (i.e. the quasi-virtual address was created from
|
||
a virtual address rather than a physical address).
|
||
|
||
Arguments:
|
||
|
||
Qva - Supplies the quasi-virtual address to be converted back to a
|
||
virtual address.
|
||
|
||
InterfaceType - Supplies the interface type of the bus to which the
|
||
Qva pertains.
|
||
|
||
BusNumber - Supplies the bus number of the bus to which the Qva pertains.
|
||
|
||
Return Value:
|
||
|
||
The Virtual Address from which the quasi-address was originally created
|
||
is returned.
|
||
|
||
--*/
|
||
{
|
||
|
||
|
||
//
|
||
// For Sable we have three supported bus types:
|
||
//
|
||
// Isa
|
||
// Eisa
|
||
// PCIBus
|
||
//
|
||
|
||
switch (InterfaceType ){
|
||
|
||
case Isa:
|
||
case Eisa:
|
||
case PCIBus:
|
||
|
||
//
|
||
// Support dense space: check to see if it's really
|
||
// a sparse space QVA.
|
||
//
|
||
|
||
if ( ((ULONG) Qva & QVA_SELECTORS) == QVA_ENABLE ) {
|
||
return( (PVOID)( (ULONG)Qva << IO_BIT_SHIFT ) );
|
||
} else {
|
||
return (Qva);
|
||
}
|
||
break;
|
||
|
||
default:
|
||
|
||
return NULL;
|
||
|
||
}
|
||
|
||
|
||
}
|
||
|