195 lines
5.2 KiB
C
195 lines
5.2 KiB
C
/*++
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Copyright (c) 1994 Digital Equipment Corporation
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Module Name:
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sablertc.h
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Abstract:
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This module is the header file that describes the TOY clock
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for the Sable.
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Author:
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94.01.16 Steve Jenness
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Revision History:
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This file was accidentally removed. It has since been added back.
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However, since the history information will be lost, the one liner
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history information was put here.
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Log for ntos\NTHALS\HALSABLE\ALPHA:
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02-25-94@13:05 V-SJEN3 addfile sablertc.h v1 [v-ntdec] latest Alpha Hal
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06-10-94@11:41 JVERT4 in sablertc.h v2 halsettimeincrement
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03-28-95@14:29 V-NTDEC1 in sablertc.h v3 fix for 9760 - NVRAM envi
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05-25-95@10:59 V-NTDEC1 delfile sablertc.h v4 checked in for 9760
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--*/
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#ifndef _SABLERTC_
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#define _SABLERTC_
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//
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// Sable's RTC is a Dallas Semiconductor 1287
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//
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// The APORT and DPORT CSR addresses are defined in a platform
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// specific file.
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//
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// The RTC NVRAM byte offsets are 0x0e -- 0x3f.
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//
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// Offsets 0x0E -- 0x3D are reserved for use by VMS/OSF.
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//
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#define RTC_RAM_NT_FLAGS0 0x3E // NT firmware flag set #0
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#define RTC_RAM_CONSOLE_SELECTION 0x3F // VMS/OSF/NT boot selection
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//
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// Define Realtime Clock register numbers.
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//
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#define RTC_SECOND 0 // second of minute [0..59]
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#define RTC_SECOND_ALARM 1 // seconds to alarm
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#define RTC_MINUTE 2 // minute of hour [0..59]
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#define RTC_MINUTE_ALARM 3 // minutes to alarm
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#define RTC_HOUR 4 // hour of day [0..23]
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#define RTC_HOUR_ALARM 5 // hours to alarm
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#define RTC_DAY_OF_WEEK 6 // day of week [1..7]
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#define RTC_DAY_OF_MONTH 7 // day of month [1..31]
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#define RTC_MONTH 8 // month of year [1..12]
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#define RTC_YEAR 9 // year [00..99]
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#define RTC_CONTROL_REGISTERA 10 // control register A
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#define RTC_CONTROL_REGISTERB 11 // control register B
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#define RTC_CONTROL_REGISTERC 12 // control register C
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#define RTC_CONTROL_REGISTERD 13 // control register D
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#define RTC_REGNUMBER_RTC_CR1 0x6A
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#ifndef _LANGUAGE_ASSEMBLY
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//
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// Define Control Register A structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_A {
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UCHAR RateSelect : 4;
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UCHAR TimebaseDivisor : 3;
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UCHAR UpdateInProgress : 1;
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} RTC_CONTROL_REGISTER_A, *PRTC_CONTROL_REGISTER_A;
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//
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// Define Control Register B structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_B {
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UCHAR DayLightSavingsEnable : 1;
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UCHAR HoursFormat : 1;
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UCHAR DataMode : 1;
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UCHAR SquareWaveEnable : 1;
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UCHAR UpdateInterruptEnable : 1;
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UCHAR AlarmInterruptEnable : 1;
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UCHAR TimerInterruptEnable : 1;
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UCHAR SetTime : 1;
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} RTC_CONTROL_REGISTER_B, *PRTC_CONTROL_REGISTER_B;
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//
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// Define Control Register C structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_C {
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UCHAR Fill : 4;
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UCHAR UpdateInterruptFlag : 1;
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UCHAR AlarmInterruptFlag : 1;
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UCHAR TimeInterruptFlag : 1;
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UCHAR InterruptRequest : 1;
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} RTC_CONTROL_REGISTER_C, *PRTC_CONTROL_REGISTER_C;
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//
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// Define Control Register D structure.
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//
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typedef struct _RTC_CONTROL_REGISTER_D {
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UCHAR Fill : 7;
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UCHAR ValidTime : 1;
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} RTC_CONTROL_REGISTER_D, *PRTC_CONTROL_REGISTER_D;
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//
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// NT firmware flags in TOY NVRAM
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//
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typedef struct _RTC_RAM_NT_FLAGS_0 {
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UCHAR AutoRunECU : 1; // Go directly to ECU
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UCHAR ResetAfterECU : 1; // Force user to reset after ECU runs
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UCHAR Fill : 5;
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UCHAR ConfigurationBit : 1; // Serial line console only
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} RTC_RAM_NT_FLAGS_0, *PRTC_RAM_NT_FLAGS_0;
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#define RTC_RAM_NT_FLAGS_0_RUNARCAPP (0x01)
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#define RTC_RAM_NT_FLAGS_0_RESERVED (0x7E)
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#define RTC_RAM_NT_FLAGS_0_USECOM1FORIO (0x80)
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#endif //_LANGUAGE_ASSEMBLY
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//
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// Values for RTC_RAM_CONSOLE_SELECTION
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//
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#define RTC_RAM_CONSOLE_SELECTION_NT 1
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#define RTC_RAM_CONSOLE_SELECTION_VMS 2
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#define RTC_RAM_CONSOLE_SELECTION_OSF 3
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//
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// Define initialization values for Sable interval timer
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// rate is 7.8125 ms, 7812.5 us, 78125 clunks
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//
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// The Sable clock is divided by 2 by the
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// Multiprocessor interval clock phasing hardware.
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// The rate select is half what would otherwise be used.
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//
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// #define RTC_RATE_SELECT 0x01
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// #define RTC_PERIOD_IN_CLUNKS 78125
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#define RTC_TIMEBASE_DIVISOR 0x02
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//
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// Define initialization values for Sable interval timer
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// There are four different rates that are used under NT
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// (see page 9-8 of KN121 System Module Programmer's Reference)
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//
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// .976562 ms
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// 1.953125 ms
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// 3.90625 ms
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// 7.8125 ms
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//
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// The Sable clock is divided by 2 by the
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// Multiprocessor interval clock phasing hardware.
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// The rate select is half what would otherwise be used.
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//
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#define RTC_RATE_SELECT1 5
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#define RTC_RATE_SELECT2 6
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#define RTC_RATE_SELECT3 7
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#define RTC_RATE_SELECT4 8
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//
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// note that rates 1-3 have some rounding error,
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// since they are not expressible in even 100ns units
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//
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#define RTC_PERIOD_IN_CLUNKS1 9766
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#define RTC_PERIOD_IN_CLUNKS2 19531
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#define RTC_PERIOD_IN_CLUNKS3 39063
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#define RTC_PERIOD_IN_CLUNKS4 78125
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//
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// Defaults
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//
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#define MINIMUM_INCREMENT RTC_PERIOD_IN_CLUNKS1
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#define MAXIMUM_INCREMENT RTC_PERIOD_IN_CLUNKS4
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#define MAXIMUM_RATE_SELECT RTC_RATE_SELECT4
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#endif // _SABLERTC_
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