370 lines
11 KiB
C
370 lines
11 KiB
C
#pragma comment(exestr, "$Header: /usr4/winnt/SOURCES/ddk35/src/hal/halsni/mips/RCS/xxinitnt.c,v 1.6 1995/04/07 10:08:17 flo Exp $")
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/*++
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Copyright (c) 1993 - 1994 Siemens Nixdorf Informationssysteme AG
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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xxinitnt.c
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Abstract:
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This module implements the interrupt initialization for a MIPS R3000
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or R4000 system.
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Environment:
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Kernel mode only.
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--*/
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#include "halp.h"
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#include "eisa.h"
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extern BOOLEAN HalpProcPc;
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extern BOOLEAN HalpCountCompareInterrupt;
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//
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// Define forward referenced prototypes.
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//
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VOID
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HalpAckExtraClockInterrupt(
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VOID
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);
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VOID
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HalpCountInterrupt (
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VOID
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);
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VOID
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HalpProgramIntervalTimer (
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IN ULONG Interval
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);
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VOID
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HalpProgramExtraTimer (
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IN ULONG Interval
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);
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//
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// Put all code for HAL initialization in the INIT section. It will be
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// deallocated by memory management when phase 1 initialization is
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// completed.
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//
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(INIT, HalpInitializeInterrupts)
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#pragma alloc_text(INIT, HalpCountInterrupt)
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#endif
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//
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// Define the IRQL mask and level mapping table.
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//
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// These tables are transfered to the PCR and determine the priority of
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// interrupts.
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//
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// N.B. The two software interrupt levels MUST be the lowest levels.
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/*+++
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The interrupts bits in the cause Register have the following Hardware Interrupts:
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7 6 5 4 3 2 1 0
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+-------------------------------+
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| x | x | x | x | x | x | x | x |
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+-------------------------------+
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| | | | | | | |
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| | | | | | | +-------- APC LEVEL (Software)
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| | | | | | +------------ Dispatch LEVEL (Software)
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| | | | | +---------------- central Int0 for R4x00 SC machines
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| | | | +-------------------- SCSI_EISA LEVEL
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| | | +------------------------ DUART (Console)
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| | +---------------------------- TIMER (82C54 in the local I/O part)
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| +-------------------------------- Ethernet (intel 82596 onboard)
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+------------------------------------ CountCompare (Profiling) or PushButton Int.
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---*/
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//
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// On an R4x00SC, the processor has only 1 central interrupt pin, so all
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// should be directed to this interrupt, except the (internal) CountCompare interrupt
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// This is also true for the oncomming SNI Desktop model, which has only the
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// central interrupt connected
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//
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UCHAR
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HalpIrqlMask_SC[] = {3, 3, 3, 3, 3, 3, 3, 3, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits (CountCompare only!)
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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3, 3, 3, 3, 3, 3, 3, 3}; // 1000 - 1111 low 4-bits
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UCHAR
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HalpIrqlTable_SC[] = {0x87, // IRQL 0
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0x86, // IRQL 1
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0x84, // IRQL 2
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0x80, // Int0Dispatch Level
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// allow only Irql 8 (profiling & HIGH_LEVEL) ?!
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0x80, // IRQL 4
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0x80, // IRQL 5
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0x80, // IRQL 6
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0x80, // IRQL 7
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0x00}; // IRQL 8
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//
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// On an R4x00MC, all the interrupts enable/disable per processor is managed by the MPagent
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//
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/*+++ Note from Dave Cutler "Mr. NT"
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| How can this happen ?
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You cannot use the interrupt mask field of the status register to
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enable/disable per processor interrupts. In fact, the IRQL mask table
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that is initialized by the HAL must be the same for all processors.
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When threads start execution they have all interrupts in the
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interrupt mask field set according to the PASSIVE_LEVEL entry in the
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interrupt mapping table of the processor they start on. They are
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immediately context switchable. If per processor interrupts weere
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controlled by the interrupt mask field of the status register, then
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as soon as the thread got scheduled on another processor, the enables
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would no longer be correct.
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d
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---*/
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UCHAR HalpIrqlMask_MC[] = {4, 7, 6, 7, 5, 7, 6, 7, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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4, 4, 4, 4, 4, 4, 4, 4}; // 1000 - 1111 low 4-bits
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UCHAR HalpIrqlTable_MC[] = {0xff, // IRQL 0
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0xfe, // IRQL 1
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0xfc, // IRQL 2
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0xf8, // IRQL 3
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0xf0, // IRQL 4
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0xb0, // IRQL 5 NET
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0x90, // IRQL 6 CLOCK
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0x80, // IRQL 7 IPI
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0x00}; // IRQL 8
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UCHAR
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HalpIrqlMask_PC[] = {4, 5, 6, 6, 7, 7, 7, 7, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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4, 4, 4, 4, 4, 4, 4, 4}; // 1000 - 1111 low 4-bits
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UCHAR
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HalpIrqlTable_PC[] = {0xfb, // IRQL 0 1111 1011
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0xfa, // IRQL 1 1111 1010
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0xf8, // IRQL 2 1111 1000
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0xf8, // IRQL 3 1111 1000
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0xf0, // IRQL 4 1111 0000
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0xe0, // IRQL 5 1110 0000
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0xc0, // IRQL 6 1100 0000
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0x80, // IRQL 7 1000 0000
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0x00}; // IRQL 8 0000 0000
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VOID
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HalpCountInterrupt (
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VOID
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)
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/*++
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Routine Description:
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This function serves as the R4000 count/compare interrupt service
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routine early in the system initialization. Its only function is
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to field and acknowledge count/compare interrupts during the system
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boot process.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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extern ULONG HalpProfileInterval;
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//
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// Acknowledge the R4000 count/compare interrupt.
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//
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HalpProfileInterval = DEFAULT_PROFILE_INTERVAL;
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HalpCountCompareInterrupt = TRUE;
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HalpWriteCompareRegisterAndClear(DEFAULT_PROFILE_COUNT);
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return;
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}
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BOOLEAN
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HalpInitializeInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This function initializes interrupts for a MIPS R3000 or R4000 system.
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Arguments:
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None.
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Return Value:
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A value of TRUE is returned if the initialization is successfully
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completed. Otherwise a value of FALSE is returned.
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--*/
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{
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ULONG Index;
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PKPRCB Prcb;
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//
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// Get the address of the processor control block for the current
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// processor.
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//
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Prcb = PCR->Prcb;
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if (Prcb->Number == 0) {
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//
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// Initialize the IRQL translation tables in the PCR. These tables are
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// used by the interrupt dispatcher to determine the new IRQL and the
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// mask value that is to be loaded into the PSR. They are also used by
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// the routines that raise and lower IRQL to load a new mask value into
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// the PSR.
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//
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if (HalpIsRM200) {
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//
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// On an RM200 (Desktop) we have only 1 interrupt, which is like
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// the central Interrupt for R4x00SC machines
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask_SC); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_SC[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_SC); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_SC[Index];
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} else {
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//
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// if this is not a Desktop, we have to check if this is an
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// R4x00 SC model or a R4x00 MC (multiprocessor model)
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//
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if (HalpProcessorId == MPAGENT) {
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//
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// this is the boot processor in an MultiProcessor Environment
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask_MC); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_MC[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_MC); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_MC[Index];
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} else {
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if ((HalpProcPc) || (HalpProcessorId == ORIONSC)) {
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//
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// this is an R4000PC or a R4600 model in an UniProcessor Environment
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask_PC); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_PC[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_PC); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_PC[Index];
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} else {
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//
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// this is an R4x00SC model in an UniProcessor Environment
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask_SC); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_SC[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_SC); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_SC[Index];
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}
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}
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}
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//
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// the main system clock is always in the onboard PC core
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//
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PCR->InterruptRoutine[CLOCK2_LEVEL] = (PKINTERRUPT_ROUTINE)HalpStallInterrupt;
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//
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// If processor 0 is being initialized, then connect the count/compare
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// interrupt to the count interrupt routine to handle early count/compare
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// interrupts during phase 1 initialization. Otherwise, connect the
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// count\compare interrupt to the appropriate interrupt service routine.
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//
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//
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// force a CountCompare interrupt
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//
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HalpWriteCompareRegisterAndClear(100);
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PCR->InterruptRoutine[PROFILE_LEVEL] = HalpCountInterrupt;
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HalpProgramIntervalTimer (MAXIMUM_INCREMENT);
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HalpEnableOnboardInterrupt(CLOCK2_LEVEL,Latched); // Enable Timer1,Counter0 interrupt
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} else {
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//
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// MultiProcessorEnvironment Processor N
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask_MC); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_MC[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_MC); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_MC[Index];
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HalpProgramExtraTimer (MAXIMUM_INCREMENT);
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PCR->InterruptRoutine[EXTRA_CLOCK_LEVEL] = HalpClockInterrupt1;
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PCR->InterruptRoutine[PROFILE_LEVEL] = HalpProfileInterrupt;
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PCR->StallScaleFactor = HalpStallScaleFactor;
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}
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return TRUE;
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}
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