562 lines
17 KiB
ArmAsm
562 lines
17 KiB
ArmAsm
//#pragma comment(exestr, "$Header: /usr4/winnt/SOURCES/halpcims/src/hal/halsnipm/mips/RCS/orcache.s,v 1.3 1996/02/23 17:55:12 pierre Exp $")
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// TITLE("Cache Flush")
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//++
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//
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// Copyright (c) 1991-1993 Microsoft Corporation
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//
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// Module Name:
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//
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// orcache.s
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//
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// Abstract:
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//
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// This module implements the code necessary for cache operations on
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// R4600 orion Machines.
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//
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// Environment:
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//
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// Kernel mode only.
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//
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//--
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#include "halmips.h"
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#include "SNIdef.h"
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#define ORION_REPLACE 0x17c00000
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//
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// some bitmap defines to display cache activities via the LED's
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// in the SNI RM machines
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//
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#define SWEEP_DCACHE 0xc0 // 1100 0000
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#define FLUSH_DCACHE_PAGE 0x80 // 1000 0000
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#define PURGE_DCACHE_PAGE 0x40 // 0100 0000
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#define ZERO_PAGE 0x0c // 0000 1100
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#define SWEEP_ICACHE 0x30 // 0011 0000
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#define PURGE_ICACHE_PAGE 0x10 // 0001 0000
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//
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// Define cache operations constants.
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//
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#define COLOR_BITS (7 << PAGE_SHIFT) // color bit (R4000 - 8kb cache)
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#define COLOR_MASK (0x7fff) // color mask (R4000 - 8kb cache)
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#define FLUSH_BASE 0xfffe0000 // flush base address
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#define PROTECTION_BITS ((1 << ENTRYLO_V) | (1 << ENTRYLO_D) ) //
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SBTTL("Flush Data Cache Page")
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//++
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//
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// VOID
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// HalpFlushDcachePageOrion (
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// IN PVOID Color,
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// IN ULONG PageFrame,
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// IN ULONG Length
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// )
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//
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// Routine Description:
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//
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// This function flushes (cache replace) up to a page of data
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// from the secondary data cache. (primary cache is already processed)
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//
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// Arguments:
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//
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// Color (a0) - Supplies the starting virtual address and color of the
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// data that is flushed.
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//
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// PageFrame (a1) - Supplies the page frame number of the page that
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// is flushed.
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//
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// Length (a2) - Supplies the length of the region in the page that is
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// flushed.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpFlushDcachePageOrion)
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#if DBG
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lw t0,KeDcacheFlushCount // get address of dcache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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15: DISABLE_INTERRUPTS(t5) // disable interrupts
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.set noreorder
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.set noat
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//
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// Flush the secondary data caches => cache replace.
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//
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.set noreorder
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.set noat
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40: and a0,a0,PAGE_SIZE -1 // PageOffset
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sll t7,a1,PAGE_SHIFT // physical address
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lw t4,KiPcr + PcSecondLevelDcacheFillSize(zero) // get 2nd fill size
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or t0,t7,a0 // physical address + offset
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subu t6,t4,1 // compute block size minus one
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and t7,t0,t6 // compute offset in block
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addu a2,a2,t6 // round up to next block
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addu a2,a2,t7 //
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nor t6,t6,zero // complement block size minus one
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and a2,a2,t6 // truncate length to even number
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beq zero,a2,60f // if eq, no blocks to flush
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and t8,t0,t6 // compute starting virtual address
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addu t9,t8,a2 // compute ending virtual address
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subu t9,t9,t4 // compute ending loop address
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li a3,ORION_REPLACE // get base flush address
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lw t0,KiPcr + PcSecondLevelDcacheSize(zero) // get cache size
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add t0,t0,-1 // mask of the cache size
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.set noreorder
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.set noat
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50: and t7,t8,t0 // offset
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addu t7,t7,a3 // physical address + offset
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lw zero,0(t7) // load Cache -> Write back old Data
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bne t8,t9,50b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address (+Linesize)
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60: ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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.end HalpFlushDcachePageOrion
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SBTTL("Purge Instruction Cache Page")
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//++
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//
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// VOID
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// HalpPurgeIcachePageOrion (
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// IN PVOID Color,
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// IN ULONG PageFrame,
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// IN ULONG Length
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// )
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//
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// Routine Description:
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//
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// This function purges (hit/invalidate) up to a page of data from the
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// instruction cache.
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//
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// Arguments:
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//
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// Color (a0) - Supplies the starting virtual address and color of the
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// data that is purged.
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//
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// PageFrame (a1) - Supplies the page frame number of the page that
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// is purged.
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//
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// Length (a2) - Supplies the length of the region in the page that is
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// purged.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpPurgeIcachePageOrion)
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#if DBG
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lw t0,KeIcacheFlushCount // get address of icache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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15: DISABLE_INTERRUPTS(t5) // disable interrupts
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.set noreorder
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.set noat
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//
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// Flush the secondary data caches => cache replace.
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//
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.set noreorder
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.set noat
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40: and a0,a0,PAGE_SIZE -1 // PageOffset
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sll t7,a1,PAGE_SHIFT // physical address
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lw t4,KiPcr + PcSecondLevelIcacheFillSize(zero) // get 2nd fill size
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beq t4,zero,60f
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or t0,t7,a0 // physical address + offset
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subu t6,t4,1 // compute block size minus one
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and t7,t0,t6 // compute offset in block
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addu a2,a2,t6 // round up to next block
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addu a2,a2,t7 //
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nor t6,t6,zero // complement block size minus one
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and a2,a2,t6 // truncate length to even number
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beq zero,a2,60f // if eq, no blocks to flush
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and t8,t0,t6 // compute starting virtual address
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addu t9,t8,a2 // compute ending virtual address
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subu t9,t9,t4 // compute ending loop address
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li a3,ORION_REPLACE // get base flush address
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lw t0,KiPcr + PcSecondLevelIcacheSize(zero) // get cache size
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add t0,t0,-1 // mask of the cache size
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50: and t7,t8,t0 // offset
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addu t7,t7,a3 // physical address + offset
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lw zero,0(t7) // load Cache -> Write back old Data
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bne t8,t9,50b // if ne, more blocks to invalidate
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addu t8,t8,t4 // compute next block address (+Linesize)
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60: ENABLE_INTERRUPTS(t5) // enable interrupts
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j ra // return
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.end HalpPurgeIcachePageOrion
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SBTTL("Sweep Data Cache")
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//++
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//
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// VOID
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// HalpSweepDcacheOrion (
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// VOID
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// )
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//
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// Routine Description:
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//
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// This function sweeps (index/writeback/invalidate) the entire data cache.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSweepDcacheOrion)
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#if DBG
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lw t0,KeDcacheFlushCount // get address of dcache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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.set at
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.set reorder
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DISABLE_INTERRUPTS(t3) // disable interrupts
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.set noreorder
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.set noat
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//
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// Sweep the primary data cache.
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//
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lw t0,KiPcr + PcFirstLevelDcacheSize(zero) // get data cache size
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lw t1,KiPcr + PcFirstLevelDcacheFillSize(zero) // get block size
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li a0,KSEG0_BASE // set starting index value
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//
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// the size is configured on SNI machines as 16KB
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// we invalidate in both sets - so divide the configured size by 2
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//
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srl t0,t0,1
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addu a1,a0,t0 // compute ending cache address
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subu a1,a1,t1 // compute ending block address
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10:
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cache INDEX_WRITEBACK_INVALIDATE_D,0(a0) // writeback/invalidate on index
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cache INDEX_WRITEBACK_INVALIDATE_D,8192(a0)
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bne a0,a1,10b // if ne, more to invalidate
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addu a0,a0,t1 // compute address of next block
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//
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// sweep secondary cache
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//
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lw t0,KiPcr + PcSecondLevelDcacheSize(zero) // get data cache size
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lw t1,KiPcr + PcSecondLevelDcacheFillSize(zero) // get block size
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li a0,ORION_REPLACE // starting address
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addu a1,a0,t0 // compute ending cache address
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subu a1,a1,t1 // compute ending block address
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25:
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lw zero,0(a0)
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bne a0,a1,25b // if ne, more to invalidate
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addu a0,a0,t1 // compute address of next block
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ENABLE_INTERRUPTS(t3) // enable interrupts
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.set at
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.set reorder
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j ra // return
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.end HalpSweepDcacheMulti
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SBTTL("Sweep Instruction Cache")
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//++
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//
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// VOID
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// HalpSweepIcacheOrion (
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// VOID
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// )
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//
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// Routine Description:
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//
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// This function sweeps (index/invalidate) the entire instruction cache.
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(HalpSweepIcacheOrion)
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#if DBG
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lw t0,KeIcacheFlushCount // get address of icache flush count
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lw t1,0(t0) // increment the count of flushes
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addu t1,t1,1 //
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sw t1,0(t0) // store result
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#endif
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//
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// Sweep the secondary instruction cache.
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//
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.set noreorder
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.set noat
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DISABLE_INTERRUPTS(t3) // disable interrupts
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.set noreorder
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.set noat
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//
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// sweep secondary cache
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//
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lw t0,KiPcr + PcSecondLevelIcacheSize(zero) // get instruction cache size
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lw t1,KiPcr + PcSecondLevelIcacheFillSize(zero) // get fill size
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beq zero,t0,20f // if eq, no second level cache
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li a0,ORION_REPLACE // set starting index value
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addu a1,a0,t0 // compute ending cache address
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subu a1,a1,t1 // compute ending block address
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10: lw zero,0(a0)
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bne a0,a1,10b // if ne, more to invalidate
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addu a0,a0,t1 // compute address of next block
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//
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// Sweep the primary instruction cache.
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//
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20: lw t0,KiPcr + PcFirstLevelIcacheSize(zero) // get instruction cache size
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lw t1,KiPcr + PcFirstLevelIcacheFillSize(zero) // get fill size
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li a0,KSEG0_BASE // set starting index value
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//
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// the size is configured on SNI machines as 16KB
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// we invalidate in both sets - so divide the configured size by 2
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//
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srl t0,t0,1
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addu a1,a0,t0 // compute ending cache address
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subu a1,a1,t1 // compute ending block address
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//
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// Sweep the primary instruction cache.
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//
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30: cache INDEX_INVALIDATE_I,0(a0) // invalidate cache line
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cache INDEX_INVALIDATE_I,8192(a0)
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bne a0,a1,30b // if ne, more to invalidate
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addu a0,a0,t1 // compute address of next block
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.set at
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.set reorder
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20: ENABLE_INTERRUPTS(t3) // enable interrupts
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.set at
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.set reorder
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j ra // return
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.end HalpSweepIcacheOrion
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SBTTL("Zero Page")
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//++
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//
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// VOID
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// HalpZeroPageOrion (
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// IN PVOID NewColor,
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// IN PVOID OldColor,
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// IN ULONG PageFrame
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// )
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//
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// Routine Description:
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//
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// This function zeros a page of memory.
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//
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// The algorithm used to zero a page is as follows:
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//
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// 1. Purge (hit/invalidate) the page from the instruction cache
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// using the old color iff the old color is not the same as
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// the new color.
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//
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// 2. Purge (hit/invalidate) the page from the data cache using
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// the old color iff the old color is not the same as the new
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// color.
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//
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// 3. Create (create/dirty/exclusive) the page in the data cache
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// using the new color.
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//
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// 4. Write zeros to the page using the new color.
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//
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// Arguments:
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//
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// NewColor (a0) - Supplies the page aligned virtual address of the
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// new color of the page that is zeroed.
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//
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// OldColor (a1) - Supplies the page aligned virtual address of the
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// old color of the page that is zeroed.
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//
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// PageFrame (a2) - Supplies the page frame number of the page that
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// is zeroed.
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//
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// Return Value:
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//
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// None.
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//
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//--
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.struct 0
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.space 3 * 4 // fill
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ZpRa: .space 4 // saved return address
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ZpFrameLength: // length of stack frame
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ZpA0: .space 4 // (a0)
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ZpA1: .space 4 // (a1)
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ZpA2: .space 4 // (a2)
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ZpA3: .space 4 // (a3)
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NESTED_ENTRY(HalpZeroPageOrion, ZpFrameLength, zero)
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subu sp,sp,ZpFrameLength // allocate stack frame
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sw ra,ZpRa(sp) // save return address
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PROLOGUE_END
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and a0,a0,COLOR_BITS // isolate new color bits
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and a1,a1,COLOR_BITS // isolate old color bits
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sw a0,ZpA0(sp) // save new color bits
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sw a1,ZpA1(sp) // save old color bits
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sw a2,ZpA2(sp) // save page frame
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//
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// If the old page color is not equal to the new page color, then change
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// the color of the page.
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//
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beq a0,a1,10f // if eq, colors match
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jal KeChangeColorPage // chagne page color
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//
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// Create dirty exclusive cache blocks and zero the data.
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//
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10: lw a3,ZpA0(sp) // get new color bits
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lw a1,ZpA2(sp) // get page frame number
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.set noreorder
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.set noat
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lw v0,KiPcr + PcAlignedCachePolicy(zero) // get cache polciy
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li t0,FLUSH_BASE // get base flush address
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or t0,t0,a3 // compute new color virtual address
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sll t1,a1,ENTRYLO_PFN // shift page frame into position
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or t1,t1,PROTECTION_BITS // merge protection bits
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or t1,t1,v0 // merge cache policy
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and a3,a3,0x1000 // isolate TB entry index
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beql zero,a3,20f // if eq, first entry
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move t2,zero // set second page table entry
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move t2,t1 // set second page table entry
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move t1,zero // set first page table entry
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20: mfc0 t3,wired // get TB entry index
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lw t4,KiPcr + PcFirstLevelDcacheFillSize(zero) // get 1st fill size
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lw v0,KiPcr + PcSecondLevelDcacheFillSize(zero) // get 2nd fill size
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.set at
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.set reorder
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DISABLE_INTERRUPTS(t5) // disable interrupts
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.set noreorder
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.set noat
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mfc0 t6,entryhi // get current PID and VPN2
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srl t7,t0,ENTRYHI_VPN2 // isolate VPN2 of virtual address
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sll t7,t7,ENTRYHI_VPN2 //
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and t6,t6,0xff << ENTRYHI_PID // isolate current PID
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or t7,t7,t6 // merge PID with VPN2 of virtual address
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mtc0 t7,entryhi // set VPN2 and PID for probe
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mtc0 t1,entrylo0 // set first PTE value
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mtc0 t2,entrylo1 // set second PTE value
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mtc0 t3,index // set TB index value
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nop // fill
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tlbwi // write TB entry - 3 cycle hazzard
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addu t9,t0,PAGE_SIZE // compute ending address of block
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dmtc1 zero,f0 // set write pattern
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and t8,t4,0x10 // test if 16-byte cache block
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//
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// Zero page in primary and secondary data caches.
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//
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50: sdc1 f0,0(t0) // zero 64-byte block
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sdc1 f0,8(t0) //
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sdc1 f0,16(t0) //
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sdc1 f0,24(t0) //
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sdc1 f0,32(t0) //
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sdc1 f0,40(t0) //
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sdc1 f0,48(t0) //
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addu t0,t0,64 // advance to next 64-byte block
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bne t0,t9,50b // if ne, more to zero
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sdc1 f0,-8(t0) //
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||
|
||
.set at
|
||
.set reorder
|
||
|
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ENABLE_INTERRUPTS(t5) // enable interrupts
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||
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lw ra,ZpRa(sp) // get return address
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||
addu sp,sp,ZpFrameLength // deallocate stack frame
|
||
j ra // return
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||
|
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.end HalpZeroPageOrion
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||
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||
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