346 lines
10 KiB
C
346 lines
10 KiB
C
//#pragma comment(exestr, "$Header: /usr4/winnt/SOURCES/halpcims/src/hal/halsnipm/mips/RCS/xxinitnt.c,v 1.5 1996/03/04 13:29:07 pierre Exp $")
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/*++
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Copyright (c) 1993 - 1994 Siemens Nixdorf Informationssysteme AG
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Copyright (c) 1991 Microsoft Corporation
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Module Name:
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xxinitnt.c
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Abstract:
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This module implements the interrupt initialization for a MIPS R3000
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or R4000 system.
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Environment:
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Kernel mode only.
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--*/
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#include "halp.h"
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#include "eisa.h"
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extern BOOLEAN HalpCountCompareInterrupt;
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//
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// Define forward referenced prototypes.
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//
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VOID
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HalpAckExtraClockInterrupt(
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VOID
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);
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VOID
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HalpCountInterrupt (
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VOID
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);
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VOID
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HalpProgramIntervalTimer (
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IN ULONG Interval
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);
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VOID
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HalpProgramExtraTimer (
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IN ULONG Interval
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);
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VOID
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HalpProgramExtraTimerPciT (
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IN ULONG Interval
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);
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//
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// Put all code for HAL initialization in the INIT section. It will be
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// deallocated by memory management when phase 1 initialization is
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// completed.
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//
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(INIT, HalpInitializeInterrupts)
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#pragma alloc_text(INIT, HalpCountInterrupt)
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#endif
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//
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// Define the IRQL mask and level mapping table.
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//
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// These tables are transfered to the PCR and determine the priority of
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// interrupts.
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//
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// N.B. The two software interrupt levels MUST be the lowest levels.
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/*+++
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The interrupts bits in the cause Register have the following Hardware Interrupts:
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7 6 5 4 3 2 1 0
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+-------------------------------+
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| x | x | x | x | x | x | x | x |
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+-------------------------------+
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| | | | | | | |
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| | | | | | | +-------- APC LEVEL (Software)
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| | | | | | +------------ Dispatch LEVEL (Software)
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| | | | | +---------------- central Int0 (proc 0)
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| | | | +-------------------- None
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| | | +------------------------ None
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| | +---------------------------- TIMER (Proc 1 for RM300MP only)
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| +-------------------------------- DCU (Proc 1 for RM400MP only - proc 0 for RM400UP only)
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+------------------------------------ CountCompare (Profiling)
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---*/
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//
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// On an PCI Desktop or minitower single-processor (ORION), the processor has only 1 central
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// interrupt pin, so all should be directed to this interrupt, except the (internal)
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// CountCompare interrupt
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//
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UCHAR
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HalpIrqlMask_PCIs[] = {3, 3, 3, 3, 3, 3, 3, 3, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits (CountCompare only!)
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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3, 3, 3, 3, 3, 3, 3, 3}; // 1000 - 1111 low 4-bits
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UCHAR
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HalpIrqlTable_PCIs[] = {0x87, // IRQL 0
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0x86, // IRQL 1
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0x84, // IRQL 2
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0x80, // Int0Dispatch Level
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// allow only Irql 8 (profiling & HIGH_LEVEL) ?!
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0x80, // IRQL 4
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0x80, // IRQL 5
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0x80, // IRQL 6
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0x80, // IRQL 7
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0x00}; // IRQL 8
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//
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// On a PCI Tower, all the external interrupts are centralised
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// on one central pin except DCU on IP6 (because of the extra-timer).
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// The internal MP-Agent interrupt is directed on the seventh pin.
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//
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UCHAR
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HalpIrqlMask_PCIm_ExT[] = {3, 3, 6, 6, 7, 7, 7, 7, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits (CountCompare only!)
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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3, 3, 3, 3, 3, 3, 3, 3}; // 1000 - 1111 low 4-bits
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UCHAR
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HalpIrqlTable_PCIm_ExT[] = {0xe7, // IRQL 0
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0xe6, // IRQL 1
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0xe4, // IRQL 2
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0xe0, // Int0Dispatch Level
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0xe0, // IRQL 4
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0xe0, // IRQL 5
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0xc0, // IRQL 6
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0x80, // IRQL 7
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0x00}; // IRQL 8
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//
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// On a PCI multi-processor minitower (or mono-processor with MPagent),
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// all the external interrupts are centralised
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// on one central pin except extra-timer on IP6 (not used if mono).
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// The internal MP-Agent interrupt is directed on the seventh pin.
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//
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UCHAR
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HalpIrqlMask_PCIm[] = {3, 5, 3, 5, 7, 7, 7, 7, // 0000 - 0111 high 4-bits
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8, 8, 8, 8, 8, 8, 8, 8, // 1000 - 1111 high 4-bits (CountCompare only!)
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0, 1, 2, 2, 3, 3, 3, 3, // 0000 - 0111 low 4-bits
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3, 3, 3, 3, 3, 3, 3, 3}; // 1000 - 1111 low 4-bits
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UCHAR
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HalpIrqlTable_PCIm[] = {0xd7, // IRQL 0
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0xd6, // IRQL 1
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0xd4, // IRQL 2
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0xd0, // Int0Dispatch Level
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0xd0, // IRQL 4
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0xc0, // IRQL 5
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0xc0, // IRQL 6
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0x80, // IRQL 7
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0x00}; // IRQL 8
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VOID
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HalpCountInterrupt (
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VOID
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)
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/*++
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Routine Description:
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This function serves as the R4000 count/compare interrupt service
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routine early in the system initialization. Its only function is
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to field and acknowledge count/compare interrupts during the system
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boot process.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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extern ULONG HalpProfileInterval;
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//
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// Acknowledge the R4000 count/compare interrupt.
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//
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HalpProfileInterval = DEFAULT_PROFILE_INTERVAL;
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HalpCountCompareInterrupt = TRUE;
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HalpWriteCompareRegisterAndClear(DEFAULT_PROFILE_COUNT);
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return;
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}
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BOOLEAN
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HalpInitializeInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This function initializes interrupts for a MIPS R3000 or R4000 system.
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Arguments:
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None.
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Return Value:
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A value of TRUE is returned if the initialization is successfully
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completed. Otherwise a value of FALSE is returned.
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--*/
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{
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ULONG Index;
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PKPRCB Prcb;
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//
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// Get the address of the processor control block for the current
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// processor.
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//
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Prcb = PCR->Prcb;
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if (Prcb->Number == 0) {
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//
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// Initialize the IRQL translation tables in the PCR. These tables are
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// used by the interrupt dispatcher to determine the new IRQL and the
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// mask value that is to be loaded into the PSR. They are also used by
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// the routines that raise and lower IRQL to load a new mask value into
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// the PSR.
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//
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if (HalpProcessorId != MPAGENT) {
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//
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// this is a PCI desktop or a single-processor PCI minitower
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//
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for (Index = 0; Index < sizeof(HalpIrqlMask_PCIs); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_PCIs[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_PCIs); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_PCIs[Index];
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} else {
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//
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// this is a PCI minitower or PCI tower
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//
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if (HalpIsTowerPci){
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for (Index = 0; Index < sizeof(HalpIrqlMask_PCIm_ExT); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_PCIm_ExT[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_PCIm_ExT); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_PCIm_ExT[Index];
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}else{
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for (Index = 0; Index < sizeof(HalpIrqlMask_PCIm); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_PCIm[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_PCIm); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_PCIm[Index];
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}
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}
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//
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// the main system clock is always in the onboard PC core
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//
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PCR->InterruptRoutine[CLOCK2_LEVEL] = (PKINTERRUPT_ROUTINE)HalpStallInterrupt;
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//
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// force a CountCompare interrupt
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//
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HalpWriteCompareRegisterAndClear(100);
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//
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// If processor 0 is being initialized, then connect the count/compare
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// interrupt to the count interrupt routine to handle early count/compare
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// interrupts during phase 1 initialization. Otherwise, connect the
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// count\compare interrupt to the appropriate interrupt service routine.
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//
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PCR->InterruptRoutine[PROFILE_LEVEL] = HalpCountInterrupt;
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HalpProgramIntervalTimer (MAXIMUM_INCREMENT);
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HalpEnableOnboardInterrupt(CLOCK2_LEVEL,Latched); // Enable Timer1,Counter0 interrupt
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} else {
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//
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// MultiProcessorEnvironment Processor N
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//
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if (HalpIsTowerPci){
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for (Index = 0; Index < sizeof(HalpIrqlMask_PCIm_ExT); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_PCIm_ExT[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_PCIm_ExT); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_PCIm_ExT[Index];
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}else{
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for (Index = 0; Index < sizeof(HalpIrqlMask_PCIm); Index += 1)
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PCR->IrqlMask[Index] = HalpIrqlMask_PCIm[Index];
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for (Index = 0; Index < sizeof(HalpIrqlTable_PCIm); Index += 1)
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PCR->IrqlTable[Index] = HalpIrqlTable_PCIm[Index];
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}
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if (Prcb->Number==1){
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if (HalpIsTowerPci){
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HalpProgramExtraTimerPciT(MAXIMUM_INCREMENT);
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}else{
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HalpProgramExtraTimer (MAXIMUM_INCREMENT);
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PCR->InterruptRoutine[EXTRA_CLOCK_LEVEL] = HalpClockInterrupt1;
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}
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}
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PCR->InterruptRoutine[PROFILE_LEVEL] = HalpProfileInterrupt;
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PCR->StallScaleFactor = HalpStallScaleFactor;
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}
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return TRUE;
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}
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