751 lines
20 KiB
NASM
751 lines
20 KiB
NASM
title "Interprocessor Interrupt"
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;++
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;
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;Copyright (c) 1991 Microsoft Corporation
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;
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;Module Name:
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;
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; spipi.asm
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;
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;Abstract:
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;
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; SystemPro IPI code.
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; Provides the HAL support for Interprocessor Interrupts for hte
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; MP SystemPro implementation.
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;
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;Author:
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;
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; Ken Reneris (kenr) 13-Jan-1992
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;
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;Revision History:
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;
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;--
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.386p
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; .xlist
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;
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; Include SystemPro detection code
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;
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include i386\spdetect.asm
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;
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; Normal includes
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;
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include hal386.inc
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include i386\kimacro.inc
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include i386\ix8259.inc
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include callconv.inc ; calling convention macros
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EXTRNP _KiCoprocessorError,0,IMPORT
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EXTRNP Kei386EoiHelper,0,IMPORT
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EXTRNP _KeRaiseIrql,2
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EXTRNP _HalBeginSystemInterrupt,3
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EXTRNP _HalEndSystemInterrupt,2
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EXTRNP _KiIpiServiceRoutine,2,IMPORT
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EXTRNP _HalEnableSystemInterrupt,3
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EXTRNP _HalpInitializePICs,0
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EXTRNP _HalDisplayString,1
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EXTRNP _HalEnableSystemInterrupt,3
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EXTRNP _HalDisableSystemInterrupt,2
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EXTRNP _HalpMapPhysicalMemory,2
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EXTRNP _HalpAcerInitializeCache,0
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extrn _HalpDefaultInterruptAffinity:DWORD
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extrn _HalpActiveProcessors:DWORD
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extrn _HalpCpuCount:DWORD
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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public _HalpFindFirstSetRight, _Sp8259PerProcessorMode
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_HalpFindFirstSetRight db 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0
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_Sp8259PerProcessorMode db 0
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align 4
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public _HalpProcessorPCR
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_HalpProcessorPCR dd MAXIMUM_PROCESSORS dup (?) ; PCR pointer for each processor
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_HalpPINTAddrTable label word
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dw SMP_MPINT0
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dw SMP_MPINT1
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dw SMP_MPINT3
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dw SMP_MPINT4
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dw SMP_MPINT5
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dw SMP_MPINT6
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dw SMP_MPINT7
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dw SMP_MPINT8
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dw SMP_MPINT9
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dw SMP_MPINT10
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dw SMP_MPINT11
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dw SMP_MPINT12
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dw SMP_MPINT13
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dw SMP_MPINT14
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dw SMP_MPINT15
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HALPPINTADDRTABLESIZE equ ($-_HalpPINTAddrTable)/TYPE(_HalpPINTAddrTable)
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BadHalString db 'HAL: SystemPro HAL.DLL cannot be run on non SystemPro'
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db '/compatible', cr,lf
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db ' Replace the hal.dll with the correct hal', cr, lf
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db ' System is HALTING *********', 0
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_DATA ends
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page ,132
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subttl "Post InterProcessor Interrupt"
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;
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; VOID
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; HalInitializeProcessor(
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; ULONG Number
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; );
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;
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;Routine Description:
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;
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; Initialize hal pcr values for current processor (if any)
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; (called shortly after processor reaches kernel, before
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; HalInitSystem if P0)
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;
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; IPI's and KeReadir/LowerIrq's must be available once this function
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; returns. (IPI's are only used once two or more processors are
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; available)
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;
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; . Enable IPI interrupt (makes sense for P1, P2, ...).
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; . Save Processor Number in PCR.
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; . if (P0)
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; . determine what kind of system is it,
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; . if (NotSysProCompatible) Halt;
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; . program VECTOR_PORT to accept IPI at IRQ13.
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; . InitializePICs.
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; . if (P1)
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; . Save ProcesserControlPort (PCR) to PCRegion, per processor.
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; . Enable PINTs on CPU.
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;
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;Arguments:
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;
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; Number - Logical processor number of calling processor
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalInitializeProcessor ,1
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;
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; Initialize various PCR values
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; PcIDR in PCR - enable slave IRQ
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; PcStallScaleFactor - bogusly large value for now
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; PcHal.PcrNumber - logical processor #
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; PcHal.PcrPic - Set if processor has it's own pics.
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; The SystemPro only defines one pic set on P0, but some clones
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; put more pics on each other processor. This isn't vastly
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; better, but it is better then processor. This isn't vastly 'em
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; PcHal.PcrIpiType - Address to jmp to once ipi is verified.
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; This is done to optimize how to deal with a varity of 'work-
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; arounds' due to non-smp nature of SP clones
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;
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cli
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mov fs:PcIDR, 0fffffffbh
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movzx eax, byte ptr [esp+4]
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mov fs:PcHal.PcrNumber, al ; Save processor # in PCR
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lock bts _HalpActiveProcessors, eax
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lock inc _HalpCpuCount
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mov dword ptr fs:PcStallScaleFactor, INITIAL_STALL_COUNT
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mov dword ptr fs:PcHal.PcrPerfSkew, 0
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mov fs:PcHal.PcrIpiSecondLevelDispatch, offset _HalpNo2ndDispatch
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;
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; Initialize IDT vector for IPI interrupts
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; KiSetHandlerAddressToIDT(I386_80387_VECTOR, HalpIrq13Handler);
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;
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mov ebx, fs:PcIDT
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lea ecx, _HalpIrq13Handler
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add ebx, (PRIMARY_VECTOR_BASE + 13) * 8
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mov word ptr [ebx+0], cx
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shr ecx, 16
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mov word ptr [ebx+6], cx
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;
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; Save away flat address of our PCR - (used in emulating clock ticks
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; on systempro p1 which doesn't have it's own clock tick)
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;
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mov ecx, fs:PcSelfPcr ; Flat address of this PCR
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mov _HalpProcessorPCR[eax*4], ecx ; Save it away
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or eax, eax
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jnz ipi_10 ; If !p0 then ipi_10
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mov fs:PcHal.PcrPic, 1 ; P0 has a pic
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mov fs:PcHal.PcrIpiType, offset P0Ipi
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; Run on P0 only
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sub esp, 4
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stdCall _DetectSystemPro,<esp> ; Which type of SystemPro
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add esp,4
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or eax, eax
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jz NotSystemPro
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lock or _HalpDefaultInterruptAffinity, 1
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cmp _SpType, SMP_SYSPRO2 ; Belize SystemPro?
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je short ipi_belize
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;
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; Set all processors IPI to irq13
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;
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mov al, PRIMARY_VECTOR_BASE + 13
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mov dx, 0FC68h ; Set SystemPro P1 Interrupt
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out dx, al ; Vector to irq13
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cmp _SpType, SMP_ACER ; Acer? Then set other acer
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jne short ipi_notacer ; processor ports as well
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mov dx, 0C028h
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out dx, al ; set P2 Interrupt Vector
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mov dx, 0C02Ch
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out dx, al ; set P3 Interrupt Vector
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stdCall _HalpAcerInitializeCache
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mov dx, 0C06h ; Check for ASMP or SMP mode
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in al, dx
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test al, 10h ; SMP mode bit set?
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jz short @f ; No, then ASMP mode
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cmp al, 0ffh ; Ambra doesn't implement
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je short @f ; this port...
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;; bugbug - problems with bootup device
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;; mov _Sp8259PerProcessorMode, SP_M8259 + SP_SMPDEVINTS
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mov _Sp8259PerProcessorMode, SP_M8259 ; Set to use multiple pic
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@@: jmp short ipi_05 ; implementation
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ipi_belize:
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;
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; Machine is Belize SystemPro
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; Set for multiple 8259s, statically distribute device interrupts, and
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; use symmetric clock interrupt.
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;
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mov _Sp8259PerProcessorMode, SP_M8259 + SP_SMPDEVINTS + SP_SMPCLOCK
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stdCall HalpInitializeBelizeIC
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ipi_notacer:
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ipi_05:
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; enable IPI vector
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stdCall _HalEnableSystemInterrupt,<PRIMARY_VECTOR_BASE+13,IPI_LEVEL,0>
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; Other P0 initialization would go here
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jmp short ipi_30
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ipi_10:
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mov fs:PcHal.PcrIpiType, offset IpiWithNoPic ; default it
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test _Sp8259PerProcessorMode, SP_M8259 ; 8259 on this processor?
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jz short ipi_20
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;
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; SP machine is set for SMP mode - which has 2 8259s per processor
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;
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mov fs:PcHal.PcrPic, 1 ; Set to use pic on this proc
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cmp _SpType, SMP_ACER
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jne short ipi_notacer2
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;
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; Machine is in ACER "SMP" mode - well, this fine SMP mode happens
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; to have an asymmetric clock interrupt, so we need to emulate non-
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; P0 clock interrupts to it just like we do on the standard SystemPro
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;
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mov fs:PcHal.PcrIpiType, offset IpiWithPicButNoClock
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stdCall _HalpInitializePICs ; Init this processors PICs
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ipi_notacer2:
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cmp _SpType, SMP_SYSPRO2
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jne short ipi_notbelize2
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;
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; Machine is Belize SystemPro
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;
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stdCall HalpInitializeBelizeIC
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ipi_notbelize2:
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;
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; Enable IPI vector for non-P0 cpu
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;
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stdCall _HalEnableSystemInterrupt,<PRIMARY_VECTOR_BASE+13, IPI_LEVEL,0>
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ipi_20:
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; Specific non-P0 initialization would go here
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ipi_30:
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movzx eax, byte ptr [esp+4] ; cpu number
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mov dx, _SpProcessorControlPort[eax*2] ; Port value for this processor
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mov fs:PcHal.PcrControlPort, dx ; Save port value
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mov fs:PcHal.PcrIpiClockTick, 0 ; Set to not signaled
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cmp _SpType, SMP_SYSPRO2
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je short @f
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in al, dx ; remove disabled & signaled
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and al, not (INTDIS or PINT) ; bits
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out dx, al
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@@:
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stdRET _HalInitializeProcessor
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NotSystemPro:
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; on a non system pro. Display message and HALT system.
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stdCall _HalDisplayString, <offset BadHalString>
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hlt
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stdENDP _HalInitializeProcessor
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;++
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;
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; VOID
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; HalpInitializeBelizeIC(
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; VOID
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; );
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;
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;Routine Description:
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;
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; Initialize interrupt control for the Belize SystemPro
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc HalpInitializeBelizeIC, 0
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push ebx
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;
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; Belize IPIs go to Belize Irq13 handler
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;
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mov ebx, fs:PcIDT
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lea ecx, _HalpBelizeIrq13Handler
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add ebx, (PRIMARY_VECTOR_BASE + 13) * 8
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mov word ptr [ebx+0], cx
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shr ecx, 16
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mov word ptr [ebx+6], cx
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;
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; Disable irq13 sources
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;
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mov dx, SMP_MPINT13PORT
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mov al, (SMP_DSBL_NCPERR + SMP_DSBL_DMACHAIN + SMP_DSBL_MCERR)
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out dx, al
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;
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; Disable ipi ports
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;
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mov ecx, HALPPINTADDRTABLESIZE
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xor ebx, ebx
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mov al, SMP_INTx_DISABLE
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@@:
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mov dx, _HalpPINTAddrTable[ ebx ]
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out dx, al
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add ebx, 2
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loopnz short @b
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stdCall _HalpInitializePICs ; Init this processors PICs
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;
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; Enable PINT
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;
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mov dx, SMP_IPI_MPINTx_PORT
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mov al, SMP_INTx_ENABLE + SMP_INTx_CLR_PINT
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out dx, al
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pop ebx
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stdRet HalpInitializeBelizeIC
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stdENDP HalpInitializeBelizeIC
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;++
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;
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; VOID
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; HalRequestIpi(
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; IN ULONG Mask
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; );
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;
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;Routine Description:
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;
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; Requests an interprocessor interrupt
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;
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;Arguments:
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;
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; Mask - Supplies a mask of the processors to be interrupted
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalRequestIpi ,1
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cmp _SpType, SMP_SYSPRO2
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jne short ripi_10
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mov eax, dword ptr [esp+4] ; (eax) = Processor bitmask
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if DBG
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or eax, eax ; must ipi somebody
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jz short ipibad
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movzx ecx, byte ptr fs:PcHal.PcrNumber
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bt eax, ecx ; cannot ipi yourself
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jc short ipibad
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endif
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mov dx, SMP_IPI_MASKPORT
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or eax, (SMP_IPI_VECTOR shl 24)
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out dx, eax
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stdRET _HalRequestIpi
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ALIGN 4
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ripi_10:
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mov ecx, dword ptr [esp+4] ; (ecx) = Processor bitmask
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if DBG
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or ecx, ecx ; must ipi somebody
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jz short ipibad
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movzx eax, byte ptr fs:PcHal.PcrNumber
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bt ecx, eax ; cannot ipi yourself
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jc short ipibad
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endif
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@@:
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movzx eax, _HalpFindFirstSetRight[ecx] ; lookup first processor to ipi
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btr ecx, eax
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mov dx, _SpProcessorControlPort[eax*2]
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in al, dx ; (al) = original content of PCP
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or al, PINT ; generate Ipi on target
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out dx, al
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or ecx, ecx ; ipi any other processors?
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jnz @b ; yes, loop
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stdRET _HalRequestIpi
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if DBG
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ipibad: int 3
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stdRET _HalRequestIpi
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endif
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stdENDP _HalRequestIpi
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page ,132
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subttl "SystemPro Irq13 Interrupt Handler"
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;++
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;
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; VOID
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; HalpIrq13Handler (
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; );
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;
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; Routine Description:
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;
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; This routine is entered as the result of an interrupt generated by inter
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; processor communication or coprocessor error.
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; Its function is to determine the sources of the interrupts and to
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; call its handler.
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;
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; If the interrupt is determined to be generated by coprocessor error,
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; this routine will lower irql to its original level, and finally invoke
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; coprocessor error handler. By doing this, the coprocessor
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; error will be handled at Irql 0 as it should be.
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;
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; N.B. This routine is specific to Compaq SystemPro. On SystemPro, the
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; IRQ13 of P0 is also used by DMA buffer chaining interrupt. Currently,
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; NO NT driver uses the DMA buffer chaining capability. For now, this
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; routine simply ignores it.
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;
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; Arguments:
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;
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; None.
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; Interrupt is dismissed
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;
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; Return Value:
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;
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; None.
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;
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;--
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ENTER_DR_ASSIST Hi13_a, Hi13_t
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cPublicProc _HalpIrq13Handler ,0
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;
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; Save machine state in trap frame
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;
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ENTER_INTERRUPT Hi13_a, Hi13_t ; (ebp) -> Trap frame
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;
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; Save previous IRQL
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;
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push 13 + PRIMARY_VECTOR_BASE ; Vector
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sub esp, 4 ; space for OldIrql
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;
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; Dismiss interrupt.
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;
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mov dx, fs:PcHal.PcrControlPort
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in al, dx
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test al, PINT
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jz Hi100 ; if not a PINT, then go Hi100
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;
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; The interrupt has been identified to be Inter-Processor Interrupt
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; We now dismiss the interprocessor interrupt and call its handler
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;
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and al, not (PINT or INTDIS)
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out dx, al ; clear PINT
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jmp fs:[PcHal.PcrIpiType] ; Go handle ipi accordingly
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align 4
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IpiWithNoPic:
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;
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; This processor doesn't have a PIC
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;
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cmp byte ptr fs:PcIrql, IPI_LEVEL ; is preview IRQL level
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jnc short Ksi20 ; >= IPI_LEVEL?
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; WARNING: Some SystemPro's actually don't complete the OUT to the
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; ProcessorControlRegister by the return of the OUT instruction. This
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; code path can do a 'sti' before the pending interrupt bit is cleared
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; on these machines. To get around this problem we do an IN from the
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; ProcessorControlPort again which will cause the last OUT to complete
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; before the IN can.
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in al, dx
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stdCall _KeRaiseIrql, <IPI_LEVEL,esp>
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;
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; It also doesn't have it's own clock interrupt, see if clock interrupt
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; emulation is requested - if so raise a software interrupt to go emulate
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; it when we reach a lower IRQL
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;
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cmp fs:PcHal.PcrIpiClockTick, 0 ; Emulate ClockTick?
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jz short Ksi30 ; No, just go service ipi
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mov fs:PcHal.PcrIpiClockTick, 0 ; yes, reset trigger
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or dword ptr fs:PcIRR, SWClockTick ; Set SW ClockTick bit
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jmp short Ksi30 ; go process ipi
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Ksi20:
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;
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; This processor is >= IPI_LEVEL, this IPI should not be here.
|
|
;
|
|
in al, dx
|
|
or al, PINT ; re-post this IPI
|
|
out dx, al
|
|
; clear IF bit in return EFLAGS
|
|
add esp, 8
|
|
and dword ptr [esp].TsEflags, NOT 200h
|
|
SPURIOUS_INTERRUPT_EXIT
|
|
|
|
align 4
|
|
IpiWithPicButNoClock:
|
|
cmp fs:PcHal.PcrIpiClockTick, 0 ; Emulate ClockTick?
|
|
jz short SymmetricIpi
|
|
|
|
mov fs:PcHal.PcrIpiClockTick, 0
|
|
or dword ptr fs:PcIRR, SWClockTick ; Set SW ClockTick bit
|
|
|
|
align 4
|
|
P0Ipi:
|
|
SymmetricIpi:
|
|
stdCall _HalBeginSystemInterrupt,<IPI_LEVEL,13 + PRIMARY_VECTOR_BASE,esp>
|
|
; or eax, eax NOTNOW: To add lazy irql support, this
|
|
; jz short KsiSpuripus needs to be added - and IpiWithNoPic
|
|
; would need fixed as well
|
|
|
|
Ksi30:
|
|
; Pass Null ExceptionFrame
|
|
; Pass TrapFrame to Ipi service rtn
|
|
stdCall _KiIpiServiceRoutine, <ebp,0>
|
|
|
|
Hi90: call fs:[PcHal.PcrIpiSecondLevelDispatch]
|
|
|
|
;
|
|
; Do interrupt exit processing
|
|
;
|
|
|
|
INTERRUPT_EXIT ; will return to caller
|
|
|
|
Hi100:
|
|
mov esi, eax ; save control register
|
|
mov edi, edx ; save control port
|
|
|
|
cmp byte ptr fs:PcHal.PcrPic, 0 ; A pic on this processor?
|
|
je short Hi120
|
|
|
|
stdCall _HalBeginSystemInterrupt, <IPI_LEVEL,13 + PRIMARY_VECTOR_BASE,esp>
|
|
jmp short Hi130
|
|
Hi120:
|
|
stdCall _KeRaiseIrql, <IPI_LEVEL,esp>
|
|
Hi130:
|
|
test esi, ERR387 ; Interrupt from 387?
|
|
jz short Hi90 ; No, then unkown exit
|
|
|
|
xor al,al
|
|
out I386_80387_BUSY_PORT, al
|
|
|
|
mov eax, esi
|
|
and eax, NOT ERR387
|
|
mov edx, edi
|
|
out dx, al ; clear ERR387
|
|
|
|
mov eax, PCR[PcPrcb]
|
|
cmp byte ptr [eax].PbCpuType, 4 ; Is this a 386?
|
|
jc short Hi40 ; Yes, then don't check CR0_NE
|
|
|
|
mov eax, cr0 ; Is CR0_NE set? If so, then
|
|
test eax, CR0_NE ; we shouldn't be getting NPX
|
|
jnz short Hi50 ; interrupts.
|
|
Hi40:
|
|
stdCall _KiCoprocessorError ; call CoprocessorError handler
|
|
Hi50:
|
|
|
|
;
|
|
; We did an out to the ProcessorControl port which might have cleared a
|
|
; pending interrupt (PINT) bit. Go process ipi handler just in case.
|
|
;
|
|
jmp Ksi30
|
|
|
|
stdENDP _HalpIrq13Handler
|
|
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpBelizeIrq13Handler (
|
|
; );
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; Same as HalpIrql13Handler, expect specific to the Belize SyetemPro
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None.
|
|
; Interrupt is dismissed
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None.
|
|
;
|
|
;--
|
|
|
|
ENTER_DR_ASSIST Hib13_a, Hib13_t
|
|
|
|
cPublicProc _HalpBelizeIrq13Handler ,0
|
|
ENTER_INTERRUPT Hib13_a, Hib13_t ; (ebp) -> Trap frame
|
|
|
|
push 13 + PRIMARY_VECTOR_BASE ; Vector
|
|
sub esp, 4 ; space for OldIrql
|
|
|
|
stdCall _HalBeginSystemInterrupt,<IPI_LEVEL,13 + PRIMARY_VECTOR_BASE,esp>
|
|
|
|
mov dx, SMP_IPI_MPINTx_PORT
|
|
in al, dx ; read clears pending int
|
|
|
|
stdCall _KiIpiServiceRoutine, <ebp,0>
|
|
|
|
call fs:[PcHal.PcrIpiSecondLevelDispatch]
|
|
|
|
|
|
;
|
|
; Do interrupt exit processing
|
|
;
|
|
|
|
INTERRUPT_EXIT ; will return to caller
|
|
|
|
|
|
stdENDP _HalpBelizeIrq13Handler
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpNoSecondDispatch (
|
|
; VOID
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; Does nothing
|
|
;--
|
|
cPublicProc _HalpNo2ndDispatch,0
|
|
stdRET _HalpNo2ndDispatch
|
|
stdENDP _HalpNo2ndDispatch
|
|
|
|
|
|
|
|
;++
|
|
;
|
|
; ULONG
|
|
; FASTCALL
|
|
; HalSystemVectorDispatchEntry (
|
|
; IN ULONG Vector,
|
|
; OUT PKINTERRUPT_ROUTINE **FlatDispatch,
|
|
; OUT PKINTERRUPT_ROUTINE *NoConnection
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; If TRUE, returns dispatch address for vector; otherwise, IDT dispatch is
|
|
; assumed
|
|
;
|
|
; Arguments:
|
|
;
|
|
; Vector - System Vector to get dispatch address of
|
|
; FlatDispatch - Returned dispatched address for system vector
|
|
; NoConnection - Returned "no connection" dispatch value for system vector
|
|
;
|
|
;--
|
|
|
|
cPublicFastCall HalSystemVectorDispatchEntry,3
|
|
|
|
xor eax, eax ; reutrn FALSE
|
|
|
|
cmp ecx, PRIMARY_VECTOR_BASE + SECOND_IPI_DISPATCH
|
|
jne short hsvexit
|
|
|
|
inc eax ; return TRUE
|
|
|
|
mov ecx, PCR[PcSelfPcr] ; return FlatDispatch
|
|
add ecx, PcHal.PcrIpiSecondLevelDispatch
|
|
mov [edx], ecx
|
|
|
|
mov ecx, [esp+4] ; return NoConnection
|
|
mov [ecx], offset _HalpNo2ndDispatch
|
|
|
|
hsvexit:
|
|
fstRET HalSystemVectorDispatchEntry
|
|
fstENDP HalSystemVectorDispatchEntry
|
|
|
|
|
|
_TEXT ENDS
|
|
END
|