620 lines
11 KiB
C
620 lines
11 KiB
C
/*++
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Copyright (c) 1990 Microsoft Corporation
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Copyright (c) 1992, 1993 Digital Equipment Corporation
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Module Name:
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ebintsup.c
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Abstract:
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The module provides the interrupt support for EB164 systems.
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Author:
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Eric Rehm (DEC) 29-December-1993
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Revision History:
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Chao Chen (DEC) 06-Sept-1994
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Adapted from Avanti module for EB164.
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--*/
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#include "halp.h"
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#include "eisa.h"
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#include "ebsgdma.h"
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#include "eb164.h"
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#include "pcrtc.h"
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#include "pintolin.h"
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//
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// Declare the interrupt masks.
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//
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UCHAR IntMask0, IntMask1, IntMask2;
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//
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// Define the context structure for use by interrupt service routines.
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//
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typedef BOOLEAN (*PSECOND_LEVEL_DISPATCH)(
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PKINTERRUPT InterruptObject,
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PVOID ServiceContext,
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PKTRAP_FRAME TrapFrame
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);
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//
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// The following is the interrupt object used for DMA controller interrupts.
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// DMA controller interrupts occur when a memory parity error occurs or a
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// programming error occurs to the DMA controller.
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//
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KINTERRUPT HalpEisaNmiInterrupt;
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//
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// The following function initializes NMI handling.
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//
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VOID
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HalpInitializeNMI(
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VOID
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);
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//
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// The following function is called when an ISA NMI occurs.
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//
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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);
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//
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// The following functions handle the PCI interrupts.
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//
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VOID
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HalpInitializePciInterrupts (
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VOID
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);
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VOID
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HalpDisablePciInterrupt(
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IN ULONG Vector
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);
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VOID
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HalpEnablePciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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);
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BOOLEAN
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HalpPciDispatch(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PKTRAP_FRAME TrapFrame
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);
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BOOLEAN
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HalpInitializeEB164Interrupts (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the structures necessary for ISA & PCI operations
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and connects the intermediate interrupt dispatchers. It also initializes
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the ISA interrupt controller.
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Arguments:
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None.
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Return Value:
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If the second level interrupt dispatchers are connected, then a value of
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TRUE is returned. Otherwise, a value of FALSE is returned.
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--*/
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{
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KIRQL oldIrql;
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//
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// Initialize the ISA NMI interrupt.
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//
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HalpInitializeNMI();
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(PVOID) HalpPCIPinToLineTable = (PVOID) EB164PCIPinToLineTable;
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//
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// Intitialize interrupt controller
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//
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KeRaiseIrql(DEVICE_HIGH_LEVEL, &oldIrql);
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//
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// Initialize the PCI interrupts.
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//
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HalpInitializePciInterrupts();
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//
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// Initialize the SIO's PICs for ISA interrupts.
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//
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HalpInitializeSioInterrupts();
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//
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// Restore the IRQL.
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//
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KeLowerIrql(oldIrql);
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//
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// Initialize the EISA DMA mode registers to a default value.
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// Disable all of the DMA channels except channel 4 which is the
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// cascade of channels 0-3.
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//
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma1BasePort.AllMask,
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0x0F
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);
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->Dma2BasePort.AllMask,
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0x0E
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);
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return(TRUE);
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}
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VOID
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HalpInitializeNMI(
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VOID
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)
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/*++
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Routine Description:
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This function is called to intialize ESC NMI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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UCHAR DataByte;
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//
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// Initialize the ESC NMI interrupt.
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//
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KeInitializeInterrupt( &HalpEisaNmiInterrupt,
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HalHandleNMI,
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NULL,
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NULL,
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EISA_NMI_VECTOR,
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EISA_NMI_LEVEL,
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EISA_NMI_LEVEL,
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LevelSensitive,
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FALSE,
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0,
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FALSE
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);
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//
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// Don't fail if the interrupt cannot be connected.
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//
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KeConnectInterrupt( &HalpEisaNmiInterrupt );
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//
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// Clear the Eisa NMI disable bit. This bit is the high order of the
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// NMI enable register.
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//
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DataByte = 0;
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WRITE_PORT_UCHAR(
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&((PEISA_CONTROL) HalpEisaControlBase)->NmiEnable,
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DataByte
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);
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}
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BOOLEAN
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HalHandleNMI(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext
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)
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/*++
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Routine Description:
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This function is called when an EISA NMI occurs. It prints the
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appropriate status information and bugchecks.
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object
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ServiceContext - Bug number to call bugcheck with.
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Return Value:
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Returns TRUE.
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--*/
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{
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UCHAR StatusByte;
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StatusByte =
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READ_PORT_UCHAR(&((PEISA_CONTROL) HalpEisaControlBase)->NmiStatus);
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if (StatusByte & 0x80) {
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HalDisplayString ("NMI: Parity Check / Parity Error\n");
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}
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if (StatusByte & 0x40) {
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HalDisplayString ("NMI: Channel Check / IOCHK\n");
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}
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KeBugCheck(NMI_HARDWARE_FAILURE);
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return(TRUE);
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}
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VOID
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HalpAcknowledgeClockInterrupt(
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VOID
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)
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/*++
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Routine Description:
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Acknowledge the clock interrupt from the interval timer. The interval
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timer for EB164 comes from a Dallas real-time clock.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Acknowledge the clock interrupt by reading the control register C of
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// the Real Time Clock.
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//
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HalpReadClockRegister( RTC_CONTROL_REGISTERC );
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return;
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}
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VOID
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HalpInitializePciInterrupts (
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VOID
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)
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/*++
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Routine Description:
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This routine initializes the EB164 PCI interrupts.
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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//
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// Clear all interrupt masks.
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// Enable the SIO interrupt in the mask.
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//
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IntMask0 = 0x10;
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IntMask1 = 0x00;
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IntMask2 = 0x00;
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//
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// Disable interrupts except for SIO.
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//
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA, ~IntMask0);
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA, ~IntMask1);
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA, ~IntMask2);
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}
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VOID
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HalpDisablePciInterrupt(
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IN ULONG Vector
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)
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/*++
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Routine Description:
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This function disables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is disabled.
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0.
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//
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Vector -= PCI_VECTORS;
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//
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// Get the current state of the interrupt mask register, then set
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// the bit corresponding to the adjusted value of Vector to zero,
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// to disable that PCI interrupt.
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//
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if (Vector >= 0 && Vector <= 7) {
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IntMask0 &= (UCHAR)~(1 << Vector);
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA, ~IntMask0);
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} else if (Vector >= 8 && Vector <= 0xf) {
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IntMask1 &= (UCHAR)~(1 << (Vector - 8));
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA, ~IntMask1);
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} else if (Vector >= 0x10 && Vector <=0x17) {
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IntMask2 &= (UCHAR)~(1 << (Vector - 16));
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA, ~IntMask2);
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} else {
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#if HALDBG
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DbgPrint("HalpDisablePciInterrupt: bad vector!\n");
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#endif
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}
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}
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VOID
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HalpEnablePciInterrupt(
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IN ULONG Vector,
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IN KINTERRUPT_MODE InterruptMode
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)
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/*++
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Routine Description:
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This function enables the PCI interrupt specified by Vector.
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Arguments:
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Vector - Supplies the vector of the PCI interrupt that is enabled.
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InterruptMode - Supplies the mode of the interrupt; LevelSensitive or
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Latched (ignored for EB164 PCI interrupts; they're always levels).
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Return Value:
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None.
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--*/
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{
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//
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// Calculate the PCI interrupt vector, relative to 0.
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//
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Vector -= PCI_VECTORS;
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//
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// Get the current state of the interrupt mask register, then set
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// the bit corresponding to the adjusted value of Vector to one,
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// to ensable that PCI interrupt.
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//
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if (Vector >= 0 && Vector <= 7) {
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IntMask0 |= (UCHAR) (1 << Vector);
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA, ~IntMask0);
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} else if (Vector >= 8 && Vector <= 0xf) {
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IntMask1 |= (UCHAR) (1 << (Vector - 8));
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA, ~IntMask1);
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} else if (Vector >= 0x10 && Vector <= 0x17) {
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IntMask2 |= (UCHAR) (1 << (Vector - 16));
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WRITE_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA, ~IntMask2);
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} else {
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#if HALDBG
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DbgPrint("HalpEnablePciInterrupt: bad vector!\n");
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#endif
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}
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}
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BOOLEAN
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HalpDeviceDispatch(
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IN PKINTERRUPT Interrupt,
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IN PVOID ServiceContext,
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IN PKTRAP_FRAME TrapFrame
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)
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/*++
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Routine Description:
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This routine is entered as the result of an interrupt being generated
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via the vector that is connected to an interrupt object associated with
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the PCI device interrupts. Its function is to call the second-level
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interrupt dispatch routine.
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Arguments:
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Interrupt - Supplies a pointer to the interrupt object.
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ServiceContext - Supplies a pointer to the PCI interrupt register.
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TrapFrame - Supplies a pointer to the trap frame for this interrupt.
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Return Value:
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Returns the value returned from the second level routine.
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--*/
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{
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PULONG DispatchCode;
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ULONG IdtIndex;
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ULONG IntNumber;
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PKINTERRUPT InterruptObject;
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UCHAR PCIVector;
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//
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// Read in the 1st interrupt register.
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//
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PCIVector = READ_PORT_UCHAR((PUCHAR)INTERRUPT_MASK0_QVA) & IntMask0;
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//
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// Did ISA interrupt occur?
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//
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if (PCIVector & 0x10) {
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//
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// ISA interrupt. Call HalpEB164SioDispatch.
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//
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return (HalpEB164SioDispatch( Interrupt, NULL, TrapFrame ) );
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}
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//
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// Which PCI interrupt occurred?
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//
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IdtIndex = PCI_MAX_INTERRUPT + 1;
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if (PCIVector) {
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for (IntNumber = 0; IntNumber < 8; IntNumber++) {
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if (PCIVector & 0x01) {
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IdtIndex = IntNumber;
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break;
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} else {
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PCIVector = PCIVector >> 1;
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}
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}
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} else {
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PCIVector = READ_PORT_UCHAR((PUCHAR)INTERRUPT_MASK1_QVA) & IntMask1;
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if (PCIVector) {
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for (IntNumber = 0; IntNumber < 8; IntNumber++) {
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if (PCIVector & 0x01) {
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IdtIndex = IntNumber + 8;
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break;
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} else {
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PCIVector = PCIVector >> 1;
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}
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}
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} else {
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PCIVector = READ_PORT_UCHAR((PUCHAR)INTERRUPT_MASK2_QVA) & IntMask2;
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for (IntNumber = 0; IntNumber < 8; IntNumber++) {
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if (PCIVector & 0x01) {
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IdtIndex = IntNumber + 16;
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break;
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} else {
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PCIVector = PCIVector >> 1;
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}
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}
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}
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}
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//
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// If no PCI interrupt is enabled and asserted then this is a passive
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// release.
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//
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if( IdtIndex > PCI_MAX_INTERRUPT ){
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#if HALDBG
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DbgPrint( "HalpDeviceDispatch: PCI Passive Release.\n" );
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#endif //HALDBG
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return FALSE;
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}
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IdtIndex += PCI_VECTORS;
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DispatchCode = (PULONG)PCR->InterruptRoutine[IdtIndex];
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InterruptObject = CONTAINING_RECORD( DispatchCode,
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KINTERRUPT,
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DispatchCode );
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return( ((PSECOND_LEVEL_DISPATCH)InterruptObject->DispatchAddress)(
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InterruptObject,
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InterruptObject->ServiceContext,
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TrapFrame) );
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}
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