342 lines
8.6 KiB
C++
342 lines
8.6 KiB
C++
;/*
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;++
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;
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;Copyright (c) 1992 Sequent Computer Systems, Inc.
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;
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;Module Name:
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;
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; w3hal.h
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;
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;Abstract:
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;
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; This header file contains definitions for the WinServer 3000.
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;
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;Author:
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;
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; Phil Hochstetler (phil@sequent.com)
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;
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;Environment:
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;
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; Kernel mode only.
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;
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;Revision History:
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;
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;--
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if 0 ; Begin C only code */
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//
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// Interrupt vector definitions for C
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//
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#define APIC_APC_VECTOR 0x30
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#define APIC_DPC_VECTOR 0x40
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#define APIC_IRQ16_VECTOR 0x60
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#define APIC_IRQ17_VECTOR 0x61
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#define APIC_IRQ18_VECTOR 0x62
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#define APIC_IRQ19_VECTOR 0x63
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#define APIC_IRQ20_VECTOR 0x64
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#define APIC_IRQ21_VECTOR 0x65
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#define APIC_IRQ22_VECTOR 0x66
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#define APIC_IRQ23_VECTOR 0x67
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#define APIC_IRQ8_VECTOR 0x70
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#define APIC_IRQ9_VECTOR 0x71
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#define APIC_IRQ10_VECTOR 0x72
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#define APIC_IRQ11_VECTOR 0x73
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#define APIC_IRQ12_VECTOR 0x74
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#define APIC_IRQ13_VECTOR 0x75
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#define APIC_IRQ14_VECTOR 0x76
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#define APIC_IRQ15_VECTOR 0x77
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#define APIC_IRQ0_VECTOR 0x80
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#define APIC_IRQ1_VECTOR 0x81
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#define APIC_IRQ2_VECTOR 0x82
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#define APIC_IRQ3_VECTOR 0x83
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#define APIC_IRQ4_VECTOR 0x84
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#define APIC_IRQ5_VECTOR 0x85
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#define APIC_IRQ6_VECTOR 0x86
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#define APIC_IRQ7_VECTOR 0x87
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#define APIC_RTC_VECTOR 0x70
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#define APIC_MOUSE_VECTOR 0x74
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#define APIC_DMA_VECTOR 0x75
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#define APIC_IDE_VECTOR 0x76
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#define APIC_KBD_VECTOR 0x81
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#define APIC_FLOPPY_VECTOR 0x86
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#define APIC_PROFILE_VECTOR 0x90
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#define APIC_CLOCK_VECTOR 0xA0
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#define APIC_IPI_VECTOR 0xB0
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#define APIC_POWERFAIL_VECTOR 0xC0
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#define EISA_CLOCK_VECTOR 0xD0
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#define EISA_KBD_VECTOR 0xD1
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#define EISA_IRQ2_VECTOR 0xD2
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#define EISA_FLOPPY_VECTOR 0xD6
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#define EISA_PIC1_SPURIOUS_VECTOR 0xD7
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#define EISA_RTC_VECTOR 0xD8
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#define EISA_MOUSE_VECTOR 0xDC
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#define EISA_DMA_VECTOR 0xDD
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#define EISA_IDE_VECTOR 0xDE
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#define EISA_PIC2_SPURIOUS_VECTOR 0xDF
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#define APIC_SPURIOUS_VECTOR 0xE0
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#define APIC_SYSINT_VECTOR 0xE1
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#define APIC_HIGH_VECTOR 0xF0
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#define APIC_STALL_VECTOR 0xF8
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#define PIC0_BASE_VECTOR EISA_CLOCK_VECTOR
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#define PIC1_BASE_VECTOR EISA_RTC_VECTOR
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#define EISA_SHIFT 12 // EISA slot starts at this offset
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#define EISA_MASK 0xfff // Low bits of EISA slot address
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#define POSTREGISTERPORT 0x80 // BIOS post register
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#define OCW2_SPECIFIC_EOI 0x60
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#define OCW2_NON_SPECIFIC_EOI 0x20
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#define PIC1_PORT0 0x20
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#define PIC1_PORT1 0x21
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#define PIC2_PORT0 0xA0
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#define PIC2_PORT1 0xA1
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#define PIC3_PORT0 0xCC0
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#define PIC3_PORT1 0xCC1
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#define EISA_2_MPIC_POLARITY_REG 0x0C0E
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#define ELCR_MASK 0xDEF8
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#define PIC1_ELCR_PORT 0x04D0
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#define PIC2_ELCR_PORT 0x04D1
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#define DESTINATION_ALL_CPUS 0xff
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#define DESTINATION_CPU_0 0x01
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#define FCR 0x0C84
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#define WarmResetVector 0x467
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#define FCR_RESET_MASK 0x0080
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#define IOMPIC_RT_MASK 0x10000
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#define FIRST_SYSTEM_SLOT 9
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#define LAST_SYSTEM_SLOT 15
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#define SLOT_ID_REG 0x0C80
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#define SLOT_ID_BOARDTYPE 0x00F00000
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#define SLOT_ID_TYPECPU 0x00100000
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#define IOUNIT_APIC_ID 7
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#define IOUNIT2_APIC_ID 8
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#define D_INT032 8E00h
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#define PeriodInUsec 200
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#define IRQL_APIC_KBD 25
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#define IRQL_APIC_FLOPPY 21
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#define IRQL_APIC_RTC 19
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#define IRQL_APIC_DMA 14
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#define IRQL_APIC_IDE 13
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#define IRQL_APIC_MOUSE 15
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//
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// Hal private data structures (max 64 bytes in length)
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//
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typedef struct _WS3_HAL_PRIVATE {
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UCHAR PcrNumber; // Logical Processor Number
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UCHAR ProcLightState; // State of Processor light (1=on,0=off)
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UCHAR ProcIrql; // Current IRQL
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UCHAR ProcPad1; // Reserved (for padding)
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USHORT ProcSlotAddr; // (slot << EISA_SHIFT)
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USHORT ProcPad2; // Reserved (for padding)
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} WS3_HAL_PRIVATE, *PWS3_HAL_PRIVATE;
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/*
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endif
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; Start of Assembly only code
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;
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; Interrupt vector definitions for ASM
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;
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APIC_APC_VECTOR equ 030h
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APIC_DPC_VECTOR equ 040h
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APIC_IRQ16_VECTOR equ 060h
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APIC_IRQ17_VECTOR equ 061h
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APIC_IRQ18_VECTOR equ 062h
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APIC_IRQ19_VECTOR equ 063h
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APIC_IRQ20_VECTOR equ 064h
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APIC_IRQ21_VECTOR equ 065h
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APIC_IRQ22_VECTOR equ 066h
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APIC_IRQ23_VECTOR equ 067h
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APIC_IRQ8_VECTOR equ 070h
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APIC_IRQ9_VECTOR equ 071h
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APIC_IRQ10_VECTOR equ 072h
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APIC_IRQ11_VECTOR equ 073h
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APIC_IRQ12_VECTOR equ 074h
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APIC_IRQ13_VECTOR equ 075h
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APIC_IRQ14_VECTOR equ 076h
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APIC_IRQ15_VECTOR equ 077h
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APIC_IRQ0_VECTOR equ 080h
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APIC_IRQ1_VECTOR equ 081h
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APIC_IRQ2_VECTOR equ 082h
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APIC_IRQ3_VECTOR equ 083h
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APIC_IRQ4_VECTOR equ 084h
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APIC_IRQ5_VECTOR equ 085h
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APIC_IRQ6_VECTOR equ 086h
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APIC_IRQ7_VECTOR equ 087h
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APIC_RTC_VECTOR equ 070h
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APIC_MOUSE_VECTOR equ 074h
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APIC_DMA_VECTOR equ 075h
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APIC_IDE_VECTOR equ 076h
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APIC_KBD_VECTOR equ 081h
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APIC_FLOPPY_VECTOR equ 086h
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APIC_PROFILE_VECTOR equ 090h
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APIC_CLOCK_VECTOR equ 0A0h
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APIC_IPI_VECTOR equ 0B0h
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APIC_POWERFAIL_VECTOR equ 0C0h
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EISA_CLOCK_VECTOR equ 0D0h
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EISA_KBD_VECTOR equ 0D1h
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EISA_IRQ2_VECTOR equ 0D2h
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EISA_FLOPPY_VECTOR equ 0D6h
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EISA_PIC1_SPURIOUS_VECTOR equ 0D7h
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EISA_RTC_VECTOR equ 0D8h
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EISA_MOUSE_VECTOR equ 0DCh
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EISA_DMA_VECTOR equ 0DDh
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EISA_IDE_VECTOR equ 0DEh
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EISA_PIC2_SPURIOUS_VECTOR equ 0DFh
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APIC_SPURIOUS_VECTOR equ 0E0h
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APIC_SYSINT_VECTOR equ 0E1h
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APIC_HIGH_VECTOR equ 0F0h
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APIC_STALL_VECTOR equ 0F8h
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PIC0_BASE_VECTOR equ EISA_CLOCK_VECTOR
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PIC1_BASE_VECTOR equ EISA_RTC_VECTOR
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EISA_SHIFT equ 12 ; EISA slot starts at this offset
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EISA_MASK equ 0fffh ; Low bits of EISA slot address
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PostRegisterPort equ 080h ; BIOS post register
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OCW2_SPECIFIC_EOI equ 060h
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OCW2_NON_SPECIFIC_EOI equ 020h
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PIC1_PORT0 equ 020h
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PIC1_PORT1 equ 021h
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PIC2_PORT0 equ 0A0h
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PIC2_PORT1 equ 0A1h
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PIC3_PORT0 equ 0CC0h
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PIC3_PORT1 equ 0CC1h
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EISA_2_MPIC_POLARITY_REG equ 0C0Eh
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ELCR_MASK equ 0DEF8h
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PIC1_ELCR_PORT equ 04D0h
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PIC2_ELCR_PORT equ 04D1h
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DESTINATION_ALL_CPUS equ 0ffh
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DESTINATION_CPU_0 equ 1
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FCR equ 0C84h
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WarmResetVector equ 0467h
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FCR_RESET_MASK equ 0080h
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IOMPIC_RT_MASK equ 10000h
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FIRST_SYSTEM_SLOT equ 9
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LAST_SYSTEM_SLOT equ 15
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SLOT_ID_REG equ 0C80h
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SLOT_ID_BOARDTYPE equ 00F00000h
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SLOT_ID_TYPECPU equ 00100000h
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IOUNIT_APIC_ID equ 7
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IOUNIT2_APIC_ID equ 8
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D_INT032 equ 8E00h ; access word for 386 ring 0 interrupt gate
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PeriodInUsec equ 200
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IRQL_APIC_KBD equ 25
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IRQL_APIC_FLOPPY equ 21
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IRQL_APIC_RTC equ 19
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IRQL_APIC_DMA equ 14
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IRQL_APIC_IDE equ 13
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IRQL_APIC_MOUSE equ 15
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;
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; The kernel leaves some space (64 bytes) of the PCR for the HAL to use
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; as it needs. Currently this space is used for some efficiency in
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; some of the MP specific code and is highly implementation-dependent.
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; Must match the preceeding C structure.
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PcrE struc
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PcrNumber db 0 ; Processor's number
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ProcLightState db 0 ; State of Processor light
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ProcIrql db 0 ; Current IRQL
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ProcPad1 db 0 ; Reserved (for padding)
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ProcSlotAddr dw 0 ; Slot (9-15) << 12
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ProcPad2 dw 0 ; Reserved (for padding)
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PcrE ends
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CR equ 0dh
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LF equ 0ah
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IoDelay macro
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push eax
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in al, 020h
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pop eax
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endm
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SET_8259_MASK macro
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out PIC1_PORT1, al ; set master 8259 mask
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shr eax, 8 ; shift slave 8259 mask to al
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out PIC2_PORT1, al ; set slave 8259 mask
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endm
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PIC1DELAY macro
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in al, PIC1_PORT1
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endm
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PIC2DELAY macro
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in al, PIC2_PORT1
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endm
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DISABLE_INTERRUPTS_AT_CPU macro
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pushfd ; save interrupt mode
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cli ; disable interrupt
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endm
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RESTORE_INTERRUPTS_AT_CPU macro
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popfd ; restore original interrupt mode
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endm
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;++
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;
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; SOFT_INTERRUPT_EXIT
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;
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; Macro Description:
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;
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; This macro is executed on return from the soft interrupt
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; service routine. Its function is to restore privileged processor
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; state, and continue thread execution.
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;
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; Arguments:
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;
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; (TOS) = previous irql
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; (TOS+4 ...) = machine_state frame
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;
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;--
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SOFT_INTERRUPT_EXIT macro
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EXTRNP _KeLowerIrql,1
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cli
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call _KeLowerIrql@4 ; restore irql
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SPURIOUS_INTERRUPT_EXIT ; exit interrupt without EOI
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endm
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; Macro for programming IDT entries directly
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IDTEntry macro Vector, Handler
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sub esp, 8 ; allocate temp stack space
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sidt fword ptr [esp] ; IDT base + limit
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mov edx, [esp+2] ; IDT linear base address
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mov ecx, Vector ; get Vector
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mov eax, offset FLAT:Handler ; Get Handler
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mov word ptr [edx+8*ecx], ax ; Lower half of handler addr
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mov word ptr [edx+8*ecx+2], KGDT_R0_CODE ; set up selector
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mov word ptr [edx+8*ecx+4], D_INT032 ; 386 interrupt gate
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shr eax, 16 ; (ax)=higher half of handler addr
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mov word ptr [edx+8*ecx+6], ax
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add esp, 8 ; deallocate temp stack space
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endm
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; End of Assembly only code
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;*/
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