628 lines
28 KiB
C
628 lines
28 KiB
C
/************************************************************************/
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/* */
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/* SETUP_CX.H */
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/* */
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/* Aug 27 1993 (c) 1993, ATI Technologies Incorporated. */
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/************************************************************************/
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/********************** PolyTron RCS Utilities
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$Revision: 1.17 $
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$Date: 15 Apr 1996 13:52:36 $
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$Author: RWolff $
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$Log: S:/source/wnt/ms11/miniport/archive/setup_cx.h_v $
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*
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* Rev 1.17 15 Apr 1996 13:52:36 RWolff
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* Fallback to claiming 32k of BIOS if we can't get the full 64k, to avoid
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* conflict with Adaptec 154x adapters with their BIOS segment set to
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* 0xC800:0000 or 0xCC00:0000
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*
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* Rev 1.16 10 Apr 1996 17:04:48 RWolff
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* Now claims our BIOS segment in order to allow access to our hardware
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* capability table in the BIOS on P6 Alder machines.
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*
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* Rev 1.15 01 Mar 1996 12:12:34 RWolff
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* VGA Graphics Index and Graphics Data are now handled as separate
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* registers rather than as offsets into the block of VGA registers.
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*
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* Rev 1.14 29 Jan 1996 17:03:12 RWolff
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* Replaced list of device IDs for Mach 64 cards with list of device IDs
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* for non-Mach 64 cards.
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*
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* Rev 1.13 23 Jan 1996 17:53:04 RWolff
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* Added GT to list of Mach 64 cards capable of supporting block I/O.
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*
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* Rev 1.12 23 Jan 1996 11:51:24 RWolff
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* Removed conditionally-compiled code to use VideoPortGetAccessRanges()
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* to find block I/O cards, since this function remaps the I/O base
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* address and this is incompatible with the use of INT 10.
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*
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* Rev 1.11 12 Jan 1996 11:19:12 RWolff
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* ASIC type definitions used in workaround for VideoPortGetBaseAddress()
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* not working are now conditionally compiled.
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*
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* Rev 1.10 23 Nov 1995 11:35:12 RWolff
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* Temporary fixes to allow detection of block-relocatable GX-F2s until
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* Microsoft fixes VideoPortGetAccessRanges().
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*
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* Rev 1.9 24 Aug 1995 15:40:46 RWolff
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* Changed detection of block I/O cards to match Microsoft's
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* standard for plug-and-play.
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*
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* Rev 1.8 27 Feb 1995 17:47:32 RWOLFF
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* Added prototype for new routine IsPackedIO_cx().
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*
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* Rev 1.7 24 Feb 1995 12:28:04 RWOLFF
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* Added support for relocatable I/O
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*
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* Rev 1.6 04 Jan 1995 13:23:36 RWOLFF
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* Locked out two memory-mapped registers that were causing problems
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* on some platforms.
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*
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* Rev 1.5 23 Dec 1994 10:48:10 ASHANMUG
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* ALPHA/Chrontel-DAC
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*
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* Rev 1.4 18 Nov 1994 11:55:02 RWOLFF
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* Prototype for new routine, renamed register to CLOCK_CNTL to match latest
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* documentation, restricted this register to I/O operation only, since it
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* isn't reliable in memory mapped form.
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*
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* Rev 1.3 31 Aug 1994 16:31:20 RWOLFF
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* No longer claims VGA_SLEEP register, which we didn't access and which
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* conflicted with DigiBoard.
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*
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* Rev 1.3 31 Aug 1994 16:30:36 RWOLFF
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* No longer claims VGA_SLEEP register, which we didn't access and which
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* conflicted with DigiBoard.
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*
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* Rev 1.2 20 Jul 1994 12:58:38 RWOLFF
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* Added support for multiple I/O base addresses for accelerator registers.
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*
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* Rev 1.1 30 Jun 1994 18:16:08 RWOLFF
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* Added prototype and definitions for IsApertureConflict_cx() (moved from
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* QUERY_CX.C).
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*
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* Rev 1.0 31 Jan 1994 11:48:44 RWOLFF
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* Initial revision.
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*
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* Rev 1.0 05 Nov 1993 13:37:06 RWOLFF
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* Initial revision.
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End of PolyTron RCS section *****************/
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#ifdef DOC
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SETUP_CX.H - Header file for SETUP_CX.C
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#endif
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/*
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* Prototypes for functions supplied by SETUP_CX.C
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*/
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extern VP_STATUS CompatIORangesUsable_cx(INTERFACE_TYPE SystemBus);
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extern VP_STATUS CompatMMRangesUsable_cx(void);
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extern int WaitForIdle_cx(void);
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extern void CheckFIFOSpace_cx(WORD SpaceNeeded);
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extern BOOL IsApertureConflict_cx(struct query_structure *QueryPtr);
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extern USHORT GetIOBase_cx(void);
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extern BOOL IsPackedIO_cx(void);
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/*
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* Definitions and global variables used in searching for
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* block I/O relocatable cards.
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*/
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#define ATI_MAX_BLOCK_CARDS 16 /* AH values A0 through AF for INT 10 */
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extern UCHAR LookForAnotherCard;
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/*
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* Definitions used internally by SETUP_CX.C
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*/
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#ifdef INCLUDE_SETUP_CX
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/*
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* Avoid runtime bugs due to overflowing the address range arrays
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* in the HW_DEVICE_EXTENSION structure.
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*
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* If more address ranges are added without increasing
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* NUM_DRIVER_ACCESS_RANGES, we will get a compile-time error because
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* too many entries in DriverIORange[] will be initialized. If
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* NUM_DRIVER_ACCESS_RANGES is increased beyond the size of
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* the arrays in the HW_DEVICE_EXTENSION structure, the "#if"
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* statement will generate a compile-time error.
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*
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* We can't use an implicit size on DriverIORange[] and define
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* NUM_DRIVER_ACCESS_RANGES as sizeof(DriverIORange)/sizeof(VIDEO_ACCESS_RANGE)
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* because the expression in a #if statement can't use the
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* sizeof() operator.
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*/
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#define NUM_DRIVER_ACCESS_RANGES 107
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/*
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* Indicate whether the specified address range is in I/O space or
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* memory mapped space. These values are intended to make it easier
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* to read the Driver??Range[] structures.
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*/
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#define ISinIO TRUE
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#define ISinMEMORY FALSE
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/*
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* Indicate that this register is not available in the current (either
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* I/O or memory mapped) form.
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*/
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#define DONT_USE -1
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/*
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* Definitions and arrays to allow accelerator registers with variable
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* bases to be built in DriverIORange_cx[]. Definitions mark the first
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* accelerator register in the array (VGA registers have a fixed base),
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* and the number of registers to loop through while building the
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* accelerator registers. The arrays contain the variable portions
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* of the registers in the order they appear in DriverIORange_cx[],
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* and the base addresses.
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*/
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#define FIRST_REG_TO_BUILD 8
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#define NUM_REGS_TO_BUILD 30
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USHORT VariableRegisterBases[NUM_BASE_ADDRESSES] = {
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M64_STD_BASE_ADDR,
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M64_ALT_BASE_ADDR_1,
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M64_ALT_BASE_ADDR_2
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};
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USHORT VariableRegisterOffsets[NUM_REGS_TO_BUILD] = {
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IO_CRTC_H_TOTAL_DISP,
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IO_CRTC_H_SYNC_STRT_WID,
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IO_CRTC_V_TOTAL_DISP,
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IO_CRTC_V_SYNC_STRT_WID,
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IO_CRTC_CRNT_VLINE,
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IO_CRTC_OFF_PITCH,
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IO_CRTC_INT_CNTL,
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IO_CRTC_GEN_CNTL,
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IO_OVR_CLR,
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IO_OVR_WID_LEFT_RIGHT,
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IO_OVR_WID_TOP_BOTTOM,
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IO_CUR_CLR0,
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IO_CUR_CLR1,
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IO_CUR_OFFSET,
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IO_CUR_HORZ_VERT_POSN,
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IO_CUR_HORZ_VERT_OFF,
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IO_SCRATCH_REG0,
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IO_SCRATCH_REG1,
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IO_CLOCK_CNTL,
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IO_BUS_CNTL,
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IO_MEM_CNTL,
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IO_MEM_VGA_WP_SEL,
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IO_MEM_VGA_RP_SEL,
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IO_DAC_REGS,
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IO_DAC_CNTL,
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IO_GEN_TEST_CNTL,
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IO_CONFIG_CNTL,
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IO_CONFIG_CHIP_ID,
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IO_CONFIG_STAT0,
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IO_CONFIG_STAT1
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};
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/*
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* For cards with relocatable I/O, the I/O registers
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* are in a dense block, with each register at the
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* same DWORD index into the block as it is into the
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* block of memory mapped registers.
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*/
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USHORT RelocatableRegisterOffsets[NUM_REGS_TO_BUILD] = {
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MM_CRTC_H_TOTAL_DISP,
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MM_CRTC_H_SYNC_STRT_WID,
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MM_CRTC_V_TOTAL_DISP,
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MM_CRTC_V_SYNC_STRT_WID,
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MM_CRTC_CRNT_VLINE,
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MM_CRTC_OFF_PITCH,
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MM_CRTC_INT_CNTL,
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MM_CRTC_GEN_CNTL,
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MM_OVR_CLR,
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MM_OVR_WID_LEFT_RIGHT,
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MM_OVR_WID_TOP_BOTTOM,
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MM_CUR_CLR0,
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MM_CUR_CLR1,
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MM_CUR_OFFSET,
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MM_CUR_HORZ_VERT_POSN,
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MM_CUR_HORZ_VERT_OFF,
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MM_SCRATCH_REG0,
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MM_SCRATCH_REG1,
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MM_CLOCK_CNTL,
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MM_BUS_CNTL,
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MM_MEM_CNTL,
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MM_MEM_VGA_WP_SEL,
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MM_MEM_VGA_RP_SEL,
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MM_DAC_REGS,
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MM_DAC_CNTL,
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MM_GEN_TEST_CNTL,
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MM_CONFIG_CNTL,
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MM_CONFIG_CHIP_ID,
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MM_CONFIG_STAT0,
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MM_CONFIG_STAT1
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};
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/*
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* Number of registers which exist in I/O mapped form. When we claim the
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* VGA and linear apertures, we will temporarily park their address
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* ranges immediately after the I/O mapped registers.
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*/
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#define NUM_IO_REGISTERS 38
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#define VGA_APERTURE_ENTRY NUM_IO_REGISTERS
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#define LFB_ENTRY 1 /* Offset into DriverApertureRange_cx[] */
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/*
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* Size of BIOS block to claim. On some machines, we must claim the
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* region occupied by our video BIOS in order to be able to detect
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* a Mach 64, but if we claim the full 64k when we have only a 32k
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* BIOS (Mach 64 cards are available with both 32k and 64k BIOSes)
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* and the driver for a SCSI card with its BIOS segment in the second
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* 32k claims its BIOS segment, we will be rejected.
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*/
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#define CLAIM_64k_BIOS 0
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#define CLAIM_32k_BIOS 1
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#define CLAIM_APERTURE_ONLY 2
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#define NUM_CLAIM_SIZES 3
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ULONG VgaResourceSize[NUM_CLAIM_SIZES] =
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{
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0x30000, /* Text and graphics screens, and 64k BIOS area */
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0x28000, /* Text and graphics screens, and 32k BIOS area */
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0x20000 /* Text and graphics screens only */
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};
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/*
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* Memory ranges we need to claim. The first is the VGA aperture, which
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* is always at a fixed location. The second is the linear framebuffer,
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* which we don't yet know where or how big it is. This information
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* will be filled in when we get it.
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*
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* In the VGA aperture, we must claim the graphics screen (A0000-AFFFF)
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* since this is used as the paged aperture, the text screens (B0000-B7FFF
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* and B8000-BFFFF) since the memory-mapped registers are here when we
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* use the paged aperture, and we use off-screen memory here to store our
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* query information, and the video BIOS (C0000-CFFFF) since we must
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* retrieve some information (signature string, table of maximum pixel
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* clock frequency for each resolution/refresh pair) from this region.
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* Since these areas are contiguous, and we do not need exclusive access
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* to any of them, claim them as a single block.
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*/
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VIDEO_ACCESS_RANGE DriverApertureRange_cx[2] = {
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{0xA0000, 0, 0, ISinMEMORY, TRUE, TRUE},
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{0, 0, 0, ISinMEMORY, TRUE, FALSE}
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};
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/*
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* Structure list is address, 0 or "not available" flag, length,
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* inIOspace, visible, shareable. This order matches the enumeration
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* in AMACHCX.H.
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*
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* VGAWonder-compatible I/O ranges come first in no particular order,
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* followed by the coprocessor registers in increasing order of I/O and
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* memory mapped addresses. This order was chosen because all the VGA
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* addresses are I/O mapped, as are the non-GUI coprocessor registers,
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* while the GUI coprocessor registers are only available as memory mapped.
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*
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* Since all the I/O mapped registers are in a block at the beginning of
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* the structure, we can feed VideoPortVerifyAccessRanges() a truncated
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* version of the structure (all I/O mapped registers, but none that are
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* only available as memory-mapped) to claim the I/O address space we need.
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*
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* The I/O addresses shown for accelerator registers are for reference only,
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* to show which register goes in which location. The actual register
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* value will be built "on the fly", since these registers have variable
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* base addresses.
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*/
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VIDEO_ACCESS_RANGE DriverIORange_cx[NUM_DRIVER_ACCESS_RANGES] = {
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{IO_VGA_BASE_IO_PORT , 0 , IO_VGA_START_BREAK_PORT - IO_VGA_BASE_IO_PORT + 1, ISinIO, TRUE, TRUE},
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{IO_VGA_END_BREAK_PORT , 0 , IO_VGA_MAX_IO_PORT - IO_VGA_END_BREAK_PORT + 1, ISinIO, TRUE, TRUE},
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{IO_VGA_SEQ_IND , 0 , 2, ISinIO, TRUE , TRUE},
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{IO_VGA_SEQ_DATA , 0 , 1, ISinIO, TRUE , TRUE},
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{IO_VGA_GRAX_IND , 0 , 2, ISinIO, TRUE , TRUE},
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{IO_VGA_GRAX_DATA , 0 , 1, ISinIO, TRUE , TRUE},
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{IO_reg1CE , 0 , 2, ISinIO, TRUE , TRUE},
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{IO_reg1CF , 0 , 1, ISinIO, TRUE , TRUE},
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{IO_CRTC_H_TOTAL_DISP , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CRTC_H_SYNC_STRT_WID , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CRTC_V_TOTAL_DISP , 0 , 4, ISinIO, TRUE , FALSE}, // 10
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{IO_CRTC_V_SYNC_STRT_WID , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CRTC_CRNT_VLINE , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CRTC_OFF_PITCH , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CRTC_INT_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CRTC_GEN_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_OVR_CLR , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_OVR_WID_LEFT_RIGHT , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_OVR_WID_TOP_BOTTOM , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CUR_CLR0 , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CUR_CLR1 , 0 , 4, ISinIO, TRUE , FALSE}, // 20
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{IO_CUR_OFFSET , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CUR_HORZ_VERT_POSN , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CUR_HORZ_VERT_OFF , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_SCRATCH_REG0 , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_SCRATCH_REG1 , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CLOCK_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_BUS_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_MEM_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_MEM_VGA_WP_SEL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_MEM_VGA_RP_SEL , 0 , 4, ISinIO, TRUE , FALSE}, // 30
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{IO_DAC_REGS , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_DAC_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_GEN_TEST_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CONFIG_CNTL , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CONFIG_CHIP_ID , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CONFIG_STAT0 , 0 , 4, ISinIO, TRUE , FALSE},
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{IO_CONFIG_STAT1 , 0 , 4, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 40
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 50
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 60
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 70
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 80
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
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{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 90
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}, // 100
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE},
|
|
{FALSE , DONT_USE , 0, ISinIO, TRUE , FALSE}
|
|
};
|
|
|
|
#if NUM_DRIVER_ACCESS_RANGES > NUM_ADDRESS_RANGES_ALLOWED
|
|
Insufficient address ranges for 68800CX-compatible graphics cards.
|
|
#endif
|
|
|
|
#define DONT_USE -1 /* Shows that this register is not memory mapped */
|
|
|
|
/*
|
|
* Structure list is address, 0 or "not available" flag, length,
|
|
* inIOspace, visible, shareable. This order matches the enumeration
|
|
* in AMACHCX.H.
|
|
*
|
|
* The registers in this structure are in the same order as in
|
|
* DriverIORange_cx[], except here we are defining memory mapped
|
|
* registers instead of I/O mapped registers.
|
|
*
|
|
* Some registers are grouped to allow block writes larger than
|
|
* the 32 bit register size. To allow this, let Windows NT think
|
|
* that the size of this register is actually the total size (in
|
|
* bytes) of all remaining registers in the group.
|
|
*/
|
|
VIDEO_ACCESS_RANGE DriverMMRange_cx[NUM_DRIVER_ACCESS_RANGES] = {
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CRTC_H_TOTAL_DISP , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CRTC_H_SYNC_STRT_WID , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_CRTC_V_TOTAL_DISP , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 10
|
|
{MM_CRTC_V_SYNC_STRT_WID , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CRTC_CRNT_VLINE , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CRTC_OFF_PITCH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CRTC_INT_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_CRTC_GEN_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_OVR_CLR , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_OVR_WID_LEFT_RIGHT , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_OVR_WID_TOP_BOTTOM , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CUR_CLR0 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_CUR_CLR1 , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 20
|
|
{MM_CUR_OFFSET , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CUR_HORZ_VERT_POSN , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CUR_HORZ_VERT_OFF , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SCRATCH_REG0 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_SCRATCH_REG1 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{MM_BUS_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_MEM_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_MEM_VGA_WP_SEL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_MEM_VGA_RP_SEL , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 30
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
{MM_GEN_TEST_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{FALSE , DONT_USE , 0, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_CONFIG_CHIP_ID , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CONFIG_STAT0 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CONFIG_STAT1 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_OFF_PITCH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_X , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_DST_Y , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 40
|
|
{MM_DST_Y_X , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_WIDTH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_HEIGHT , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_HEIGHT_WIDTH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_DST_X_WIDTH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_BRES_LNTH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_BRES_ERR , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_BRES_INC , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DST_BRES_DEC , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_DST_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 50
|
|
{MM_SRC_OFF_PITCH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_X , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_Y , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_Y_X , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_SRC_WIDTH1 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_HEIGHT1 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_HEIGHT1_WIDTH1 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_X_START , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_Y_START , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_SRC_Y_X_START , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 60
|
|
{MM_SRC_WIDTH2 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_HEIGHT2 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_HEIGHT2_WIDTH2 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SRC_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_HOST_DATA0 , 0 ,64, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA1 , 0 ,60, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA2 , 0 ,56, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA3 , 0 ,52, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA4 , 0 ,48, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_HOST_DATA5 , 0 ,44, ISinMEMORY, TRUE, FALSE}, // 70
|
|
{MM_HOST_DATA6 , 0 ,40, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA7 , 0 ,36, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA8 , 0 ,32, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA9 , 0 ,28, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_HOST_DATA10 , 0 ,24, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA11 , 0 ,20, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA12 , 0 ,16, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA13 , 0 ,12, ISinMEMORY, TRUE, FALSE},
|
|
{MM_HOST_DATA14 , 0 , 8, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_HOST_DATA15 , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 80
|
|
{MM_HOST_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_PAT_REG0 , 0 , 8, ISinMEMORY, TRUE, FALSE},
|
|
{MM_PAT_REG1 , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_PAT_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_SC_LEFT , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SC_RIGHT , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SC_LEFT_RIGHT , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SC_TOP , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_SC_BOTTOM , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_SC_TOP_BOTTOM , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 90
|
|
{MM_DP_BKGD_CLR , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DP_FRGD_CLR , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DP_WRITE_MASK , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DP_CHAIN_MASK , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_DP_PIX_WIDTH , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DP_MIX , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_DP_SRC , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CLR_CMP_CLR , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CLR_CMP_MSK , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_CLR_CMP_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE}, // 100
|
|
{MM_FIFO_STAT , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CONTEXT_MASK , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CONTEXT_SAVE_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_CONTEXT_LOAD_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
|
|
{MM_GUI_TRAJ_CNTL , 0 , 4, ISinMEMORY, TRUE, FALSE},
|
|
{MM_GUI_STAT , 0 , 4, ISinMEMORY, TRUE, FALSE}
|
|
};
|
|
|
|
|
|
/*
|
|
* Device IDs for PCI configuration registers. Only non-Mach 64
|
|
* IDs are listed here, since future IDs will (for the forseeable
|
|
* future) almost certainly be Mach 64 cards, so we can assume
|
|
* that any ID we haven't rejected is a Mach 64, which we should
|
|
* accept.
|
|
*
|
|
* Currently, the Mach 32 AX is our only PCI card which is not
|
|
* a Mach 64.
|
|
*/
|
|
#define ATI_DEVID_M32AX 0x4158
|
|
|
|
|
|
#endif /* defined INCLUDE_SETUP_CX */
|
|
|