375 lines
18 KiB
C
375 lines
18 KiB
C
/************************************************************************/
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/* */
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/* SETUP_M.H */
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/* */
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/* Aug 27 1993 (c) 1993, ATI Technologies Incorporated. */
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/************************************************************************/
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/********************** PolyTron RCS Utilities
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$Revision: 1.5 $
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$Date: 18 May 1995 14:14:34 $
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$Author: RWOLFF $
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$Log: S:/source/wnt/ms11/miniport/vcs/setup_m.h $
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*
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* Rev 1.5 18 May 1995 14:14:34 RWOLFF
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* No longer uses the memory-mapped form of CLOCK_SEL (sometimes the
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* value written wouldn't "take" even though a readback showed the
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* correct value).
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*
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* Rev 1.4 23 Dec 1994 10:48:16 ASHANMUG
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* ALPHA/Chrontel-DAC
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*
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* Rev 1.3 07 Jul 1994 14:00:48 RWOLFF
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* Andre Vachon's fix: re-sized DriverMMRange_m[] from NUM_DRIVER_ACCESS_RANGES
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* entries to NUM_IO_ACCESS_RANGES entries because this array doesn't need
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* a slot for the framebuffer.
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*
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* Rev 1.2 30 Jun 1994 18:22:38 RWOLFF
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* Added prototypes for IsApertureConflict_m() and IsVGAConflict_m(), and
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* definitions used by these routines.
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*
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* Rev 1.1 20 May 1994 14:04:18 RWOLFF
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* Ajith's change: removed unused register SRC_CMP_COLOR from lists to be mapped
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*
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* Rev 1.0 31 Jan 1994 11:49:36 RWOLFF
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* Initial revision.
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*
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* Rev 1.5 14 Jan 1994 15:27:02 RWOLFF
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* Added prototype for MemoryMappedEnabled_m()
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*
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* Rev 1.4 15 Dec 1993 15:32:40 RWOLFF
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* No longer claims EISA configuration registers and placeholder for
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* the linear framebuffer.
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*
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* Rev 1.3 05 Nov 1993 13:32:50 RWOLFF
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* Added prototype of function to unmap I/O address ranges.
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*
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* Rev 1.1 08 Oct 1993 11:16:46 RWOLFF
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* Added I/O vs. Memory Mapped definitions formerly in ATIMP.H.
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*
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* Rev 1.0 03 Sep 1993 14:29:26 RWOLFF
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* Initial revision.
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End of PolyTron RCS section *****************/
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#ifdef DOC
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SETUP_M.H - Header file for SETUP_M.C
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#endif
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/*
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* Prototypes for functions supplied by SETUP_M.C
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*/
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extern VP_STATUS CompatIORangesUsable_m(void);
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extern void CompatMMRangesUsable_m(void);
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extern void UnmapIORanges_m(void);
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extern BOOL MemoryMappedEnabled_m(void);
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extern int WaitForIdle_m(void);
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extern void CheckFIFOSpace_m(WORD SpaceNeeded);
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extern BOOL IsApertureConflict_m(struct query_structure *QueryPtr);
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extern BOOL IsVGAConflict_m(void);
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/*
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* Definitions used internally by SETUP_M.C
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*/
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#ifdef INCLUDE_SETUP_M
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/*
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* Avoid runtime bugs due to overflowing the address range arrays
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* in the HW_DEVICE_EXTENSION structure.
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*
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* If more address ranges are added without increasing
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* NUM_DRIVER_ACCESS_RANGES, we will get a compile-time error because
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* too many entries in DriverIORange[] will be initialized. If
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* NUM_DRIVER_ACCESS_RANGES is increased beyond the size of
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* the arrays in the HW_DEVICE_EXTENSION structure, the "#if"
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* statement will generate a compile-time error.
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*
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* We can't use an implicit size on DriverIORange[] and define
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* NUM_DRIVER_ACCESS_RANGES as sizeof(DriverIORange)/sizeof(VIDEO_ACCESS_RANGE)
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* because the expression in a #if statement can't use the
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* sizeof() operator.
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*/
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#define NUM_DRIVER_ACCESS_RANGES 20*5+2
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#define FRAMEBUFFER_ENTRY NUM_DRIVER_ACCESS_RANGES - 1
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#define NUM_IO_ACCESS_RANGES FRAMEBUFFER_ENTRY
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/*
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* Indicate whether the specified address range is in I/O space or
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* memory mapped space. These values are intended to make it easier
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* to read the Driver??Range[] structures.
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*/
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#define ISinIO TRUE
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#define ISinMEMORY FALSE
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//------------------------------------------------------------------
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// struct list is address, 0, length, inIOspace, visible, sharable
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// this order MATCHES AMACH.H ENUM data structure
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// all entries are in INCREASING IO address.
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VIDEO_ACCESS_RANGE DriverIORange_m[NUM_DRIVER_ACCESS_RANGES] = {
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{IO_DAC_MASK , 0, 1, ISinIO, 1, FALSE}, // Mach DAC registers
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{IO_DAC_R_INDEX , 0, 1, ISinIO, 1, FALSE},
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{IO_DAC_W_INDEX , 0, 1, ISinIO, 1, FALSE},
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{IO_DAC_DATA , 0, 3, ISinIO, 1, FALSE},
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{IO_DISP_STATUS , 0, 1, ISinIO, 1, FALSE}, // First Mach register
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{IO_OVERSCAN_COLOR_8 , 0, 2, ISinIO, 1, FALSE},
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{IO_H_DISP , 0, 2, ISinIO, 1, FALSE},
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{IO_OVERSCAN_GREEN_24 , 0, 2, ISinIO, 1, FALSE},
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{IO_H_SYNC_STRT , 0, 1, ISinIO, 1, FALSE},
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{IO_CURSOR_OFFSET_LO , 0, 2, ISinIO, 1, FALSE},
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{IO_H_SYNC_WID , 0, 1, ISinIO, 1, FALSE}, // 10
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{IO_CURSOR_OFFSET_HI , 0, 2, ISinIO, 1, FALSE},
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{IO_V_TOTAL , 0, 2, ISinIO, 1, FALSE},
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{IO_CONFIG_STATUS_1 , 0, 2, ISinIO, 1, FALSE},
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{IO_V_DISP , 0, 2, ISinIO, 1, FALSE},
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{IO_CONFIG_STATUS_2 , 0, 2, ISinIO, 1, FALSE},
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{IO_V_SYNC_STRT , 0, 2, ISinIO, 1, FALSE},
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{IO_CURSOR_COLOR_0 , 0, 2, ISinIO, 1, FALSE},
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{IO_CURSOR_COLOR_1 , 0, 1, ISinIO, 1, FALSE},
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{IO_V_SYNC_WID , 0, 2, ISinIO, 1, FALSE},
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{IO_HORZ_CURSOR_OFFSET, 0, 1, ISinIO, 1, FALSE}, // 20
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{IO_VERT_CURSOR_OFFSET, 0, 1, ISinIO, 1, FALSE},
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{IO_DISP_CNTL , 0, 1, ISinIO, 1, FALSE},
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{IO_CRT_PITCH , 0, 2, ISinIO, 1, FALSE},
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{IO_CRT_OFFSET_LO , 0, 2, ISinIO, 1, FALSE},
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{IO_CRT_OFFSET_HI , 0, 2, ISinIO, 1, FALSE},
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{IO_LOCAL_CONTROL , 0, 2, ISinIO, 1, FALSE},
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{IO_FIFO_OPT , 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_CURSOR_COLOR_0, 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_CURSOR_COLOR_1, 0, 2, ISinIO, 1, FALSE},
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{IO_SUBSYS_CNTL , 0, 2, ISinIO, 1, FALSE}, // 30
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{IO_MEM_BNDRY , 0, 1, ISinIO, 1, FALSE},
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{IO_ROM_PAGE_SEL , 0, 2, ISinIO, 1, FALSE},
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{IO_SHADOW_CTL , 0, 2, ISinIO, 1, FALSE},
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{IO_ADVFUNC_CNTL , 0, 2, ISinIO, 1, FALSE},
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{IO_CLOCK_SEL , 0, 2, ISinIO, 1, FALSE},
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{IO_ROM_ADDR_1 , 0, 2, ISinIO, 1, FALSE},
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{IO_ROM_ADDR_2 , 0, 2, ISinIO, 1, FALSE},
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{IO_SHADOW_SET , 0, 2, ISinIO, 1, FALSE},
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{IO_MEM_CFG , 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_GE_STATUS , 0, 2, ISinIO, 1, FALSE}, // 40
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{IO_VERT_OVERSCAN , 0, 2, ISinIO, 1, FALSE},
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{IO_MAX_WAITSTATES , 0, 2, ISinIO, 1, FALSE},
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{IO_GE_OFFSET_LO , 0, 2, ISinIO, 1, FALSE},
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{IO_BOUNDS_LEFT , 0, 2, ISinIO, 1, FALSE},
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{IO_BOUNDS_TOP , 0, 2, ISinIO, 1, FALSE},
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{IO_BOUNDS_RIGHT , 0, 2, ISinIO, 1, FALSE},
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{IO_BOUNDS_BOTTOM , 0, 2, ISinIO, 1, FALSE},
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{IO_CUR_Y , 0, 2, ISinIO, 1, FALSE},
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{IO_PATT_DATA_INDEX , 0, 2, ISinIO, 1, FALSE},
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{IO_CUR_X , 0, 2, ISinIO, 1, FALSE}, // 50
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{IO_SRC_Y , 0, 2, ISinIO, 1, FALSE},
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{IO_SRC_X , 0, 2, ISinIO, 1, FALSE},
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{IO_PATT_DATA , 0, 2, ISinIO, 1, FALSE},
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{IO_ERR_TERM , 0, 2, ISinIO, 1, FALSE},
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{IO_R_MISC_CNTL , 0, 2, ISinIO, 1, FALSE},
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{IO_MAJ_AXIS_PCNT , 0, 2, ISinIO, 1, FALSE},
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{IO_BRES_COUNT , 0, 2, ISinIO, 1, FALSE},
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{IO_CMD , 0, 2, ISinIO, 1, FALSE},
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{IO_LINEDRAW_INDEX , 0, 2, ISinIO, 1, FALSE},
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{IO_SHORT_STROKE , 0, 2, ISinIO, 1, FALSE}, // 60
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{IO_BKGD_COLOR , 0, 2, ISinIO, 1, FALSE},
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{IO_LINEDRAW_OPT , 0, 2, ISinIO, 1, FALSE},
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{IO_FRGD_COLOR , 0, 2, ISinIO, 1, FALSE},
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{IO_DEST_X_START , 0, 2, ISinIO, 1, FALSE},
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{IO_WRT_MASK , 0, 2, ISinIO, 1, FALSE},
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{IO_DEST_X_END , 0, 2, ISinIO, 1, FALSE},
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{IO_RD_MASK , 0, 2, ISinIO, 1, FALSE},
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{IO_DEST_Y_END , 0, 2, ISinIO, 1, FALSE},
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{IO_CMP_COLOR , 0, 2, ISinIO, 1, FALSE},
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{IO_SRC_X_START , 0, 2, ISinIO, 1, FALSE}, // 70
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{IO_BKGD_MIX , 0, 2, ISinIO, 1, FALSE},
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{IO_ALU_BG_FN , 0, 2, ISinIO, 1, FALSE},
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{IO_FRGD_MIX , 0, 2, ISinIO, 1, FALSE},
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{IO_ALU_FG_FN , 0, 2, ISinIO, 1, FALSE},
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{IO_MULTIFUNC_CNTL , 0, 2, ISinIO, 1, FALSE},
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{IO_SRC_X_END , 0, 2, ISinIO, 1, FALSE},
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{IO_SRC_Y_DIR , 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_SSV , 0, 2, ISinIO, 1, FALSE},
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{IO_SCAN_X , 0, 2, ISinIO, 1, FALSE},
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{IO_DP_CONFIG , 0, 2, ISinIO, 1, FALSE}, // 80
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{IO_PATT_LENGTH , 0, 2, ISinIO, 1, FALSE},
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{IO_PATT_INDEX , 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_SCISSOR_L , 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_SCISSOR_T , 0, 2, ISinIO, 1, FALSE},
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{IO_PIX_TRANS , 0, 2, ISinIO, 1, FALSE},
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{IO_PIX_TRANS_HI , 0, 1, ISinIO, 1, FALSE},
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{IO_EXT_SCISSOR_R , 0, 2, ISinIO, 1, FALSE},
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{IO_EXT_SCISSOR_B , 0, 2, ISinIO, 1, FALSE},
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{IO_DEST_CMP_FN , 0, 2, ISinIO, 1, FALSE},
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{IO_ASIC_ID , 0, 2, ISinIO, 1, FALSE}, // 90
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{IO_LINEDRAW , 0, 2, ISinIO, 1, FALSE},
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{IO_SEQ_IND , 0, 1, ISinIO, 1, TRUE}, // VGA
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{IO_HI_SEQ_ADDR , 0, 2, ISinIO, TRUE, TRUE},
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{IO_SEQ_DATA , 0, 1, ISinIO, TRUE, TRUE},
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{VGA_BASE_IO_PORT , 0, VGA_START_BREAK_PORT - VGA_BASE_IO_PORT + 1, ISinIO, TRUE, TRUE},
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{VGA_END_BREAK_PORT , 0, VGA_MAX_IO_PORT - VGA_END_BREAK_PORT + 1, ISinIO, TRUE, TRUE},
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{0x000001ce , 0, 1, ISinIO, TRUE, TRUE}, /* VGAWonder uses these ports for bank switching */
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{0x000001cf , 0, 1, ISinIO, TRUE, TRUE},
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{IO_EXT_CUR_Y , 0, 2, ISinIO, 1, FALSE},
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{0x000003CE , 0, 2, ISinIO, TRUE, TRUE}, // 100
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{0x00000000, 0, 0, ISinMEMORY, TRUE, FALSE}
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};
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#if NUM_DRIVER_ACCESS_RANGES > NUM_ADDRESS_RANGES_ALLOWED
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Insufficient address ranges for 8514/A-compatible graphics cards.
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#endif
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#define DONT_USE -1 /* Shows that this register is not memory mapped */
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/* struct list is address, 0, length, inIOspace, visible, sharable */
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// this order MATCHES AMACH.H ENUM data structure
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VIDEO_ACCESS_RANGE DriverMMRange_m[NUM_IO_ACCESS_RANGES] = {
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{FALSE , DONT_USE , 4, ISinMEMORY , TRUE , FALSE}, // Mach DAC registers
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{FALSE , DONT_USE , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DISP_STATUS , 0 , 4, ISinMEMORY , TRUE , FALSE}, // First Mach register
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{FALSE , DONT_USE , 2, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , FALSE},
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{MM_CURSOR_OFFSET_LO , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 1, ISinIO , TRUE , FALSE}, // 10
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{MM_CURSOR_OFFSET_HI , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_CONFIG_STATUS_1 , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_CONFIG_STATUS_2 , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_CURSOR_COLOR_0 , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CURSOR_COLOR_1 , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_HORZ_CURSOR_OFFSET , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 20
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{MM_VERT_CURSOR_OFFSET , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DISP_CNTL , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CRT_PITCH , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CRT_OFFSET_LO , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CRT_OFFSET_HI , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_EXT_CURSOR_COLOR_0 , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_EXT_CURSOR_COLOR_1 , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SUBSYS_CNTL , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 30
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{FALSE , DONT_USE , 1, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_ADVFUNC_CNTL , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_EXT_GE_STATUS , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 40
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_GE_OFFSET_LO , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_BOUNDS_LEFT , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_BOUNDS_TOP , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_BOUNDS_RIGHT , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_BOUNDS_BOTTOM , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CUR_Y , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_PATT_DATA_INDEX , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CUR_X , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 50
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{MM_SRC_Y , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SRC_X , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_PATT_DATA , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_ERR_TERM , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_MAJ_AXIS_PCNT , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_BRES_COUNT , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE},
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{MM_LINEDRAW_INDEX , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SHORT_STROKE , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 60
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{MM_BKGD_COLOR , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_LINEDRAW_OPT , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_FRGD_COLOR , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DEST_X_START , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_WRT_MASK , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DEST_X_END , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_RD_MASK , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DEST_Y_END , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_CMP_COLOR , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SRC_X_START , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 70
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{MM_BKGD_MIX , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_ALU_BG_FN , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_FRGD_MIX , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_ALU_FG_FN , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_MULTIFUNC_CNTL , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SRC_X_END , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SRC_Y_DIR , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_EXT_SSV , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_SCAN_X , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DP_CONFIG , 0 , 4, ISinMEMORY , TRUE , FALSE}, // 80
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{MM_PATT_LENGTH , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_PATT_INDEX , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_EXT_SCISSOR_L , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_EXT_SCISSOR_T , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_PIX_TRANS , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_PIX_TRANS_HI , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_EXT_SCISSOR_R , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_EXT_SCISSOR_B , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{MM_DEST_CMP_FN , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , FALSE}, // 90
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{MM_LINEDRAW , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , TRUE}, // VGA
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{FALSE , DONT_USE , 2, ISinMEMORY , TRUE , TRUE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , TRUE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , TRUE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , TRUE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , TRUE},
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{FALSE , DONT_USE , 1, ISinMEMORY , TRUE , TRUE},
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{MM_EXT_CUR_Y , 0 , 4, ISinMEMORY , TRUE , FALSE},
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{FALSE , DONT_USE , 2, ISinIO , TRUE , TRUE} // 100
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};
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#endif /* defined INCLUDE_SETUP_M */
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