452 lines
18 KiB
C
452 lines
18 KiB
C
/*++
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Copyright (c) 1992 Digital Equipment Corporation
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Module Name:
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qvdata.h
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Abstract:
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This module contains all global mode settings used by the QVision driver.
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "dderror.h"
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#include "devioctl.h"
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#include "miniport.h"
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#include "ntddvdeo.h"
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#include "video.h"
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#include "qv.h"
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//
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// Video mode table - Lists the information about each individual mode
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//
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QV_VIDEO_MODES QVModes[] = {
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// 60 Hz modes (Monitor class 3)
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{
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MODE_32, // QVision Video mode
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MONITOR_CLASS_3, // QVision monitor class for 60 Hz
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{
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sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
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0,
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640, // X Resolution, in pixels
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480, // Y Resolution, in pixels
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1024, // Screen stride, in bytes (distance
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// between the start point of two
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// consecutive scan lines, in bytes)
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1, // Number of video memory planes
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8, // Number of bits per plane
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60, // Screen Frequency, in Hertz
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320, // Horizontal size of screen in millimeters
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240, // Vertical size of screen in millimeters
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8, // Number Red pixels in DAC
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8, // Number Green pixels in DAC
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8, // Number Blue pixels in DAC
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0x00000000, // Mask for Red Pixels in non-palette modes
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0x00000000, // Mask for Green Pixels in non-palette modes
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0x00000000, // Mask for Blue Pixels in non-palette modes
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
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VIDEO_MODE_MANAGED_PALETTE, // Mode description flags.
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1024, // Video Memory Bitmap Width
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1024 // Video Memory Bitmap Height
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}
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},
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{
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MODE_34, // QVision Video mode
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MONITOR_CLASS_3, // QVision monitor class for 60 Hz
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{
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sizeof(VIDEO_MODE_INFORMATION),
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0,
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800,
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600,
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1024,
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1,
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8,
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60,
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320,
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240,
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8,
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8,
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8,
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0x00000000,
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0x00000000,
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0x00000000,
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
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VIDEO_MODE_MANAGED_PALETTE,
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1024, // Video Memory Bitmap Width
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1024 // Video Memory Bitmap Height
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}
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},
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{
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MODE_38, // QVision Video mode
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MONITOR_CLASS_3, // QVision monitor class for 60 Hz
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{
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sizeof(VIDEO_MODE_INFORMATION),
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0,
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1024,
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768,
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1024,
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1,
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8,
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60,
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320,
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240,
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8,
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8,
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8,
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0x00000000,
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0x00000000,
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0x00000000,
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
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VIDEO_MODE_MANAGED_PALETTE,
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1024, // Video Memory Bitmap Width
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1024 // Video Memory Bitmap Height
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}
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},
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// 75/72 Hz modes (Monitor class 2)
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{
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MODE_32, // QVision Video mode
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MONITOR_CLASS_2, // QVision monitor class for 75Hz
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{
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sizeof(VIDEO_MODE_INFORMATION), // Size of the mode informtion structure
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0,
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640, // X Resolution, in pixels
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480, // Y Resolution, in pixels
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1024, // Screen stride, in bytes (distance
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// between the start point of two
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// consecutive scan lines, in bytes)
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1, // Number of video memory planes
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8, // Number of bits per plane
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75, // Screen Frequency, in Hertz
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320, // Horizontal size of screen in millimeters
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240, // Vertical size of screen in millimeters
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8, // Number Red pixels in DAC
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8, // Number Green pixels in DAC
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8, // Number Blue pixels in DAC
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0x00000000, // Mask for Red Pixels in non-palette modes
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0x00000000, // Mask for Green Pixels in non-palette modes
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0x00000000, // Mask for Blue Pixels in non-palette modes
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
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VIDEO_MODE_MANAGED_PALETTE, // Mode description flags.
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1024, // Video Memory Bitmap Width
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1024 // Video Memory Bitmap Height
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}
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},
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{
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MODE_34, // QVision Video mode
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MONITOR_CLASS_2, // QVision monitor class for 72Hz
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{
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sizeof(VIDEO_MODE_INFORMATION),
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0,
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800,
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600,
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1024,
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1,
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8,
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72,
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320,
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240,
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8,
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8,
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8,
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0x00000000,
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0x00000000,
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0x00000000,
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
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VIDEO_MODE_MANAGED_PALETTE,
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1024, // Video Memory Bitmap Width
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1024 // Video Memory Bitmap Height
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}
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},
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{
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MODE_38, // QVision Video mode
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MONITOR_CLASS_2, // QVision monitor class for 72Hz
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{
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sizeof(VIDEO_MODE_INFORMATION),
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0,
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1024,
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768,
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1024,
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1,
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8,
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72,
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320,
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240,
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8,
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8,
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8,
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0x00000000,
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0x00000000,
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0x00000000,
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VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_PALETTE_DRIVEN |
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VIDEO_MODE_MANAGED_PALETTE,
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1024, // Video Memory Bitmap Width
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1024 // Video Memory Bitmap Height
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}
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}
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};
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ULONG NumVideoModes = sizeof(QVModes) / sizeof(QV_VIDEO_MODES);
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/*************************************************************************
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* SetMode register values
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*
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* The following data tables are used by the SetMode function to load
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* the appropriate register values for a video mode switch. Each table
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* contains 8 entries which can be either a single value or another table.
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* These entries correspond to register values for one of the eight new
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* Triton video modes as follows:
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*
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* Video Mode Mode Type Table Index
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* ---------- ---------- -----------
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* 32 640x480x8 0
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* 34 800x600x8 1
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* 38 1024x768x8 2
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* 3B 512x480x16 3
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* 3C 640x400x16 4
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* 3E 640x480x16 5
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* 4D 512x480x32 6
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* 4E 640x400x32 7
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*
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*
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* The first group of tables below contain one set of values which apply
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* to all classes of monitors. For these tables, the first index selects
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* the video mode and the second (if applicable) selects the port index.
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* The second group of tables contain a set of values for each monitor
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* class. For these tables, the first index selects the monitor class,
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* the second selects the video mode, and the third (if applicable) selects
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* the port index. Four monitor classes are currently defined (see the
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* SetMode header) but more may be added by simply appending a new set of
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* register values for the new monitor class to the appropriate data tables
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* below and incrementing the #define constant, MON_CLASS_CNT. Note that
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* monitor class 3 is a special case in that its true register values are
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* loaded at run time.
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*
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*************************************************************************/
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/*************************************************************************
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* The following tables have only one set of values which apply to all
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* monitor classes.
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*************************************************************************/
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/* Sequencer register values (3C5.00 - 3C5.04) */
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UCHAR abSeq[MODE_CNT][SEQ_CNT] = {
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{ 0x01, 0x01, 0xff, 0x00, 0x0e },
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{ 0x03, 0x01, 0xff, 0x00, 0x0e }, // MODE_34
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{ 0x01, 0x01, 0xff, 0x00, 0x0e },
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{ 0x01, 0x01, 0xff, 0x00, 0x0e },
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{ 0x01, 0x01, 0xff, 0x00, 0x0e },
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{ 0x01, 0x01, 0xff, 0x00, 0x0e },
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{ 0x01, 0x01, 0xff, 0x00, 0x0e },
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{ 0x01, 0x01, 0xff, 0x00, 0x0e } };
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/* Attribute Controller register values (3C0.00 - 3C0.13h) */
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UCHAR abAttr[MODE_CNT][ATTR_CNT] = {
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 },
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{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a,
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0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 0x41, 0x00, 0x0f, 0x00 } };
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/* Graphics Controller register values (3CF.00 - 3CF.08) */
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UCHAR abGraphics[MODE_CNT][GRFX_CNT] = {
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff } };
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/* Control Register 1 values (63CA) */
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UCHAR abCtrlReg1[MODE_CNT] =
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{ 0x03, 0x03, 0x03, 0x05, 0x05, 0x05, 0x07, 0x07 };
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/* DAC Command Register 1 values (13C8) */
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UCHAR abDacCmd1[MODE_CNT] =
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{ 0x40, 0x40, 0x40, 0x20, 0x20, 0x20, 0x00, 0x00 };
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/* Overflow Register 1 values (3CF.42h) */
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UCHAR abOverflow1[MODE_CNT] =
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01 };
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/*************************************************************************
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* The following tables have a different set of values for each monitor
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* class.
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*************************************************************************/
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/* CRTC register values (3D5.00 - 3D5.18h) */
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UCHAR abCrtc[MON_CLASS_CNT][MODE_CNT][CRTC_CNT] = {
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{
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/* CRTC register values for monitor class 0 */
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x8c, 0xdf, 0x80, 0x00, 0xe5,
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0x03, 0xe3, 0xff },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00 },
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{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00 },
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{ 0x4a, 0x3f, 0x3f, 0x8d, 0x42, 0x0c, 0x0e, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0x8e, 0xdf, 0x80, 0x00, 0xe5,
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0x06, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x84, 0x8f, 0xa0, 0x00, 0x95,
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0x03, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x8c, 0xdf, 0xa0, 0x00, 0xe5,
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0x03, 0xe3, 0xff },
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{ 0x4a, 0x3f, 0x3f, 0x8d, 0x42, 0x0c, 0x0e, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0x8e, 0xdf, 0x00, 0x00, 0xe5,
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0x06, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x84, 0x8f, 0x40, 0x00, 0x95,
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0x03, 0xe3, 0xff }
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},
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{
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/* CRTC register values for monitor class 1 */
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x8c, 0xdf, 0x80, 0x00, 0xe5,
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0x03, 0xe3, 0xff },
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{ 0xa1, 0x7f, 0x7f, 0x84, 0x87, 0x9d, 0x2e, 0xf5, 0x00, 0x60, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x8b, 0xff, 0x40, 0x00, 0xff,
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0x2e, 0xe3, 0xff },
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{ 0xa1, 0x7f, 0x7f, 0x84, 0x85, 0x9b, 0x2e, 0xf5, 0x00, 0x60, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x8b, 0xff, 0x80, 0x00, 0xff,
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0x2e, 0xe3, 0xff },
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{ 0x4a, 0x3f, 0x3f, 0x8d, 0x42, 0x0c, 0x0e, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0x8e, 0xdf, 0x80, 0x00, 0xe5,
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0x06, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x84, 0x8f, 0xa0, 0x00, 0x95,
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0x03, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x8c, 0xdf, 0xa0, 0x00, 0xe5,
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0x03, 0xe3, 0xff },
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{ 0x4a, 0x3f, 0x3f, 0x8d, 0x42, 0x0c, 0x0e, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0x8e, 0xdf, 0x00, 0x00, 0xe5,
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0x06, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x84, 0x8f, 0x40, 0x00, 0x95,
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0x03, 0xe3, 0xff }
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},
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{
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/* CRTC register values for monitor class 2 */
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{ 0x69, 0x4f, 0x55, 0x86, 0x58, 0x80, 0x56, 0xb2, 0x00, 0x60, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x83, 0xdf, 0x80, 0x00, 0x01,
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0x32, 0xe3, 0xff }, // MODE_32
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{ 0x8b, 0x63, 0x66, 0x8b, 0x6d, 0x1d, 0xe9, 0xf0, 0x00, 0x60, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x8a, 0x57, 0x80, 0x00, 0x6e,
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0xd1, 0xe3, 0xff }, // MODE_34
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{ 0x9e, 0x7f, 0x7f, 0x81, 0x83, 0x93, 0x1e, 0xf1, 0x00, 0x60, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x83, 0xff, 0x80, 0x00, 0xff,
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0x1e, 0xe3, 0xff }, // MODE_38
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{ 0x54, 0x3f, 0x44, 0x92, 0x47, 0x0d, 0x56, 0xb2, 0x00, 0x60, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x83, 0xdf, 0x80, 0x00, 0x01,
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0x32, 0xe3, 0xff },
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{ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, 0x00, 0x40, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x8e, 0x8f, 0x50, 0x00, 0x96,
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0xb9, 0xe3, 0xff },
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|
{ 0x69, 0x4f, 0x55, 0x86, 0x58, 0x80, 0x56, 0xb2, 0x00, 0x60, 0x00,
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|
0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x83, 0xdf, 0xa0, 0x00, 0x01,
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|
0x32, 0xe3, 0xff },
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|
{ 0x54, 0x3f, 0x44, 0x92, 0x47, 0x0d, 0x56, 0xb2, 0x00, 0x60, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x83, 0xdf, 0x00, 0x00, 0x01,
|
|
0x32, 0xe3, 0xff },
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|
{ 0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0xbf, 0x1f, 0x00, 0x40, 0x00,
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|
0x00, 0x00, 0x00, 0x00, 0x00, 0x9c, 0x8e, 0x8f, 0x50, 0x00, 0x96,
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|
0xb9, 0xe3, 0xff }
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|
},
|
|
{
|
|
/* CRTC register array for monitor class 3 (3rd party) */
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{ 0x5f, 0x4f, 0x50, 0x81, 0x53, 0x9f, 0x0b, 0x3e, 0x00, 0x40, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0x8c, 0xdf, 0x80, 0x00, 0xe5,
|
|
0x03, 0xe3, 0xff }, // MODE_32
|
|
{ 0x7f, 0x63, 0x64, 0x80, 0x68, 0x19, 0x73, 0xf0, 0x00, 0x60, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x8c, 0x57, 0x80, 0x00, 0x58,
|
|
0x72, 0xe3, 0xff }, // MODE_34
|
|
{ 0x9b, 0x7f, 0x7f, 0x9e, 0x87, 0x17, 0x31, 0xf5, 0x00, 0x60, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x94, 0xff, 0x80, 0x00, 0xff,
|
|
0x31, 0xe3, 0xff }, // MODE_38
|
|
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00 },
|
|
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00 },
|
|
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00 },
|
|
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00 },
|
|
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00 }
|
|
} };
|
|
|
|
/* Miscellaneous Output Reg. values (3C2) */
|
|
UCHAR abMiscOut[MON_CLASS_CNT][MODE_CNT] =
|
|
{
|
|
/* Monitor class 0 */
|
|
{ 0xef, 0x00, 0x00, 0xf7, 0x6f, 0xef, 0xf7, 0x6f },
|
|
|
|
/* Monitor class 1 */
|
|
{ 0xef, 0x27, 0x27, 0xf7, 0x6f, 0xef, 0xf7, 0x6f },
|
|
|
|
/* Monitor class 2 */
|
|
{ 0xf3, 0x23, 0x2b, 0xfb, 0x6f, 0xf3, 0xfb, 0x6f }, // mode 32, 34, 38...
|
|
|
|
/* Monitor class 3 (loaded later) */
|
|
{ 0xef, 0xf3, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00 } // mode 32, 34, 38...
|
|
};
|
|
|
|
/* Overflow Register 2 values (3CF.51h) */
|
|
UCHAR abOverflow2[MON_CLASS_CNT][MODE_CNT] =
|
|
{
|
|
/* Monitor class 0 */
|
|
{ 0x08, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08 },
|
|
|
|
/* Monitor class 1 */
|
|
{ 0x08, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08 },
|
|
|
|
/* Monitor class 2 */
|
|
{ 0x28, 0x20, 0x00, 0x08, 0x28, 0x28, 0x08, 0x28 }, // [1] = MODE_34
|
|
|
|
/* Monitor class 3 (loaded later) */
|
|
{ 0x08, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // [1] = MODE_34
|
|
};
|