688 lines
22 KiB
C
688 lines
22 KiB
C
/*++
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Copyright (c) 1992 Microsoft Corporation
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Copyright (c) 1993 Western Digital Corporation
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Copyright (c) 1994-1995 IBM Corporation
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Module Name:
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wd90c24a.h
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Abstract:
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This module contains the definitions for the WD90C24A/A2 miniport driver.
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Environment:
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Kernel mode
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Revision History:
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--*/
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//
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// Assume PPC is Linear Framebuffer (1MB aperture)
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//
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#ifdef PPC
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#define ENABLE_LINEAR_FRAME_BUFFER 1
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#define NO_INT10_MODE_SET 1
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#endif
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#ifndef NO_INT10_MODE_SET
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#define INT10_MODE_SET 1
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#endif
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//
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// Do full save and restore.
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//
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// #define EXTENDED_REGISTER_SAVE_RESTORE 1
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//
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// Capabilities flags
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//
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// These are private flags passed to the display driver. They're
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// put in the 'DriverSpecificAttributeFlags' field of the
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// 'VIDEO_MODE_INFORMATION' structure (found in 'ntddvdeo.h') passed
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// to the display driver via an 'VIDEO_QUERY_AVAIL_MODES' or
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// 'VIDEO_QUERY_CURRENT_MODE' IOCTL.
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//
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// NOTE: These definitions must match those in the display driver's
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// 'driver.h'!
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typedef enum {
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CAPS_NEED_SW_POINTER = 0x00000100, // Needs the pointer simulation
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// for the virtual screen
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} CAPS;
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//
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// Define type of WD boards
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//
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typedef enum _BOARD_TYPE {
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WDPVGA1A = 1,
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WD90C00,
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WD90C10, // WD90C10 or WD90C11
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WD90C20, // WD90C20 or WD90C22
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WD90C30,
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SPEEDSTAR30,
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WD90C26,
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WD90C26A,
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WD90C24,
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WD90C24A, // WD90C24A or WD90C24A2
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WD90C31,
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SPEEDSTAR31,
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WD90C33,
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OTHER
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} BOARD_TYPE;
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typedef enum _LCD_TYPE{
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NoLCD = 1, // CRT
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IBM_F8515 = 2, // CRT + IBM F8515 10.4" TFT LCD
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IBM_F8532 = 4, // CRT + IBM F8532 10.4" TFT SVGA LCD
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TOSHIBA_DSTNC = 8 // CRT + Toshiba 10.4" Dual Scan STN Color LCD
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} LCD_TYPE;
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#define LCD_ENABLE 1
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#define LCD_DISABLE 0
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#define CRT_ENABLE 2
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#define CRT_DISABLE 0
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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#define MEM_VGA 0xA0000
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#define MEM_VGA_SIZE 0x20000
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#ifdef ENABLE_LINEAR_FRAME_BUFFER
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//
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// Base address of Linear-Framebuffer in a 1MB aperture video memory range.
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//
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#define MEM_FRAME 0x100000 // WD linear address start address
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#define MEM_FRAME_SIZE 0x100000 // 1MB for 1024x768x256 maximum
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#endif
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//
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// Port definitions for filling the ACCSES_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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#define WD_EXT_PORT_START 0x000023C0
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#define WD_EXT_PORT_END 0x000023C7
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//
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// VGA port-related definitions.
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//
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//
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// VGA register definitions
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//
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// ports in monochrome mode
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#define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
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#define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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#define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x3C0
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#define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x0015 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x0017 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
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// port
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#define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x001F // and Data registers
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#define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
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// port in color mode
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
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// VGA registers.
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//
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#define CRTC_ADDRESS_MONO_OFFSET 0x04
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#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
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#define ATT_ADDRESS_OFFSET 0x10
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#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
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#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
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#define SEQ_ADDRESS_OFFSET 0x14
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#define DAC_PIXEL_MASK_OFFSET 0x16
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#define DAC_STATE_OFFSET 0x17
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#define DAC_ADDRESS_WRITE_OFFSET 0x18
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#define GRAPH_ADDRESS_OFFSET 0x1E
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#define CRTC_ADDRESS_COLOR_OFFSET 0x24
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#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
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//
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// VGA indexed register indexes.
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Highest valid palette register index
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//
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#define VIDEO_MAX_PALETTE_REGISTER 0x0F
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//
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// Indices for type of memory mapping; used in ModesVGA[], must match
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// MemoryMap[].
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//
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typedef enum _VIDEO_MEMORY_MAP {
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MemMap_Mono,
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MemMap_CGA,
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MemMap_VGA,
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#ifdef ENABLE_LINEAR_FRAME_BUFFER
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MemMap_FRAME // new memory map for frame buffer
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#endif
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} VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP;
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//
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// Memory map table definition
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//
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typedef struct {
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ULONG MaxSize; // Maximum addressable size of memory.
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ULONG Start; // Start address of mode.
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} MEMORYMAPS;
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//
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// For a mode, the type of banking supported. Controls the information
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// returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking.
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//
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typedef enum _BANK_TYPE {
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NoBanking = 0,
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NormalBanking,
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PlanarHCBanking
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} BANK_TYPE, *PBANK_TYPE;
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//
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// Structure used to describe each video mode in ModesVGA[].
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//
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#define NUM_DISPLAY_MODE 2 // 0:CRT Only or Simultaneously
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// 1:Simultaneously
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typedef struct {
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USHORT fbType; // color or monochrome, text or graphics, via
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// VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
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USHORT numPlanes; // # of video memory planes
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USHORT bitsPerPlane; // # of bits of color in each plane
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SHORT col; // # of text columns across screen with default font
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SHORT row; // # of text rows down screen with default font
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USHORT hres; // # of pixels across screen
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USHORT vres; // # of scan lines down screen
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USHORT wbytes; // # of bytes from start of one scan line to start of next
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ULONG sbytes; // total size of addressable display memory in bytes
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ULONG Frequency; // Vertical Frequency
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ULONG Interlaced; // Determines if the mode is interlaced or not
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BANK_TYPE banktype; // NoBanking, NormalBanking, PlanarHCBanking
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VIDEO_MEMORY_MAP MemMap; // index from VIDEO_MEMORY_MAP of memory
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// mapping used by this mode
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LCD_TYPE LCDtype; // LCD types to be supported by this mode
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BOOLEAN ValidMode; //Determines which modes are valid.
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#ifdef INT10_MODE_SET
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UCHAR FrequencyMask; // value used to mask the mode frequency
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UCHAR FrequencySetting; // value used to set the mode frequency
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ULONG Int10ModeNumber; // Mode number via Int 10
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#endif
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PUSHORT CmdStrings[NUM_DISPLAY_MODE]; // pointer to array of register-setting commands
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ULONG DisplayDevices[NUM_DISPLAY_MODE];
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} VIDEOMODE, *PVIDEOMODE;
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//
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// Mode into which to put the VGA before starting a VDM, so it's a plain
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// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
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// 80x25 text mode.)
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//
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#define DEFAULT_MODE 0
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//
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// Info for the validator functions.
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//
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//
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// Number of each type of indexed register in a standard VGA, used by
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// validator and state save/restore functions.
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//
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// Note: VDMs currently only support basic VGAs only.
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//
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#define VGA_NUM_SEQUENCER_PORTS 5
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#define VGA_NUM_CRTC_PORTS 25
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#define VGA_NUM_GRAPH_CONT_PORTS 9
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#define VGA_NUM_ATTRIB_CONT_PORTS 21
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#define VGA_NUM_DAC_ENTRIES 256
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#ifdef EXTENDED_REGISTER_SAVE_RESTORE
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//
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// Indices to start save/restore in extension registers:
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// For both chip types
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#define WD_GRAPH_EXT_START 0x09
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#define WD_GRAPH_EXT_END 0x0E
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#define WD_SEQUENCER_EXT_START 0x07
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#define WD_SEQUENCER_EXT_END 0x09
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#define WD_SEQUENCER_1_EXT_START 0x10
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#define WD_SEQUENCER_1_EXT_END 0x14
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#define WD_CRTC_EXT_START 0x2A
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#define WD_CRTC_EXT_END 0x30
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#define WD_CRTC_1_EXT_START 0x3E
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#define WD_CRTC_1_EXT_END 0x3E
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//
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// Number of extended regs for both chip types.
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//
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#define WD_NUM_GRAPH_EXT_PORTS (WD_GRAPH_EXT_END - WD_GRAPH_EXT_START + 1)
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#define WD_NUM_SEQUENCER_EXT_PORTS (WD_SEQUENCER_EXT_END - WD_SEQUENCER_EXT_START + 1) + \
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(WD_SEQUENCER_1_EXT_END - WD_SEQUENCER_1_EXT_START + 1)
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#define WD_NUM_CRTC_EXT_PORTS (WD_CRTC_EXT_END - WD_CRTC_EXT_START + 1) + \
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(WD_CRTC_1_EXT_END - WD_CRTC_1_EXT_START + 1)
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//
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// set values for save/restore area based on largest value for a chipset.
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//
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#define EXT_NUM_GRAPH_CONT_PORTS WD_NUM_GRAPH_EXT_PORTS
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#define EXT_NUM_SEQUENCER_PORTS WD_NUM_SEQUENCER_EXT_PORTS
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#define EXT_NUM_CRTC_PORTS WD_NUM_CRTC_EXT_PORTS
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#define EXT_NUM_ATTRIB_CONT_PORTS 0
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#define EXT_NUM_DAC_ENTRIES 0
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#else
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#define EXT_NUM_GRAPH_CONT_PORTS 0
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#define EXT_NUM_SEQUENCER_PORTS 0
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#define EXT_NUM_CRTC_PORTS 0
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#define EXT_NUM_ATTRIB_CONT_PORTS 0
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#define EXT_NUM_DAC_ENTRIES 0
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#endif
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#ifdef i386
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//
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// Info used by the Validator functions and save/restore code.
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// Structure used to trap register accesses that must be done atomically.
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//
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#define VGA_MAX_VALIDATOR_DATA 100
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#define VGA_VALIDATOR_UCHAR_ACCESS 1
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#define VGA_VALIDATOR_USHORT_ACCESS 2
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#define VGA_VALIDATOR_ULONG_ACCESS 3
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typedef struct _VGA_VALIDATOR_DATA {
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ULONG Port;
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UCHAR AccessType;
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ULONG Data;
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} VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
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//
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// Info for the save and restore state functions.
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//
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//
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// Number of bytes to save in each plane.
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//
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#define VGA_PLANE_SIZE 0x10000
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//
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// These constants determine the offsets within the
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// VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
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// restore the VGA's state.
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//
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#define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
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#define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
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#define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
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VGA_NUM_SEQUENCER_PORTS)
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#define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
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VGA_NUM_CRTC_PORTS)
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#define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
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VGA_NUM_GRAPH_CONT_PORTS)
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#define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
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VGA_NUM_ATTRIB_CONT_PORTS)
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#define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
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(3 * VGA_NUM_DAC_ENTRIES))
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#define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
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#define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
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EXT_NUM_SEQUENCER_PORTS)
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#define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
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EXT_NUM_CRTC_PORTS)
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#define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET + \
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EXT_NUM_GRAPH_CONT_PORTS)
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#define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
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EXT_NUM_ATTRIB_CONT_PORTS)
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#define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
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#define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
|
||
sizeof (VGA_VALIDATOR_DATA)) + \
|
||
sizeof (ULONG) + \
|
||
sizeof (ULONG) + \
|
||
sizeof (PVIDEO_ACCESS_RANGE)
|
||
|
||
#define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
|
||
|
||
#define VGA_MISC_DATA_AREA_SIZE 0
|
||
|
||
#define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
|
||
|
||
#define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
|
||
#define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
|
||
#define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
|
||
|
||
//
|
||
// Space needed to store all state data.
|
||
//
|
||
|
||
#define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
|
||
|
||
#endif
|
||
|
||
//
|
||
// Device extension for the driver object. This data is only used
|
||
// locally, so this structure can be added to as needed.
|
||
//
|
||
|
||
typedef struct _HW_DEVICE_EXTENSION {
|
||
|
||
PUCHAR IOAddress; // base I/O address of VGA ports
|
||
PUCHAR ExtendedIOAddress; // base I/O Address of Extended ports
|
||
PVOID VideoMemoryAddress; // base virtual memory address of VGA memory
|
||
ULONG AdapterMemorySize; // size, in bytes, of the memory on the
|
||
// board.
|
||
ULONG ModeIndex; // index of current mode in ModesVGA[]
|
||
ULONG NumAvailableModes; // number of valid modes on this device
|
||
PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
|
||
// current mode
|
||
|
||
#ifdef i386
|
||
|
||
USHORT FontPelColumns; // Width of the font in pels
|
||
USHORT FontPelRows; // height of the font in pels
|
||
|
||
VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
|
||
|
||
UCHAR CursorEnable; // whether cursor is enabled or not
|
||
UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
|
||
UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
|
||
|
||
#endif
|
||
|
||
UCHAR BoardID; // Used to identify different boards
|
||
// supported.
|
||
|
||
// Flat Panel Information
|
||
UCHAR PanelType; // Type
|
||
ULONG PanelXResolution; // Horizontal Resolution
|
||
ULONG PanelYResolution; // Vertical Resolution
|
||
|
||
BOOLEAN ExtendedRegisters; // Determines if extended registers have
|
||
// been claimed.
|
||
|
||
PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
|
||
ULONG PhysicalVideoMemoryLength; // length of display memory
|
||
PHYSICAL_ADDRESS PhysicalFrameBase; // physical memory address and
|
||
ULONG PhysicalFrameLength; // length of display memory for
|
||
// the current mode.
|
||
#ifdef i386
|
||
|
||
//
|
||
// These 4 fields must be at the end of the device extension and must be
|
||
// kept in this order since this data will be copied to and from the save
|
||
// state buffer that is passed to and from the VDM.
|
||
//
|
||
|
||
ULONG TrappedValidatorCount; // number of entries in the Trapped
|
||
// validator data Array.
|
||
VGA_VALIDATOR_DATA TrappedValidatorData[VGA_MAX_VALIDATOR_DATA];
|
||
// Data trapped by the validator routines
|
||
// but not yet played back into the VGA
|
||
// register.
|
||
|
||
ULONG SequencerAddressValue; // Determines if the Sequencer Address Port
|
||
// is currently selecting the SyncReset data
|
||
// register.
|
||
|
||
ULONG CurrentNumVdmAccessRanges; // Number of access ranges in
|
||
// the access range array pointed
|
||
// to by the next field
|
||
PVIDEO_ACCESS_RANGE CurrentVdmAccessRange; // Access range currently
|
||
// associated to the VDM
|
||
|
||
#endif
|
||
|
||
ULONG CRTPresent; // External CRT Present(1) or not(0)
|
||
ULONG LCDEnable; // 0: LCD Disable 1: LCD Enable
|
||
|
||
ULONG VirtualScreenEnable; // 0: Panning disable 1: Panning enable
|
||
ULONG VirtualScreenPosX; // Horizontal position of virtual screen window
|
||
ULONG VirtualScreenPosY; // Vertial position of virtual screen window
|
||
USHORT VirtualScreenOption; // User preference
|
||
// 0 = OFF
|
||
// 1 = ON
|
||
// 2 = AUTO
|
||
|
||
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
||
|
||
|
||
//
|
||
// Function prototypes.
|
||
//
|
||
|
||
#ifdef i386
|
||
|
||
//
|
||
// Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
|
||
//
|
||
|
||
VP_STATUS
|
||
VgaValidatorUcharEntry (
|
||
ULONG Context,
|
||
ULONG Port,
|
||
UCHAR AccessMode,
|
||
PUCHAR Data
|
||
);
|
||
|
||
VP_STATUS
|
||
VgaValidatorUshortEntry (
|
||
ULONG Context,
|
||
ULONG Port,
|
||
UCHAR AccessMode,
|
||
PUSHORT Data
|
||
);
|
||
|
||
VP_STATUS
|
||
VgaValidatorUlongEntry (
|
||
ULONG Context,
|
||
ULONG Port,
|
||
UCHAR AccessMode,
|
||
PULONG Data
|
||
);
|
||
|
||
BOOLEAN
|
||
VgaPlaybackValidatorData (
|
||
PVOID Context
|
||
);
|
||
|
||
//
|
||
// Bank switch code start and end labels, define in HARDWARE.ASM
|
||
//
|
||
|
||
extern UCHAR BankSwitchStart;
|
||
extern UCHAR BankSwitchEnd;
|
||
|
||
//
|
||
// Vga init scripts for font loading
|
||
//
|
||
|
||
extern USHORT EnableA000Data[];
|
||
extern USHORT DisableA000Color[];
|
||
|
||
#endif
|
||
|
||
extern MEMORYMAPS MemoryMaps[];
|
||
extern VIDEOMODE ModesVGA[];
|
||
extern ULONG NumVideoModes;
|
||
|
||
|
||
#ifndef ENABLE_LINEAR_FRAME_BUFFER
|
||
#define NUM_WD_ACCESS_RANGES 4
|
||
#else
|
||
#define NUM_WD_ACCESS_RANGES 5
|
||
#endif
|
||
|
||
#define NUM_VGA_ACCESS_RANGES 3
|
||
extern VIDEO_ACCESS_RANGE VgaAccessRange[];
|
||
|
||
#ifdef i386
|
||
|
||
#define VGA_NUM_EMULATOR_ACCESS_ENTRIES 6
|
||
extern EMULATOR_ACCESS_ENTRY VgaEmulatorAccessEntries[];
|
||
|
||
#define NUM_MINIMAL_VGA_VALIDATOR_ACCESS_RANGE 4
|
||
extern VIDEO_ACCESS_RANGE MinimalVgaValidatorAccessRange[];
|
||
|
||
#define NUM_FULL_VGA_VALIDATOR_ACCESS_RANGE 2
|
||
extern VIDEO_ACCESS_RANGE FullVgaValidatorAccessRange[];
|
||
|
||
#endif
|