649 lines
19 KiB
C
649 lines
19 KiB
C
/*++
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Copyright (c) 1993, 1994 Weitek Corporation
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Module Name:
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p9100.c
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Abstract:
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This module contains the code specific to the Weitek P9100.
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Environment:
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Kernel mode
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Revision History may be found at the end of this file.
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--*/
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#include "p9.h"
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#include "p9gbl.h"
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#include "p91regs.h"
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#ifdef _MIPS_
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# include "vga.h"
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# include "wtkp9xvl.h"
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#endif
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VOID
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InitP9100(
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PHW_DEVICE_EXTENSION HwDeviceExtension
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)
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/*++
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Routine Description:
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Initialize the P9100.
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Arguments:
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HwDeviceExtension - Pointer to the miniport driver's device extension.
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Return Value:
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None.
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--*/
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{
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VideoDebugPrint((2, "InitP9100------\n"));
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P9_WR_REG(P91_INTERRUPT_EN, 0x00000080L); //INTERRUPT-EN = disabled
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P9_WR_REG(P91_PREHRZC, 0x00000000L); //PREHRZC = 0
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P9_WR_REG(P91_PREVRTC, 0x00000000L); //PREVRTC = 0
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//
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// Initialize the P9100 registers.
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//
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P9_WR_REG(P91_RFPERIOD, 0x00000186L); //RFPERIOD =
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P9_WR_REG(P91_RLMAX, 0x000000FAL); //RLMAX =
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P9_WR_REG(P91_DE_PMASK, 0xFFFFFFFFL); //allow writing in all 8 planes
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P9_WR_REG(P91_DE_DRAW_MODE, P91_WR_INSIDE_WINDOW | P91_DE_DRAW_BUFF_0);
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P9_WR_REG(P91_PE_W_OFF_XY, 0x00000000L); //disable any co-ord offset
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return;
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}
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VOID
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P91_WriteTiming(
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PHW_DEVICE_EXTENSION HwDeviceExtension
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)
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/*++
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Routine Description:
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Initializes the P9100 Crtc timing registers.
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Arguments:
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HwDeviceExtension - Pointer to the miniport driver's device extension.
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Return Value:
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None.
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--*/
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{
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int num, den, bpp;
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ULONG ulValueRead, ulValueWritten;
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ULONG ulHRZSR;
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ULONG ulHRZBR;
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ULONG ulHRZBF;
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ULONG ulHRZT;
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VideoDebugPrint((2, "P91_WriteTiming - Entry\n"));
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bpp = HwDeviceExtension->usBitsPixel / 8; // Need bytes per pixel
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//
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// 24-bit color
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//
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if (bpp == 3)
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{
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num = 3;
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den = HwDeviceExtension->Dac.usRamdacWidth/8;
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}
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else
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{
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num = 1;
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den = HwDeviceExtension->Dac.usRamdacWidth/(bpp * 8);
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}
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//
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// Calculate HRZSR.
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//
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ulHRZSR = (ULONG) (HwDeviceExtension->VideoData.hsyncp /
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(ULONG) den) * (ULONG) num;
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ulHRZSR -= HwDeviceExtension->p91State.ulBlnkDlyAdj;
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//
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// Calculate HRZBR.
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//
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ulHRZBR = (ULONG) ((HwDeviceExtension->VideoData.hsyncp +
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HwDeviceExtension->VideoData.hbp) / (ULONG) den) *
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(ULONG) num;
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ulHRZBR -= HwDeviceExtension->p91State.ulBlnkDlyAdj;
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// ulHRZBR -= 4;
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ulHRZBF = (ULONG) ( (HwDeviceExtension->VideoData.hsyncp+
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HwDeviceExtension->VideoData.hbp+
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HwDeviceExtension->VideoData.XSize) / (ULONG) den) * (ULONG) num;
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//
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// Calculate HRZBF.
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//
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ulHRZBF -= HwDeviceExtension->p91State.ulBlnkDlyAdj;
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// ulHRZBF -= 4;
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ulHRZT = (ULONG) ( (HwDeviceExtension->VideoData.hsyncp+
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HwDeviceExtension->VideoData.hbp+
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HwDeviceExtension->VideoData.XSize+
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HwDeviceExtension->VideoData.hfp) /
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(ULONG) den) * (ULONG) num;
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--ulHRZT;
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//
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// Changes requested by Rober Embry, Jan 26 Spec.
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//
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if (HwDeviceExtension->Dac.ulDacId == DAC_ID_BT489)
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{
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//
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// Fix for fussy screen problem, Per Sam Jenson
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//
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ulHRZT = 2 * (ulHRZT>>1) + 1;
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}
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if ((HwDeviceExtension->Dac.ulDacId == DAC_ID_BT489) ||
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(HwDeviceExtension->Dac.ulDacId == DAC_ID_BT485))
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{
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if (bpp == 1)
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{
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ulHRZBR -= 12 * num / den;
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ulHRZBF -= 12 * num / den;
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}
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else
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{
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ulHRZBR -= 9 * num / den;
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ulHRZBF -= 9 * num / den;
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}
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}
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//
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// By robert embry 12/1/94
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//
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// The hardware configuration (Power 9100 version and DAC type) affects
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// the minimum horizontal back porch timing that a board can support.
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// The most flexible (able to support the smallest back porch)
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// configuration is with Power 9100 A4 with the IBM or ATT DAC.
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//
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// The Power 9100 A2 increases the front porch minimum by one.
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// The Brooktree DAC increases the front porch minimum by one, also.
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//
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// Configuration Min. Back Porch
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// ----------------- ---------------
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// P9100 A4, IBM/ATT DAC 40 pixels (5 CRTC clocks)
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// P9100 A2, IBM/ATT DAC 48 pixels (6 CRTC clocks)
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// P9100 A4, BT485/9 DAC 48 pixels (6 CRTC clocks)
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// P9100 A2, BT485/9 DAC 56 pixels (7 CRTC clocks)
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//
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// Since we want one P9x00RES.DAT file AND we don't want to penalize the
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// most common configuration, the driver needs to choose the best fit
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// when the P9x00RES.DAT file specifies a set of parameters that are not
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// supported.
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//
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// Algorithm for BEST FIT:
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//
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// First, time must be taken from something else. Either by shortening
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// the pulse width or the front porch (shifts line to right.) The
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// largest value of the two is decreased, sync pulse if equal.
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//
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// A given P9x00RES.DAT file will result in valid register values
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// in one hardware configuration, but not in another. This code
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// adjusts these register values so the P9x00RES.DAT file parameters
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// work for all boards, but not necesarily giving the requested timing.
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// The P9100 A4 silicon with an IBM or ATT DAC is the best case.
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// When the P9100 A2 or a Brooktree DAC is present then the
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// minimum supportable horizontal back porch is enlarged.
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//
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// psuedo BASIC code:
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//
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// This is parameter checking code for the Power 9100's hrzSR and hrzBR
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// registers. The following equation must be satisfied: hrzSR < hrzBR.
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//
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// If this equation is violated in the presence of the Power 9100 A2
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// silicon or a non-pipelined DAC (BT485/9) then these register values
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// are modified.
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//
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// This code should go just before the registers are written.
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// The register values may need to be modified by up to 2 counts.
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//
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// IF (DacType=BT485 OR DacType=BT485A OR DacType=BT489 OR _
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// SiliconVerion=A2) THEN {
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// WHILE hrzSR >= hrzBR {
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// IF hsp>hfp THEN DECR hrzSR _ ;shrink sync pulse width
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// ELSE INCR hrzBR :INCR hrzBF ;shorten front porch
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// } }
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//
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if ((HwDeviceExtension->Dac.ulDacId == DAC_ID_BT489) ||
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(HwDeviceExtension->Dac.ulDacId == DAC_ID_BT485) ||
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(HwDeviceExtension->p91State.usRevisionID < WTK_9100_REV3))
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{
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while (ulHRZSR >= ulHRZBR)
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{
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if (HwDeviceExtension->VideoData.hsyncp >
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HwDeviceExtension->VideoData.hfp)
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{
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ulHRZSR--;
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}
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else
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{
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ulHRZBR++;
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ulHRZBF++;
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}
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}
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}
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//
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// Write to the video timing registers
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//
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do
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{
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P9_WR_REG(P91_HRZSR, ulHRZSR);
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ulValueRead = (ULONG) P9_RD_REG(P91_HRZSR);
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} while (ulValueRead != ulHRZSR);
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do
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{
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P9_WR_REG(P91_HRZBR, ulHRZBR);
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ulValueRead = (ULONG) P9_RD_REG(P91_HRZBR);
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} while (ulValueRead != ulHRZBR);
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do
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{
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P9_WR_REG(P91_HRZBF, ulHRZBF);
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ulValueRead = (ULONG) P9_RD_REG(P91_HRZBF);
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} while (ulValueRead != ulHRZBF);
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do
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{
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P9_WR_REG(P91_HRZT, ulHRZT);
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ulValueRead = (ULONG) P9_RD_REG(P91_HRZT);
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} while (ulValueRead != ulHRZT);
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ulValueWritten = (ULONG) HwDeviceExtension->VideoData.vsp;
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do
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{
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P9_WR_REG(P91_VRTSR, ulValueWritten);
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ulValueRead = (ULONG) P9_RD_REG(P91_VRTSR);
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} while (ulValueRead != ulValueWritten);
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ulValueWritten = (ULONG) HwDeviceExtension->VideoData.vsp+
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HwDeviceExtension->VideoData.vbp;
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do
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{
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P9_WR_REG(P91_VRTBR, ulValueWritten);
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ulValueRead = (ULONG) P9_RD_REG(P91_VRTBR);
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} while (ulValueRead != ulValueWritten);
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ulValueWritten = (ULONG) HwDeviceExtension->VideoData.vsp+
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HwDeviceExtension->VideoData.vbp+
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HwDeviceExtension->VideoData.YSize;
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do
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{
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P9_WR_REG(P91_VRTBF, ulValueWritten);
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ulValueRead = (ULONG) P9_RD_REG(P91_VRTBF);
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} while (ulValueRead != ulValueWritten);
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ulValueWritten = (ULONG) HwDeviceExtension->VideoData.vsp+
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HwDeviceExtension->VideoData.vbp+
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HwDeviceExtension->VideoData.YSize+
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HwDeviceExtension->VideoData.vfp;
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do
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{
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P9_WR_REG(P91_VRTT, ulValueWritten);
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ulValueRead = (ULONG) P9_RD_REG(P91_VRTT);
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} while (ulValueRead != ulValueWritten);
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VideoDebugPrint((2, "P91_WriteTiming - Exit\n"));
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return;
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} // End of P91_WriteTimings()
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VOID
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P91_SysConf(
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PHW_DEVICE_EXTENSION HwDeviceExtension
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)
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/*++
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Routine Description:
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Syscon converts the ->XSize value into the correct bits in
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the System Configuration Register and writes the register
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(This register contains the XSize of the display.)
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Half-word and byte swapping are set via bits: 12 & 13;
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The shift control fields are set to the size of the scanline in bytes;
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And pixel size is set to bits per pixel.
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XSize and ulFrameBufferSize must be set prior to entering this routine.
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This routine also initializes the clipping registers.
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Arguments:
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HwDeviceExtension - Pointer to the miniport driver's device extension.
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Return Value:
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None.
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--*/
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{
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int i, j, iBytesPerPixel; // loop counters
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long sysval; // swap bytes and words for little endian PC
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int xtem = (int) HwDeviceExtension->VideoData.XSize;
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long ClipMax; // clipping register value for NotBusy to restore
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iBytesPerPixel = (int) HwDeviceExtension->usBitsPixel / 8; // Calc Bytes/pixel
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xtem *= iBytesPerPixel;
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VideoDebugPrint((2, "P91_SysConf------\n"));
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//
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// The following sets up the System Configuration Register
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// for BPP with byte and half-word swapping. This swapping
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// is usually what is needed since the frame-buffer is stored
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// in big endian pixel format and the 80x86 software usually
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// expects little endian pixel format.
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//
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if (iBytesPerPixel == 1)
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sysval = SYSCFG_BPP_8;
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else if (iBytesPerPixel == 2)
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sysval = SYSCFG_BPP_16;
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else if (iBytesPerPixel == 3)
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sysval = SYSCFG_BPP_24;
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else // if (iBytesPerPixel == 4)
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sysval = SYSCFG_BPP_32;
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//
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// Now set the Shift3, Shift0, Shift1 & Shift2 multipliers.
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//
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// Each field in the sysconfig can only set a limited
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// range of bits in the size.
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//
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if (xtem & 0x1c00) // 7168
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{
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//
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// Look at all the bits for shift control 3
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//
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j=3;
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for (i=4096;i>=1024;i>>=1)
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{
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//
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// If this bit is on...
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//
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if (i & xtem)
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{
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//
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// Use this field to set it and
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// remove the bit from the size. Each
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// field can only set one bit.
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//
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sysval |= ((long)j)<<29;
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xtem &= ~i;
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break;
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}
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j=j-1;
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}
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}
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if (xtem & 0xf80) // each field in the sysconreg can only set
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{ // a limited range of bits in the size
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j = 7; // each field is 3 bits wide
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//
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// Look at all the bits for shift control 0
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//
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for (i = 2048; i >= 128;i >>= 1) // look at all the bits field 3 can effect
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{
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if (i & xtem) // if this bit is on,
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{
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sysval |= ((long) j) << 20; // use this field to set it
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xtem &= ~i; // and remove the bit from the size
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break; // each field can only set one bit
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}
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j -= 1;
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}
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}
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if (xtem & 0x7C0) // do the same thing for field 2
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{
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//
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// Do the same thing for shift control 1
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//
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j = 6; // each field is 3 bits wide
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for (i = 1024; i >= 64; i >>= 1) // look at all the bits field 2 can effect
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{
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if (i & xtem) // if this bit is on,
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{
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sysval |= ((long)j)<<17; // use this field to set it
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xtem &= ~i; // and remove the bit from the size
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break; // each field can only set one bit
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}
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j -= 1;
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}
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}
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if (xtem & 0x3E0) // do the same thing for field 1
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{
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j = 5; // each field is 3 bits wide
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//
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// do the same thing for shift control 2
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//
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for (i = 512; i >= 32;i >>= 1) // look at all the bits field 1 can effect
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{
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if (i & xtem) // if this bit is on,
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{
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sysval |= ((long) j) << 14; // use this field to set it
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xtem &= ~i; // and remove the bit from the size
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break; // each field can only set one bit
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}
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j -= 1;
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}
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}
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//
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// If there are bits left, it is an illegal x size. This just means
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// that we cannot handle it because we have not implemented a
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// full multiplier. However, the vast majority of screen sizes can be
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// expressed as a sum of few powers of two.
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//
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if (xtem != 0) // if there are bits left, it is an
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return; // illegal x size.
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VideoDebugPrint((2, "P91_SysConf:sysval = 0x%lx\n", sysval));
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P9_WR_REG(P91_SYSCONFIG, sysval); // send data to the register
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xtem = (int) (HwDeviceExtension->VideoData.XSize * (ULONG) iBytesPerPixel);
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//
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// Now calculate and set the max clipping to allow access to all of
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// the extra memory.
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//
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// There are two sets of clipping registers. The first takes the
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// horizontal diemnsion in pixels and the vertical dimension in
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// scanlines.
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//
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ClipMax=((long) HwDeviceExtension->VideoData.XSize - 1L) << 16 |
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(div32(HwDeviceExtension->FrameLength, (USHORT) xtem) - 1L);
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P9_WR_REG(P91_DE_P_W_MIN, 0L);
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P9_WR_REG(P91_DE_P_W_MAX, ClipMax);
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//
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// The second set takes the horizontal dimension in bytes and the
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// vertical dimension in scanlines.
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//
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ClipMax=((long) xtem -1L) << 16 |
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(div32(HwDeviceExtension->FrameLength, (USHORT) xtem) - 1L); // calc and set max
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P9_WR_REG(P91_DE_B_W_MIN, 0L);
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P9_WR_REG(P91_DE_B_W_MAX, ClipMax);
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return;
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} // End of P91_SysConf()
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#ifdef _MIPS_
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/***************************************************************************\
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* *
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* Save & Restore VGA registers routines *
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* *
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* this is to avoid "blind" boot end *
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* *
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\***************************************************************************/
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void P91SaveVGARegs(PHW_DEVICE_EXTENSION HwDeviceExtension,VGA_REGS * SaveVGARegisters)
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{
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UCHAR ucIndex ;
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ULONG ulIndex ;
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/* Miscellaneous Output Register: [3C2]w, [3CC]r */
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SaveVGARegisters->MiscOut = VGA_RD_REG(0x00C) ;
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/* CRT Controller Registers 0-18: index [3D4], data [3D5] */
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for (ucIndex = 0 ; ucIndex < 0x18 ; ucIndex ++)
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||
{
|
||
VGA_WR_REG(0x014 ,ucIndex) ;
|
||
SaveVGARegisters->CR[ucIndex] = VGA_RD_REG(0x015) ;
|
||
}
|
||
|
||
/* Sequencer Registers 1-4: index [3C4], data [3C5] */
|
||
for (ucIndex = 1 ; ucIndex < 4 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x004 ,ucIndex) ;
|
||
SaveVGARegisters->SR[ucIndex] = VGA_RD_REG(0x005) ;
|
||
}
|
||
|
||
/* Graphics Controller Registers 0-8: index [3CE], data [3CF] */
|
||
for (ucIndex = 0 ; ucIndex < 8 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x00E ,ucIndex) ;
|
||
SaveVGARegisters->GR[ucIndex] = VGA_RD_REG(0x00F) ;
|
||
}
|
||
|
||
/* Attribute Controller Registers 0-14: index and data [3C0]w, [3C1]r */
|
||
VGA_RD_REG(0x01A) ; /* set toggle to index mode */
|
||
for (ucIndex = 0 ; ucIndex < 0x14 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x000 ,ucIndex) ; /* write index */
|
||
SaveVGARegisters->AR[ucIndex] = VGA_RD_REG(0x001) ; /* read data */
|
||
VGA_WR_REG(0x000 ,SaveVGARegisters->AR[ucIndex]) ; /* toggle */
|
||
}
|
||
|
||
/* Look-Up Table: Read Index [3C7]w, Write Index [3C8], Data [3C9] */
|
||
VGA_WR_REG(0x007 ,0) ; /* set read index to 0 */
|
||
for (ulIndex = 0 ; ulIndex < (3 * 256) ; ulIndex ++)
|
||
{
|
||
SaveVGARegisters->LUT[ulIndex] = VGA_RD_REG(0x009) ;
|
||
}
|
||
}
|
||
|
||
|
||
void P91RestoreVGAregs(PHW_DEVICE_EXTENSION HwDeviceExtension,VGA_REGS * SaveVGARegisters)
|
||
{
|
||
UCHAR ucIndex ;
|
||
ULONG ulIndex ;
|
||
|
||
WriteP9ConfigRegister(HwDeviceExtension,P91_CONFIG_MODE,0x2);
|
||
/* Put the VGA back in color mode for our PROM */
|
||
VGA_WR_REG(MISCOUT ,1) ;
|
||
|
||
/* Enable VGA Registers: [3C3] = 1 */
|
||
VGA_WR_REG(0x003 ,1) ;
|
||
|
||
/* Miscellaneous Output Register: [3C2]w, [3CC]r */
|
||
VGA_WR_REG(0x002 ,SaveVGARegisters->MiscOut) ;
|
||
|
||
/* Enable CR0-CR7: CR11[7] = 0 */
|
||
VGA_WR_REG(0x014 ,0x11) ;
|
||
VGA_WR_REG(0x015 ,SaveVGARegisters->CR[0x11] & 0x7F) ;
|
||
|
||
/* CRT Controller Registers 0-18: index [3D4], data [3D5] */
|
||
for (ucIndex = 0 ; ucIndex < 0x18 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x014 ,ucIndex) ;
|
||
VGA_WR_REG(0x015 ,SaveVGARegisters->CR[ucIndex]) ;
|
||
}
|
||
|
||
/* Synchronous Reset: SR0 = 1 */
|
||
VGA_WR_REG(0x004 ,0) ;
|
||
VGA_WR_REG(0x005 ,1) ;
|
||
|
||
/* ClockMode: SR1 */
|
||
VGA_WR_REG(0x004 ,1) ;
|
||
VGA_WR_REG(0x005 ,SaveVGARegisters->SR[1]) ;
|
||
|
||
/* Non Reset Mode: SR0 = 0 */
|
||
VGA_WR_REG(0x004 ,0) ;
|
||
VGA_WR_REG(0x005 ,0) ;
|
||
|
||
/* Sequencer Registers 2-4: index [3C4], data [3C5] */
|
||
for (ucIndex = 2 ; ucIndex < 4 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x004 ,ucIndex) ;
|
||
VGA_WR_REG(0x005 ,SaveVGARegisters->SR[ucIndex]) ;
|
||
}
|
||
|
||
/* Graphics Controller Regs 0-8: index [3CE], data [3CF] */
|
||
VGA_WR_REG(0x00E ,1) ;
|
||
VGA_WR_REG(0x00F ,0x0F) ; /* enable all 4 planes for GR0 */
|
||
for (ucIndex = 0 ; ucIndex < 8 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x00E ,ucIndex) ;
|
||
VGA_WR_REG(0x00F ,SaveVGARegisters->GR[ucIndex]) ;
|
||
}
|
||
|
||
/* Attrib Controller Regs 0-14:index and data [3C0]w,[3C1]r */
|
||
VGA_RD_REG(0x01A) ; /* set toggle to index mode */
|
||
for (ucIndex = 0 ; ucIndex < 0x14 ; ucIndex ++)
|
||
{
|
||
VGA_WR_REG(0x000 ,ucIndex) ; /* write index */
|
||
VGA_WR_REG(0x000 ,SaveVGARegisters->AR[ucIndex]) ;
|
||
/* write data */
|
||
}
|
||
VGA_WR_REG(0x000 ,0x20) ; /* set index[5] to 1 */
|
||
|
||
/* Look-Up Table:
|
||
Read Index [3C7]w, Write Index [3C8], Data [3C9] */
|
||
VGA_WR_REG(0x008 ,0) ; /* set write index to 0 */
|
||
for (ulIndex = 0 ; ulIndex < (3 * 256) ; ulIndex ++)
|
||
{
|
||
VGA_WR_REG(0x009 ,SaveVGARegisters->LUT[ulIndex]) ;
|
||
}
|
||
}
|
||
|
||
#endif
|