170 lines
11 KiB
C
170 lines
11 KiB
C
/**********************************************************************************
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*
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* machine-struct.h -- Definition of "machine-op" structure
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*
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**********************************************************************************
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*
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* $Header: /u/simpson/ppcas/src/RCS/machine-struct.h,v 4.3 1993/03/23 18:50:16 simpson Exp $
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*
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* $Log: machine-struct.h,v $
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* Revision 4.3 1993/03/23 18:50:16 simpson
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* Added support for extended shift/rotate ops such as "clrlsldi"
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*
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* Revision 4.2 93/03/16 21:07:22 simpson
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* Fixed handling of "too large" operands on shifted instrs.
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*
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* Revision 4.1 93/03/02 16:02:29 simpson
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* Major checkpoint before modifying relocation logic
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*
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* Revision 1.4 93/03/02 15:43:19 simpson
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* First cut at support for branch prediction op suffix (+, -)
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*
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* Revision 1.3 92/11/24 17:16:16 simpson
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* Addition of MXU instructions to assembler, including padding with
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* no-ops (0x60000000) where necessary
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*
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* Revision 1.2 92/11/23 16:51:13 simpson
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* First trial since adding 8-byte instr capability, in prep for MXU
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*
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* Revision 1.1 92/11/20 11:12:02 simpson
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* Initial revision
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*
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*/
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/*
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* Hash-lookup on machine-op (doesn't start with '.') yields
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* a pointer to one of these, or NULL:
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*/
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typedef struct _machine_op {
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char *name; /* op-code */
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PPC_INSTRUCTION template; /* binary pattern to be filled in */
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unsigned long template2; /* used if instr is > 4 bytes long */
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unsigned long arch_flags; /* flags for instr features, applicable architectures */
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unsigned long inst_mask; /* instruction decode mask */
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char len; /* instruction length, in bytes */
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char align; /* alignment req't, in bytes */
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char count; /* count of operands for this template */
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char arg_types[5]; /* array of operand types */
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} *machine_op;
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#define OPT_BC_Rel 0x80000000 /* Branch condition relative (can take +/- for br. pred. */
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#define OPT_BC_Abs 0x40000000 /* Branch condition absolute (can take +/- for br. pred. */
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#define OPT_BC_Reg 0x20000000 /* Branch condition register (can take +/- for br. pred. */
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#define OPT_BC 0xE0000000 /* Any of the above ... */
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#define OPT_RC 0x10000000 /* Mnemonic can end in '.', causing RC to be set */
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#define OPT_Special 0x08000000 /* Special processing of operands needed (machine-ops.c) */
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#define OPT_crbA_eq_crbB 0x04000000
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#define OPT_rS_eq_rB 0x02000000
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#define OPT_Simplified 0x06000000
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#define ARCH_Power 0x00000001 /* original Power (RS/6000) */
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#define ARCH_RIOS_2 0x00000002 /* RIOS-2 added instructions */
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#define ARCH_PowerPC_1_0 0x00000004 /* PowerPC Version 1.00 */
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#define ARCH_Amazon_1_0 0x00000008 /* Amazon Version 1.00 */
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#define ARCH_MXU_1_01 0x00000010 /* Matrix unit Version 1.01 */
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/* Note: instructions in the "base" architecture have 0xFFFF for the "arch" field */
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/*
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* Values of entries in the arg_types array
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*/
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enum opnd {
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/* Name Length Sign Start End Description */
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opBA = 1, /* 5 U 11 15 CR bit number */
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opBB, /* 5 U 16 20 CR bit number */
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opBD, /* 14 +- 16 29 Branch displacement, relative, in words */
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opBDA, /* 14 U 16 29 Branch address, absolute, in words */
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opBFcr, /* 3 U 6 8 CR field number */
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opBFfpscr, /* 3 U 6 8 FPSCR field number */
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opBFAcr, /* 3 U 11 13 CR field number */
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opBFAfpscr, /* 3 U 11 13 FPSCR field number */
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opBI, /* 5 U 11 15 CR bit number */
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opBO, /* 5 U 6 10 Branch options */
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opBTcr, /* 5 U 6 10 CR bit number */
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opBTfpscr, /* 5 U 6 10 FPSCR bit number */
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opDBATL, /* 10 U 11* 20 Data BAT (Lower) register number */
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opDBATU, /* 10 U 11* 20 Data BAT (Upper) register number */
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opFLM, /* 8 U 7 14 FPSCR field mask */
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opFL1, /* 4 U 16 19 Power SVC code */
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opFL2, /* 3 U 27 29 Power SVC code */
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opFRA, /* 5 U 11 15 Floating point register number */
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opFRB, /* 5 U 16 20 Floating point register number */
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opFRC, /* 5 U 21 25 Floating point register number */
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opFRS, /* 5 U 6 10 Floating point register number */
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opFRT, /* 5 U 6 10 Floating point register number */
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opFXM, /* 8 U 12 19 CR field mask */
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opIBATL, /* 10 U 11* 20 Instruction BAT (Lower) register number */
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opIBATU, /* 10 U 11* 20 Instruction BAT (Upper) register number */
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opL, /* 1 U 10 10 Length code for compare instructions */
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opLEV, /* 7 U 20 26 Level number (vector) in 'scv' (Amazon, Power) */
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opLI, /* 24 +- 6 29 Branch displacement, relative, in words */
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opLIA, /* 24 U 6 29 Branch address, absolute, in words */
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opMB32, /* 5 U 21 25 Mask begin bit number */
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opMB64, /* 6 U 21 26 Mask begin bit number */
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opME32, /* 5 U 26 30 Mask end bit number */
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opME64, /* 6 U 21 26 Mask end bit number */
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opNB, /* 5 U 16 20 Number of bytes (string move) */
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opRA, /* 5 U 11 15 General register number */
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opRB, /* 5 U 16 20 General register number */
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opRS, /* 5 U 6 10 General register number */
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opRT, /* 5 U 6 10 General register number */
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opSH32, /* 5 U 16 20 Shift amount */
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opSH64, /* 6 U 16* - Shift amount. High-order bit is 30 */
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opSI, /* 16 +- 16 31 Signed immediate */
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opSIneg, /* 16 +- 16 31 Signed immediate negated */
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opSIign, /* 16 +-U 16 31 Immediate operand, sign ignored (for "addis" et al.) */
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opSInegign, /* 16 +-U 16 31 Same, but subtract from 0 first */
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opSPR, /* 10 U 11* 20 SPR number (5-bit halves reversed) */
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opSPRG, /* 10 U 11* 20 SPRG number in 'mtsprg/mfsprg' */
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opSR, /* 4 U 12 15 Segment Register number */
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opSV, /* 14 U 16 29 Power SVC code */
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opTO, /* 5 U 6 10 Trap options */
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opU, /* 4 U 16 19 Immediate data for FPSCR field */
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opUI, /* 16 U 16 31 Unsigned immediate */
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/* Other kinds of operands, not 1-for-1 with machine instruction fields: */
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opMASK32, /* 32 U - - 32-bit mask; field of 1's w/in 0's or vice versa */
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opMASK64L, /* 64 U - - 64-bit mask, with implicit Mask Begin = 0 */
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opMASK64R, /* 64 U - - 64-bit mask, with implicit Mask End = 63 */
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opMASK64SH, /* 64 U - - 64-bit mask, with Mask End = 63 - SH */
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opMB64X, /* - - - - Mask Begin field *not* present in instruction */
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opME64X, /* - - - - Mask End field *not* present in instruction */
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opME64XSH, /* - - - - Mask End field *not* present, form 63 - SH */
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opBDISP, /* - - - - Base (5-bit reg) and Displacement (16-bit) */
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opBDISP14, /* - - - - Base (5-bit reg) and Displacement (14-bit) */
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opBP32, /* 5 U - - Bit position in a 32-bit reg (0:31) */
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opBP64, /* 6 U - - Bit position in a 64-bit reg (0:63) */
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opNB32, /* 6 U - - Number of bits (1:32) */
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opNB64, /* 7 U - - Number of bits (1:64) */
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opTBfrom, /* 10 U 11* 20 268 or 269; time base number (5-bit halves reversed) */
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opTBto, /* 10 U 11* 20 284 or 285; time base number (5-bit halves reversed) */
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/* Matrix Unit operands */
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opBS, /* 11 U 41 51 Matrix ? */
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opBT, /* 11 U 41 51 Matrix ? */
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opC, /* 1 U 40 40 Matrix ? */
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opCT, /* 5 U 40 44 Matrix CType */
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opMA, /* 11 U 52 62 Matrix ? */
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opMB, /* 11 U 19 29 Matrix ? */
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opMI, /* 11 U 52 62 Matrix ? */
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opMS, /* 11 U 41 51 Matrix source */
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opMT, /* 11 U 41 51 Matrix target */
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opMX, /* 11 U 52 62 Matrix ? */
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opMXC, /* 6 U 13 18 Matrix ? */
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opMXCT, /* 5 U 47 51 Matrix ? */
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opIGNORE /* Operand removed from instruction template; don't generate anything for opnd */
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};
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typedef struct _opcode_indx {
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unsigned long op_index; /* start of next opcode in machine_ops */
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} *opcode_indx;
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