172 lines
4.7 KiB
ArmAsm
172 lines
4.7 KiB
ArmAsm
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// TITLE("Interlocked Support")
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//++
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//
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// Copyright (c) 1998 Intel Corporation
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// Copyright (c) 1998 Microsoft Corporation
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//
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// Module Name:
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//
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// slist.s
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//
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// Abstract:
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//
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// This module implements functions to support interlocked S_List
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// operations.
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//
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// Author:
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//
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// William K. Cheung (v-wcheung) 10-Mar-1998
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//
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// Environment:
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//
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// User mode.
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//
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// Revision History:
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//
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//--
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#include "ksia64.h"
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SBTTL("Interlocked Pop Entry Sequenced List")
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//++
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//
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// PSINGLE_LIST_ENTRY
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// RtlpInterlockedPopEntrySList (
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// IN PSLIST_HEADER ListHead
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// )
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//
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// Routine Description:
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//
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// This function removes an entry from the front of a sequenced singly
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// linked list so that access to the list is synchronized in a MP system.
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// If there are no entries in the list, then a value of NULL is returned.
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// Otherwise, the address of the entry that is removed is returned as the
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// function value.
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//
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// Arguments:
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//
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// ListHead (a0) - Supplies a pointer to the sequenced listhead from which
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// an entry is to be removed.
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//
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// Return Value:
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//
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// The address of the entry removed from the list, or NULL if the list is
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// empty.
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//
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//--
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LEAF_ENTRY(RtlpInterlockedPopEntrySList)
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ld8 t0 = [a0] // load next entry & sequence
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add t6 = 0xFFFF, r0
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dep t1 = 0, a0, 0, 61 // capture region bits
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;;
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Epop10:
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mov ar.ccv = t0
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shr t2 = t0, 63 - 42 + 3
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;;
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shladd v0 = t2, 3, t1 // merge region & va bits
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;;
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cmp.eq pt2, pt1 = t1, v0 // if eq, list is empty
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add t4 = t6, t0 // adjust depth & sequence
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;;
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(pt2) add v0 = 0, zero
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//
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// N.B. It is possible for the following instruction to fault in the rare
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// case where the first entry in the list is allocated on another
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// processor and free between the time the free pointer is read above
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// and the following instruction.
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//
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(pt1) ld8 t5 = [v0] // get addr of successor entry
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extr.u t4 = t4, 0, 24 // extract depth & sequence
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;;
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(pt1) shl t5 = t5, 63 - 42 // shift va into position
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;;
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(pt1) ld8 t3 = [a0] // reload next entry & sequence
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(pt1) or t5 = t4, t5 // merge va, depth & sequence
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(pt2) br.ret.spnt.clr brp // return if the list is null
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;;
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(pt1) cmp.eq.unc pt4, pt1 = t3, t0
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;;
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(pt4) cmpxchg8.rel.nt1 t3 = [a0], t5, ar.ccv // perform the pop
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nop.i 0
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;;
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(pt4) cmp.eq.unc pt3 = t3, t0 // if eq, cmpxchg8 succeeded
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mov t0 = t3
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(pt3) br.ret.sptk brp
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br Epop10 // try again
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LEAF_EXIT(RtlpInterlockedPopEntrySList)
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//++
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//
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// PSINGLE_LIST_ENTRY
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// RtlpInterlockedPushEntrySList (
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// IN PSLIST_HEADER ListHead,
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// IN PSINGLE_LIST_ENTRY ListEntry
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// )
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//
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// Routine Description:
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//
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// This function inserts an entry at the head of a sequenced singly linked
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// list so that access to the list is synchronized in an MP system.
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//
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// Arguments:
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//
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// ListHead (a0) - Supplies a pointer to the sequenced listhead into which
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// an entry is to be inserted.
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//
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// ListEntry (a1) - Supplies a pointer to the entry to be inserted at the
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// head of the list.
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//
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// Return Value:
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//
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// Previous contents of ListHead. NULL implies list went from empty
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// to not empty.
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//
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//--
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LEAF_ENTRY(RtlpInterlockedPushEntrySList)
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ld8 t0 = [a0] // load next entry & sequence
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dep t1 = 0, a0, 0, 61 // capture region bits
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mov t6 = 0x10001
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shl t5 = a1, 63 - 42 // shift va into position
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;;
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Epush10:
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mov ar.ccv = t0 // set the comparand
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add t4 = t0, t6
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shr v0 = t0, 63 - 42 + 3 // extract next entry address
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;;
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cmp.ne pt3 = zero, v0 // if ne, list not empty
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;;
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(pt3) shladd v0 = v0, 3, t1 // merge region & va bits
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extr.u t4 = t4, 0, 24 // extract depth & sequence
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;;
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st8 [a1] = v0
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or t5 = t4, t5 // merge va, depth & sequence
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;;
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cmpxchg8.rel t3 = [a0], t5, ar.ccv
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;;
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cmp.eq pt2, pt1 = t0, t3
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mov t0 = t3
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(pt2) br.ret.sptk brp // if equal, return
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(pt1) br.spnt Epush10 // retry
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LEAF_EXIT(RtlpInterlockedPushEntrySList)
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