507 lines
12 KiB
C
507 lines
12 KiB
C
/*++
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Copyright (c) 1994 NEC Corporation
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Copyright (c) 1994 NEC Software, Ltd.
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Module Name:
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nec98.h (cf. eisa.h)
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Abstract:
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The module defines the structures, and defines for the NEC PC98 chip set.
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Author:
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Michio Nakamura 20-Sep-1994
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Revision History:
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Takaaki Tochizawa 13-Mar-1998 Add 2nd DMA for FIR.
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*/
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#ifndef _EISA_
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#define _EISA_
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// Define the DMA page register structure.
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#define DMA_BANK_A31_A24_DR0 0xe05
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#define DMA_BANK_A31_A24_DR1 0xe07
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#define DMA_BANK_A31_A24_DR2 0xe09
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#define DMA_BANK_A31_A24_DR3 0xe0b
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#define DMA_INC_ENABLE_A31_A24 0xe0f
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// Define the DMA 2 page register structure.
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#define DMA2_BANK_A31_A24_DR5 0xf07
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#define DMA2_BANK_A31_A24_DR6 0xf09
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#define DMA2_BANK_A31_A24_DR7 0xf0b
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#define DMA2_INC_ENABLE_A31_A24 0xf0f
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// Define the DMA 2 mode change register
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#define DMA2_MODE_CHANGE 0xf4
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#define DMA2_MODE_8237_COMP 0x0
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#define DMA2_MODE_71037_A 0x1
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#define DMA2_MODE_71037_B 0x2
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#define DMA2_MODE_71037_C 0x3
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#define DMA_STATUS 0xc8
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#define DMA_COMMAND 0xc8
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#define SINGLE_MASK 0xca
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#define MODE 0xcb
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#define CLEAR_BYTE_POINTER 0xcc
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#define CLEAR_MASK 0xce
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typedef struct _DMA_PAGE{
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UCHAR Reserved1; // offset 0x20
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UCHAR Channel1; // offset 0x21
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UCHAR Reserved2;
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UCHAR Channel2; // offset 0x23
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UCHAR Reserved3;
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UCHAR Channel3; // offset 0x25
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UCHAR Reserved4;
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UCHAR Channel0; // offset 0x27
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UCHAR Reserved5[0x120-0x27];// offset 0x120
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UCHAR Channel5; // offset 0x121
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UCHAR Reserved6;
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UCHAR Channel6; // offset 0x123
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UCHAR Reserved7;
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UCHAR Channel7; // offset 0x125
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UCHAR Reserved8[4];
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}DMA_PAGE, *PDMA_PAGE;
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// Define the DMA stop register structure.
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typedef struct _DMA_CHANNEL_STOP {
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UCHAR ChannelLsb;
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UCHAR ChannelMsb;
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UCHAR ChannelHsb;
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UCHAR Reserved;
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}DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
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// Define DMA 1 address and count structure.
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typedef struct _DMA1_ADDRESS_COUNT {
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UCHAR Reserved1;
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UCHAR DmaBaseAddress;
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UCHAR Reserved2;
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UCHAR DmaBaseCount;
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}DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
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// Define DMA 2 address and count structure.
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typedef struct _DMA2_ADDRESS_COUNT {
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UCHAR Reserved1;
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UCHAR DmaBaseAddress;
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UCHAR Reserved2;
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UCHAR DmaBaseCount;
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}DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
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// Define DMA 1 control register structure.
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typedef struct _DMA1_CONTROL {
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DMA1_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR Reserved1;
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UCHAR DmaStatus; //offset 0x11
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UCHAR Reserved2;
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UCHAR DmaRequest; //offset 0x13
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UCHAR Reserved3;
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UCHAR SingleMask; //offset 0x15
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UCHAR Reserved4;
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UCHAR Mode; //offset 0x17
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UCHAR Reserved5;
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UCHAR ClearBytePointer; //offset 0x19
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UCHAR Reserved6;
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UCHAR MasterClear; //offset 0x1b
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UCHAR Reserved7;
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UCHAR ClearMask; //offset 0x1d
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UCHAR Reserved;
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UCHAR AllMask; //offset 0x1f
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}DMA1_CONTROL, *PDMA1_CONTROL;
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// Define DMA 2 control register structure.
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typedef struct _DMA2_CONTROL {
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UCHAR Reserved8[0x100-0x20];//offset 0x20
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DMA2_ADDRESS_COUNT DmaAddressCount[4]; //offset 0x100
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UCHAR Reserved1;
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UCHAR DmaStatus; //offset 0x111
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UCHAR Reserved2;
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UCHAR DmaRequest; //offset 0x113
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UCHAR Reserved3;
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UCHAR SingleMask; //offset 0x115
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UCHAR Reserved4;
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UCHAR Mode; //offset 0x117
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UCHAR Reserved5;
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UCHAR ClearBytePointer; //offset 0x119
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UCHAR Reserved6;
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UCHAR MasterClear; //offset 0x11b
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UCHAR Reserved7;
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UCHAR ClearMask; //offset 0x11d
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UCHAR Reserved;
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UCHAR AllMask; //offset 0x11f
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UCHAR Reserved9[10]; //offset 0x120
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}DMA2_CONTROL, *PDMA2_CONTROL;
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// Define Timer control register structure.
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typedef struct _TIMER_CONTROL {
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UCHAR BcdMode : 1;
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UCHAR Mode : 3;
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UCHAR SelectByte : 2;
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UCHAR SelectCounter : 2;
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}TIMER_CONTROL, *PTIMER_CONTROL;
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// Define Timer status register structure.
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typedef struct _TIMER_STATUS {
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UCHAR BcdMode : 1;
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UCHAR Mode : 3;
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UCHAR SelectByte : 2;
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UCHAR CrContentsMoved : 1;
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UCHAR OutPin : 1;
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}TIMER_STATUS, *PTIMER_STATUS;
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// Define Mode values.
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#define TM_SIGNAL_END_OF_COUNT 0
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#define TM_ONE_SHOT 1
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#define TM_RATE_GENERATOR 2
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#define TM_SQUARE_WAVE 3
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#define TM_SOFTWARE_STROBE 4
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#define TM_HARDWARE_STROBE 5
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// Define SelectByte values
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#define SB_COUNTER_LATCH 0
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#define SB_LSB_BYTE 1
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#define SB_MSB_BYTE 2
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#define SB_LSB_THEN_MSB 3
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// Define SelectCounter values.
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#define SELECT_COUNTER_0 0
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#define SELECT_COUNTER_1 1
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#define SELECT_COUNTER_2 2
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#define SELECT_READ_BACK 3
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// Define Timer clock for speaker.
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#define TIMER_CLOCK_IN 1193167 // 1.193Mhz
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// Define NMI Status/Control register structure.
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typedef struct _NMI_STATUS {
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UCHAR SpeakerGate : 1;
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UCHAR SpeakerData : 1;
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UCHAR DisableEisaParity : 1;
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UCHAR DisableNmi : 1;
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UCHAR RefreshToggle : 1;
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UCHAR SpeakerTimer : 1;
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UCHAR IochkNmi : 1;
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UCHAR ParityNmi : 1;
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}NMI_STATUS, *PNMI_STATUS;
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// Define NMI Enable register structure.
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typedef struct _NMI_ENABLE {
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UCHAR RtClockAddress : 7;
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UCHAR NmiDisable : 1;
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}NMI_ENABLE, *PNMI_ENABLE;
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// Define the NMI extended status and control register structure.
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typedef struct _NMI_EXTENDED_CONTROL {
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UCHAR BusReset : 1;
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UCHAR EnableNmiPort : 1;
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UCHAR EnableFailSafeNmi : 1;
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UCHAR EnableBusMasterTimeout : 1;
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UCHAR Reserved1 : 1;
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UCHAR PendingPortNmi : 1;
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UCHAR PendingBusMasterTimeout : 1;
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UCHAR PendingFailSafeNmi : 1;
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}NMI_EXTENDED_CONTROL, *PNMI_EXTENDED_CONTROL;
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// Define 82357 register structure.
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typedef struct _EISA_CONTROL {
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union {
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DMA1_CONTROL Dma1BasePort; // Offset 0x00
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struct {
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UCHAR Interrupt1ControlPort0; // Offset 0x00
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UCHAR Reserved1;
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UCHAR Interrupt1ControlPort1; // Offset 0x02
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UCHAR Reserved2[5];
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UCHAR Interrupt2ControlPort0; // Offset 0x08
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UCHAR Reserved3;
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UCHAR Interrupt2ControlPort1; // Offset 0x0A
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UCHAR Reserved4[sizeof(DMA1_CONTROL)-11];
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};
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};
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union {
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DMA_PAGE DmaPageLowPort; // Offset 0x20
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DMA2_CONTROL Dma2BasePort; // Offset 0x20
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struct {
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UCHAR Reserved20[9]; // Offset 0x20
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UCHAR PageIncrementMode; // Offset 0x29
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UCHAR Reserved21;
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UCHAR InDirectAddress; // Offset 0x2b
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UCHAR Reserved22;
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UCHAR InDirectData; // Offset 0x2d
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UCHAR Reserved23[0x7f - 0x2e];
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UCHAR PageIncrementMode2; // Offset 0x7f
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UCHAR Reserved24[0x129 - 0x80];
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UCHAR DMA2PageIncrementMode; // Offset 0x129
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};
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};
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UCHAR Reserved25[0xfffc - 0x130]; // Offset 0x130
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// No NEC PC98 have 2nd DMA controller. But PC/AT has one. Therefore there are some valuable
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// refer to 2nd DMA in ixisasup.c.
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// I add it following valuable so that HAL builds. HAL of NEC PC98 doesn't use it.
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UCHAR Dma1ExtendedModePort;
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UCHAR Dma2ExtendedModePort;
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UCHAR DmaPageHighPort;
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UCHAR Interrupt1EdgeLevel;
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UCHAR Interrupt2EdgeLevel;
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} EISA_CONTROL, *PEISA_CONTROL;
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// Define initialization command word 1 structure.
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typedef struct _INITIALIZATION_COMMAND_1 {
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UCHAR Icw4Needed : 1;
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UCHAR CascadeMode : 1;
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UCHAR Unused1 : 2;
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UCHAR InitializationFlag : 1;
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UCHAR Unused2 : 3;
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}INITIALIZATION_COMMAND_1, *PINITIALIZATION_COMMAND_1;
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// Define initialization command word 4 structure.
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typedef struct _INITIALIZATION_COMMAND_4 {
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UCHAR I80x86Mode : 1;
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UCHAR AutoEndOfInterruptMode : 1;
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UCHAR Unused1 : 2;
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UCHAR SpecialFullyNested : 1;
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UCHAR Unused2 : 3;
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}INITIALIZATION_COMMAND_4, *PINITIALIZATION_COMMAND_4;
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// Define EISA interrupt controller operational command values.
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// Define operation control word 2 commands.
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#define NONSPECIFIC_END_OF_INTERRUPT 0x20
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#define SPECIFIC_END_OF_INTERRUPT 0x60
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// Define external EISA interupts
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#define EISA_EXTERNAL_INTERRUPTS_1 0xf8
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#define EISA_EXTERNAL_INTERRUPTS_2 0xbe
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// Define the DMA mode register structure.
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typedef struct _DMA_EISA_MODE {
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UCHAR Channel : 2;
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UCHAR TransferType : 2;
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UCHAR AutoInitialize : 1;
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UCHAR AddressDecrement : 1;
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UCHAR RequestMode : 2;
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}DMA_EISA_MODE, *PDMA_EISA_MODE;
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// Define TransferType values.
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#define VERIFY_TRANSFER 0x00
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#define READ_TRANSFER 0x01 // Read from the device.
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#define WRITE_TRANSFER 0x02 // Write to the device.
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// Define RequestMode values.
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#define DEMAND_REQUEST_MODE 0x00
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#define SINGLE_REQUEST_MODE 0x01
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#define BLOCK_REQUEST_MODE 0x02
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#define CASCADE_REQUEST_MODE 0x03
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// Define the DMA extended mode register structure.
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typedef struct _DMA_EXTENDED_MODE {
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UCHAR ChannelNumber : 2;
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UCHAR TransferSize : 2;
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UCHAR TimingMode : 2;
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UCHAR EndOfPacketInput : 1;
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UCHAR StopRegisterEnabled : 1;
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}DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
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// Define the DMA extended mode register transfer size values.
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#define BY_BYTE_8_BITS 0
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#define BY_WORD_16_BITS 1
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#define BY_BYTE_32_BITS 2
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#define BY_BYTE_16_BITS 3
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// Define the DMA extended mode timing mode values.
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#define COMPATIBLITY_TIMING 0
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#define TYPE_A_TIMING 1
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#define TYPE_B_TIMING 2
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#define BURST_TIMING 3
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#ifndef DMA1_COMMAND_STATUS
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// Define constants used by Intel 8237A DMA chip
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#define DMA_SETMASK 4
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#define DMA_CLEARMASK 0
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#define DMA_READ 4 // These two appear backwards, but I think
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#define DMA_WRITE 8 // the DMA docs have them mixed up
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#define DMA_SINGLE_TRANSFER 0x40
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#define DMA_AUTO_INIT 0x10 // Auto initialization mode
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#endif
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// This structure is drive layout and partition information
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// for NEC PC-98xx series.
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typedef struct _PARTITION_INFORMATION_NEC {
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UCHAR PartitionType;
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BOOLEAN RecognizedPartition;
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BOOLEAN RewritePartition;
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ULONG PartitionNumber;
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LARGE_INTEGER IplStartOffset;
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LARGE_INTEGER StartingOffset;
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LARGE_INTEGER PartitionLength;
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UCHAR BootableFlag;
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UCHAR PartitionName[16];
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} PARTITION_INFORMATION_NEC, *PPARTITION_INFORMATION_NEC;
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typedef struct _DRIVE_LAYOUT_INFORMATION_NEC {
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ULONG PartitionCount;
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ULONG Signature;
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UCHAR BootRecordNec[8];
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PARTITION_INFORMATION_NEC PartitionEntry[1];
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} DRIVE_LAYOUT_INFORMATION_NEC, *PDRIVE_LAYOUT_INFORMATION_NEC;
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// The system has memory over 16MB ?
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extern UCHAR Over16MBMemoryFlag;
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// We can't use DMA between 15MB and 16MB.
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#define NOTDMA_MINIMUM_PHYSICAL_ADDRESS 0x0f00000
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VOID
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FASTCALL
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xHalExamineMBR(
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IN PDEVICE_OBJECT DeviceObject,
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IN ULONG SectorSize,
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IN ULONG MBRTypeIdentifier,
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OUT PVOID *Buffer
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);
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VOID
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FASTCALL
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xHalIoAssignDriveLetters(
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IN struct _LOADER_PARAMETER_BLOCK *LoaderBlock,
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IN PSTRING NtDeviceName,
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OUT PUCHAR NtSystemPath,
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OUT PSTRING NtSystemPathString
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);
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NTSTATUS
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FASTCALL
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xHalIoReadPartitionTable(
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IN PDEVICE_OBJECT DeviceObject,
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IN ULONG SectorSize,
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IN BOOLEAN ReturnRecognizedPartitions,
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OUT struct _DRIVE_LAYOUT_INFORMATION **PartitionBuffer
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);
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NTSTATUS
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FASTCALL
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xHalIoSetPartitionInformation(
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IN PDEVICE_OBJECT DeviceObject,
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IN ULONG SectorSize,
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IN ULONG PartitionNumber,
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IN ULONG PartitionType
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);
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NTSTATUS
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FASTCALL
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xHalIoWritePartitionTable(
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IN PDEVICE_OBJECT DeviceObject,
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IN ULONG SectorSize,
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IN ULONG SectorsPerTrack,
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IN ULONG NumberOfHeads,
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IN struct _DRIVE_LAYOUT_INFORMATION *PartitionBuffer
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);
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#endif //_EISA_
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