925 lines
21 KiB
C
925 lines
21 KiB
C
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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alpmach.c
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Abstract:
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This file contains the ALPHA specific code for dealing with
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the process of stepping a single instruction. This includes
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determination of the next offset to be stopped at and if the
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instruction is all call type instruction.
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Author:
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Miche Baker-Harvey (miche) - stole the appropriate parts
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from ntsd for the alpha version.
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Environment:
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Win32 - User
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Notes:
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There are equivalent INTEL and MIPS files.
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--*/
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#include "precomp.h"
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#pragma hdrstop
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extern INT nVerbose;
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extern char rgchDebug[];
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extern LPDM_MSG LpDmMsg;
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extern CRITICAL_SECTION csContinueQueue;
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#define FALSE 0
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#define TRUE 1
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#define STATIC static
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ALPHA_INSTRUCTION disinstr;
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ULONG findTypeFromOpcode(ULONG);
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BOOL
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IsRet(
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HTHDX hthd,
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LPADDR addr
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)
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{
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DWORD instr;
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DWORD cBytes;
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if (!AddrReadMemory( hthd->hprc, hthd, addr, &instr, 4, &cBytes )) {
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return FALSE;
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}
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return (instr == 0x6bfa8001);
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}
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void
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IsCall (
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HTHDX hthd,
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LPADDR lpaddr,
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LPINT lpf,
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BOOL fStepOver
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)
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/*++
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Routine Description:
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IsCall
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Arguments:
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hthd - Supplies the handle to the thread
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lpaddr - Supplies the address to be check for a call instruction
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lpf - Returns class of instruction:
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INSTR_IS_CALL
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INSTR_BREAKPOINT
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INSTR_SOFT_INTERRUPT
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INSTR_TRACE_BIT
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fStepOver - Supplies step over vs step into flag
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Side Effects:
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The value of lpaddr is set to point to the returned-to
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instruction when the instruction is type INSTR_IS_CALL.
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Return Value:
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lpf - see Arguments.
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--*/
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{
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DWORD opcode;
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DWORD function;
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ADDR firaddr = *lpaddr;
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DWORD length;
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ALPHA_INSTRUCTION disinstr;
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BOOL r;
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if (hthd->fIsCallDone) {
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*lpaddr = hthd->addrIsCall;
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*lpf = hthd->iInstrIsCall;
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return;
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}
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/*
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* Assume that this is not a call instruction
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*/
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*lpf = INSTR_TRACE_BIT;
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/*
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* Read in the dword which contains the instruction under
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* inspection.
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*/
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r = AddrReadMemory(hthd->hprc,
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hthd,
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&firaddr,
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&disinstr.Long,
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sizeof(DWORD),
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&length );
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if (!r || length != sizeof(DWORD)) {
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DPRINT(1, ("AddrReadMemory in IsCall FAILED"));
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return;
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}
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/*
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* Assume that this is a jump instruction and get the opcode.
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* This is the top 6 bits of the instruction dword.
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*/
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opcode = disinstr.Jump.Opcode;
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/*
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* Jump and Branch to Subroutine are CALLs
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*/
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if (opcode == JMP_OP) {
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function = disinstr.Jump.Function;
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if (function == JSR_FUNC) {
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*lpf = INSTR_IS_CALL;
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}
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}
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if (opcode == BSR_OP) {
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*lpf = INSTR_IS_CALL;
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}
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/*
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* There are several PAL breakpoint operations,
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* and a couple operations redirect control
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*/
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if (opcode == CALLPAL_OP) {
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function = disinstr.Pal.Function;
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switch(function) {
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case (BPT_FUNC):
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case (CALLKD_FUNC):
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case (KBPT_FUNC):
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*lpf = INSTR_BREAKPOINT;
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break;
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case (CALLSYS_FUNC):
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case (GENTRAP_FUNC):
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*lpf = INSTR_IS_CALL;
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break;
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default:
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break;
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}
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}
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DPRINT(1, ("(IsCall?) FIR=%08I64x Type=%s\n", firaddr,
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*lpf==INSTR_IS_CALL ? "CALL":
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(*lpf==INSTR_BREAKPOINT ? "BREAKPOINT":
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(*lpf==INSTR_SOFT_INTERRUPT ? "INTERRUPT":
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"NORMAL"))));
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if (*lpf==INSTR_IS_CALL) {
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lpaddr->addr.off += sizeof (disinstr);
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hthd->addrIsCall = *lpaddr;
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}
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hthd->iInstrIsCall = *lpf;
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return;
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} /* IsCall() */
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#if 1
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ULONG64
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AlpGetNextOffset (
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HTHDX hthd,
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BOOL fStep
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)
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/*++
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Routine Description:
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From a limited disassembly of the instruction pointed
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by the FIR register, compute the offset of the next
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instruction for either a trace or step operation.
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trace -> the next instruction to execute
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step -> the instruction in the next memory location or the
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next instruction executed due to a branch (step
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over subroutine calls).
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Arguments:
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hthd - Supplies the handle to the thread to get the next offset for
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fStep - Supplies TRUE for STEP offset and FALSE for trace offset
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Returns:
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step or trace offset if input is TRUE or FALSE, respectively
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Version Information:
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This copy of GetNextOffset is from ntsd\alpha\ntdis.c@v16 (11/14/92)
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12-may-97 kentf modified to make LDx_L .. STx_C sequences atomic.
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--*/
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{
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ULONG64 returnvalue;
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ULONG opcode;
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ULONG64 updatedpc;
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ULONG64 branchTarget;
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BOOL r;
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int i;
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#define MAX_LOCKED_SEQUENCE 40
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LONGLONG Rav;
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LONGLONG Fav;
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ULONGLONG Rbv;
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DWORD length;
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PULONGLONG RegArray = &hthd->context.IntV0;
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ADDR firaddr;
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ALPHA_INSTRUCTION disinstr;
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AddrFromHthdx(&firaddr, hthd);
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// relative addressing updates PC first
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// Assume next sequential instruction is next offset
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updatedpc = firaddr.addr.off + sizeof(ULONG);
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r = AddrReadMemory(hthd->hprc,
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hthd,
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&firaddr,
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&disinstr.Long,
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sizeof(DWORD),
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&length );
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if (!r || length != sizeof(DWORD)) {
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DPRINT(1, ("GetNextOffset: failed AddrReadMemory %08I64x\n", firaddr.addr.off));
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assert(FALSE);
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return 4;
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}
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opcode = disinstr.Memory.Opcode;
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returnvalue = updatedpc;
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switch(findTypeFromOpcode(opcode)) {
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case ALPHA_CALLPAL:
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if (disinstr.Pal.Function == CALLSYS_FUNC) {
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return RegArray[RA_REG];
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}
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break;
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case ALPHA_JUMP:
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switch(disinstr.Jump.Function) {
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case JSR_FUNC:
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case JSR_CO_FUNC:
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if (fStep) {
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// Step over the subroutine call;
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return returnvalue;
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}
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// fall through
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case JMP_FUNC:
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case RET_FUNC:
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Rbv = RegArray[disinstr.Memory.Rb];
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return (Rbv & (~3));
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break;
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}
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break;
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case ALPHA_BRANCH:
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branchTarget = (updatedpc + (disinstr.Branch.BranchDisp * 4));
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Rav = (LONGLONG)RegArray[disinstr.Memory.Ra];
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DPRINT(1, ("Rav %08I64x returnValue %08I64x branchTarget %08I64x\n",
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Rav, returnvalue, branchTarget));
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switch(opcode) {
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case BR_OP: return(branchTarget); break;
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case BSR_OP: if (!fStep) return(branchTarget); break;
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case BEQ_OP: if (Rav == 0) return(branchTarget); break;
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case BLT_OP: if (Rav < 0) return(branchTarget); break;
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case BLE_OP: if (Rav <= 0) return(branchTarget); break;
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case BNE_OP: if (Rav != 0) return(branchTarget); break;
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case BGE_OP: if (Rav >= 0) return(branchTarget); break;
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case BGT_OP: if (Rav > 0) return(branchTarget); break;
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case BLBC_OP: if ((Rav & 0x1) == 0) return(branchTarget); break;
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case BLBS_OP: if ((Rav & 0x1) == 1) return(branchTarget); break;
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};
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return returnvalue;
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break;
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case ALPHA_FP_BRANCH:
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branchTarget = (updatedpc + (disinstr.Branch.BranchDisp * 4));
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RegArray = &hthd->context.FltF0;
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Fav = (LONGLONG)RegArray[disinstr.Branch.Ra];
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if (Fav == 0x8000000000000000) {
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Fav = 0;
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}
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DPRINT(1, ("Fav %08I64x returnValue %08I64x branchTarget %08I64x\n",
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Fav, returnvalue, branchTarget));
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switch(opcode) {
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case FBEQ_OP: if (Fav == 0) return (branchTarget); break;
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case FBLT_OP: if (Fav < 0) return (branchTarget); break;
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case FBNE_OP: if (Fav != 0) return (branchTarget); break;
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case FBLE_OP: if (Fav <= 0) return (branchTarget); break;
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case FBGE_OP: if (Fav >= 0) return (branchTarget); break;
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case FBGT_OP: if (Fav > 0) return (branchTarget); break;
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};
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return returnvalue;
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break;
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case ALPHA_MEMORY:
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if (opcode == LDL_L_OP || opcode == LDQ_L_OP) {
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// BUGBUG kentf This is not good enough. It will fail if a branch is
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// BUGBUG kentf taken before the STx_C.
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firaddr.addr.off = updatedpc;
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for (i = 0; i < MAX_LOCKED_SEQUENCE; i++) {
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r = AddrReadMemory(hthd->hprc,
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hthd,
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&firaddr,
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&disinstr.Long,
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sizeof(DWORD),
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&length );
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if (!r || length != sizeof(DWORD)) {
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DPRINT(1, ("GetNextOffset: failed AddrReadMemory %08I64x\n", firaddr.addr.off));
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assert(FALSE);
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return 4;
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}
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opcode = disinstr.Memory.Opcode;
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if (opcode == STL_C_OP || opcode == STQ_C_OP) {
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return firaddr.addr.off + sizeof(ULONG);
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}
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firaddr.addr.off += sizeof(ULONG);
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}
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DPRINT(1, ("GetNextOffset: did not find STx_C for LDx_L at %08I64x\n", updatedpc-4));
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}
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break;
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}
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return returnvalue;
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}
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#endif // 1
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XOSD
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SetupFunctionCall(
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LPEXECUTE_OBJECT_DM lpeo,
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LPEXECUTE_STRUCT lpes
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)
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{
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/*
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* Can only execute functions on the current stopped thread. Therefore
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* assert that the current thread is stopped.
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*/
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assert(lpeo->hthd->tstate & ts_stopped);
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if (!(lpeo->hthd->tstate & ts_stopped)) {
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return xosdBadThread;
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}
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/*
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* Now get the current stack offset.
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*/
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lpeo->addrStack.addr.off = lpeo->hthd->context.IntSp;
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/*
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* Now place the return address correctly
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*/
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lpeo->hthd->context.Fir = lpeo->hthd->context.IntRa =
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lpeo->addrStart.addr.off;
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/*
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* Set the instruction pointer to the starting addresses
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* and write the context back out
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*/
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lpeo->hthd->context.Fir = lpeo->addrStart.addr.off;
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lpeo->hthd->fContextDirty = TRUE;
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return xosdNone;
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}
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BOOL
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CompareStacks(
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LPEXECUTE_OBJECT_DM lpeo
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)
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/*++
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Routine Description:
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This routine is used to determine if the stack pointers are correct
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for terminating function evaluation.
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Arguments:
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lpeo - Supplies the pointer to the DM Execute Object description
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Return Value:
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TRUE if the evaluation is to be terminated and FALSE otherwise
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--*/
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{
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if (lpeo->addrStack.addr.off <= lpeo->hthd->context.IntSp) {
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return TRUE;
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}
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return FALSE;
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} /* CompareStacks() */
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BOOL
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ProcessFrameStackWalkNextCmd(
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HPRCX hprc,
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HTHDX hthd,
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PCONTEXT context,
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LPVOID pctxPtrs
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)
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{
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return FALSE;
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} // ProcessFrameStackWalkNextCmd
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#if 0
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#if DBG
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ULONG RtlDebugFlags = 0;
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#define RTL_DBG_VIRTUAL_UNWIND 1
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#define RTL_DBG_VIRTUAL_UNWIND_DETAIL 2
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// Define an array of symbolic names for the integer registers.
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PCHAR RtlpIntegerRegisterNames[32] = {
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"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", // 0 - 7
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"t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", // 8 - 15
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"a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", // 16 - 23
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"t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", // 24 - 31
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};
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// This function disassembles the instruction at the given address. It is
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// only used for debugging and recognizes only those few instructions that
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// are relevant during reverse execution of the prologue by virtual unwind.
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VOID
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_RtlpDebugDisassemble (
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IN ULONG64 ControlPc,
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IN PCONTEXT ContextRecord
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)
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{
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UCHAR Comments[50];
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PULONGLONG FloatingRegister;
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ULONG Function;
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ULONG Hint;
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ULONG Literal8;
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ALPHA_INSTRUCTION Instruction;
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PULONGLONG IntegerRegister;
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LONG Offset16;
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UCHAR Operands[20];
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ULONG Opcode;
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PCHAR OpName;
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ULONG Ra;
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ULONG Rb;
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ULONG Rc;
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PCHAR RaName;
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PCHAR RbName;
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PCHAR RcName;
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if (RtlDebugFlags & RTL_DBG_VIRTUAL_UNWIND_DETAIL) {
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Instruction.Long = *((PULONG)ControlPc);
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Hint = Instruction.Jump.Hint;
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Literal8 = Instruction.OpLit.Literal;
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Offset16 = Instruction.Memory.MemDisp;
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Opcode = Instruction.Memory.Opcode;
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Ra = Instruction.OpReg.Ra;
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RaName = RtlpIntegerRegisterNames[Ra];
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Rb = Instruction.OpReg.Rb;
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RbName = RtlpIntegerRegisterNames[Rb];
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Rc = Instruction.OpReg.Rc;
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RcName = RtlpIntegerRegisterNames[Rc];
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IntegerRegister = &ContextRecord->IntV0;
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FloatingRegister = &ContextRecord->FltF0;
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OpName = NULL;
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switch (Opcode) {
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case JMP_OP :
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if (Instruction.Jump.Function == RET_FUNC) {
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OpName = "ret";
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sprintf(Operands, "%s, (%s), %04lx", RaName, RbName, Hint);
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sprintf(Comments, "%s = %I64x", RbName, IntegerRegister[Rb]);
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}
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break;
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case LDAH_OP :
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case LDA_OP :
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case STQ_OP :
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if (Opcode == LDA_OP) {
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OpName = "lda";
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} else if (Opcode == LDAH_OP) {
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OpName = "ldah";
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} else if (Opcode == STQ_OP) {
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OpName = "stq";
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}
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sprintf(Operands, "%s, $%d(%s)", RaName, Offset16, RbName);
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sprintf(Comments, "%s = %I64x", RaName, IntegerRegister[Ra]);
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break;
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case ARITH_OP :
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case BIT_OP :
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Function = Instruction.OpReg.Function;
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if ((Opcode == ARITH_OP) && (Function == ADDQ_FUNC)) {
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OpName = "addq";
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} else if ((Opcode == ARITH_OP) && (Function == SUBQ_FUNC)) {
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OpName = "subq";
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} else if ((Opcode == BIT_OP) && (Function == BIS_FUNC)) {
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OpName = "bis";
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} else {
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break;
|
|
}
|
|
if (Instruction.OpReg.RbvType == RBV_REGISTER_FORMAT) {
|
|
sprintf(Operands, "%s, %s, %s", RaName, RbName, RcName);
|
|
|
|
} else {
|
|
sprintf(Operands, "%s, $%d, %s", RaName, Literal8, RcName);
|
|
}
|
|
sprintf(Comments, "%s = %I64x", RcName, IntegerRegister[Rc]);
|
|
break;
|
|
|
|
case FPOP_OP :
|
|
if (Instruction.FpOp.Function == CPYS_FUNC) {
|
|
OpName = "cpys";
|
|
sprintf(Operands, "f%d, f%d, f%d", Ra, Rb, Rc);
|
|
sprintf(Comments, "f%d = %I64x", Rc, FloatingRegister[Rc]);
|
|
}
|
|
break;
|
|
|
|
case STT_OP :
|
|
OpName = "stt";
|
|
sprintf(Operands, "f%d, $%d(%s)", Ra, Offset16, RbName);
|
|
sprintf(Comments, "f%d = %I64x", Ra, FloatingRegister[Ra]);
|
|
break;
|
|
}
|
|
if (OpName == NULL) {
|
|
OpName = "???";
|
|
sprintf(Operands, "...");
|
|
sprintf(Comments, "Unknown to virtual unwind.");
|
|
}
|
|
DEBUG_PRINT_5(" %08I64x: %08lx %-5s %-16s // %s\n",
|
|
ControlPc, Instruction.Long, OpName, Operands, Comments);
|
|
}
|
|
return;
|
|
}
|
|
|
|
#define _RtlpFoundTrapFrame(NextPc) \
|
|
if (RtlDebugFlags & RTL_DBG_VIRTUAL_UNWIND) { \
|
|
DEBUG_PRINT_1(" *** Looks like a trap frame (fake prologue), Fir = %I64x\n", \
|
|
NextPc); \
|
|
}
|
|
|
|
#else
|
|
|
|
#define _RtlpDebugDisassemble(ControlPc, ContextRecord)
|
|
#define _RtlpFoundTrapFrame(NextPc)
|
|
|
|
#endif
|
|
|
|
|
|
// MBH - this value is redefined in windbg common code to be IntSp.
|
|
|
|
#define SP_REG 30
|
|
|
|
|
|
DWORD
|
|
BranchUnassemble(
|
|
void *Memory,
|
|
ADDR *Addr,
|
|
BOOL *IsBranch,
|
|
BOOL *TargetKnown,
|
|
BOOL *IsCall,
|
|
BOOL *IsTable,
|
|
ADDR *Target
|
|
)
|
|
{
|
|
ULONG OpCode;
|
|
ALPHA_INSTRUCTION *Instr;
|
|
UOFFSET TargetOffset;
|
|
|
|
UNREFERENCED_PARAMETER( Addr );
|
|
|
|
assert( Memory );
|
|
assert( IsBranch );
|
|
assert( TargetKnown );
|
|
assert( IsCall );
|
|
assert( Target );
|
|
|
|
*IsBranch = FALSE;
|
|
*IsTable = FALSE;
|
|
|
|
TargetOffset = 0;
|
|
Instr = (ALPHA_INSTRUCTION *)Memory;
|
|
OpCode = Instr->Jump.Opcode;
|
|
|
|
switch ( OpCode ) {
|
|
|
|
case JMP_OP:
|
|
switch ( Instr->Jump.Function ) {
|
|
|
|
case JMP_FUNC:
|
|
case RET_FUNC:
|
|
*IsBranch = TRUE;
|
|
*IsCall = FALSE;
|
|
*TargetKnown = FALSE;
|
|
break;
|
|
|
|
case JSR_FUNC:
|
|
case JSR_CO_FUNC:
|
|
*IsBranch = TRUE;
|
|
*IsCall = TRUE;
|
|
*TargetKnown = FALSE;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case CALLPAL_OP:
|
|
switch( Instr->Pal.Function ) {
|
|
case CALLSYS_FUNC:
|
|
case GENTRAP_FUNC:
|
|
*IsBranch = TRUE;
|
|
*IsCall = TRUE;
|
|
*TargetKnown = FALSE;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case BSR_OP:
|
|
*IsBranch = TRUE;
|
|
*IsCall = TRUE;
|
|
*TargetKnown = TRUE;
|
|
TargetOffset = (GetAddrOff(*Addr) + 4) + (Instr->Branch.BranchDisp << 2);
|
|
break;
|
|
|
|
case BR_OP:
|
|
case FBEQ_OP:
|
|
case FBLT_OP:
|
|
case FBLE_OP:
|
|
case FBNE_OP:
|
|
case FBGE_OP:
|
|
case FBGT_OP:
|
|
case BLBC_OP:
|
|
case BEQ_OP:
|
|
case BLT_OP:
|
|
case BLE_OP:
|
|
case BLBS_OP:
|
|
case BNE_OP:
|
|
case BGE_OP:
|
|
case BGT_OP:
|
|
*IsBranch = TRUE;
|
|
*IsCall = FALSE;
|
|
*TargetKnown = TRUE;
|
|
TargetOffset = (GetAddrOff(*Addr) + 4) + (Instr->Branch.BranchDisp << 2);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
AddrInit( Target, 0, 0, TargetOffset, TRUE, TRUE, FALSE, FALSE );
|
|
|
|
return sizeof( DWORD );
|
|
}
|
|
|
|
#endif // If 0
|
|
|
|
#ifndef KERNEL
|
|
|
|
UOFFSET
|
|
GetSPFromNLGDest(
|
|
HTHDX hthd,
|
|
LPNLG_DESTINATION pNlgDest
|
|
)
|
|
{
|
|
UOFFSET dwRet;
|
|
|
|
switch (pNlgDest->dwCode) {
|
|
case NLG_CATCH_ENTER: // Catch handler
|
|
case NLG_EXCEPT_ENTER: // Exception handler
|
|
case NLG_FILTER_ENTER: // Exception filter
|
|
case NLG_CATCH_LEAVE: // Return from Catch
|
|
case NLG_FINALLY_ENTER: // Termination handlers
|
|
case NLG_DESTRUCTOR_ENTER: // -GX handler
|
|
case NLG_LONGJMPEX: // Exception safe longjmp
|
|
dwRet = pNlgDest->uoffFramePointer;
|
|
break;
|
|
|
|
case NLG_LONGJMP:
|
|
dwRet = pNlgDest->uoffFramePointer+1;
|
|
break;
|
|
|
|
default:
|
|
dwRet = STACK_POINTER(hthd)+1; // emulate Virtual FP?
|
|
break;
|
|
}
|
|
|
|
return dwRet;
|
|
}
|
|
|
|
PVOID
|
|
InfoExceptionDuringStep(
|
|
HTHDX hthd
|
|
)
|
|
{
|
|
Unreferenced(hthd);
|
|
|
|
// Information that needs to be propagated from the step location
|
|
// to the action handler when an exception occurs is passed in the
|
|
// void * returned by this function. In case of Alpha no information
|
|
// needs to be passed currently.
|
|
return NULL;
|
|
}
|
|
|
|
|
|
|
|
DWORDLONG
|
|
GetFunctionResult(
|
|
PCALLSTRUCT pcs
|
|
)
|
|
{
|
|
return pcs->context.IntV0;
|
|
}
|
|
|
|
|
|
VOID
|
|
vCallFunctionHelper(
|
|
HTHDX hthd,
|
|
DWORD64 lpFunction,
|
|
int cArgs,
|
|
va_list vargs
|
|
)
|
|
{
|
|
int i;
|
|
|
|
assert(Is64PtrSE(lpFunction));
|
|
|
|
for (i = 0; i < cArgs; i++) {
|
|
(&hthd->context.IntA0)[i] = va_arg(vargs, DWORD);
|
|
}
|
|
|
|
hthd->context.IntRa = PC(hthd);
|
|
Set_PC(hthd, lpFunction);
|
|
hthd->fContextDirty = TRUE;
|
|
}
|
|
|
|
BOOL
|
|
GetWndProcMessage(
|
|
HTHDX hthd,
|
|
UINT* pmsg
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is used to get the current Windows message (WM_CREATE, etc)
|
|
when execution has been stopped at a wndproc.
|
|
|
|
Return Value:
|
|
|
|
False on failure; True otherwise.
|
|
|
|
--*/
|
|
{
|
|
*pmsg = (UINT)hthd->context.IntA1;
|
|
return TRUE;
|
|
}
|
|
|
|
#endif // !KERNEL
|
|
|
|
BOOL
|
|
DecodeSingleStepEvent(
|
|
HTHDX hthd,
|
|
DEBUG_EVENT64 *de,
|
|
PDWORD eventCode,
|
|
PDWORD_PTR subClass
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
|
|
Arguments:
|
|
|
|
hthd - Supplies thread that has a single step exception pending
|
|
|
|
de - Supplies the DEBUG_EVENT64 structure for the exception
|
|
|
|
eventCode - Returns the remapped debug event id
|
|
|
|
subClass - Returns the remapped subClass id
|
|
|
|
|
|
Return Value:
|
|
|
|
TRUE if event was a real single step or was successfully mapped
|
|
to a breakpoint. FALSE if a register breakpoint occurred which was
|
|
not expected.
|
|
|
|
--*/
|
|
{
|
|
return FALSE;
|
|
}
|
|
|
|
ULONGLONG
|
|
GetRegValue(
|
|
PCONTEXT regs,
|
|
int cvindex
|
|
)
|
|
{
|
|
if (cvindex < CV_ALPHA_IntV0+32) {
|
|
return (®s->IntV0)[cvindex - CV_ALPHA_IntV0];
|
|
}
|
|
|
|
switch (cvindex) {
|
|
|
|
case CV_ALPHA_Fir:
|
|
return regs->Fir;
|
|
|
|
case CV_ALPHA_Psr:
|
|
return regs->Psr;
|
|
|
|
default:
|
|
assert(!"GetRegValue called with unrecognized index");
|
|
return (ULONGLONG)0 - 1;
|
|
}
|
|
}
|