72 lines
5.3 KiB
C
72 lines
5.3 KiB
C
{ SzAH, rtCPU | rtInvisible | rtInteger, 8, 0, iregAH },
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{ SzAL, rtCPU | rtInvisible | rtInteger, 8, 0, iregAL },
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{ SzAX, rtCPU | rtRegular | rtInteger, 16, 0, iregAX },
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{ SzEAX, rtCPU | rtExtended | rtInteger, 32, 0, iregEAX },
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{ SzBH, rtCPU | rtInvisible | rtInteger, 8, 0, iregBH },
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{ SzBL, rtCPU | rtInvisible | rtInteger, 8, 0, iregBL },
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{ SzBX, rtCPU | rtRegular | rtInteger, 16, 0, iregBX },
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{ SzEBX, rtCPU | rtExtended | rtInteger, 32, 0, iregEBX },
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{ SzCH, rtCPU | rtInvisible | rtInteger, 8, 0, iregCH },
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{ SzCL, rtCPU | rtInvisible | rtInteger, 8, 0, iregCL },
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{ SzCX, rtCPU | rtRegular | rtInteger, 16, 0, iregCX },
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{ SzECX, rtCPU | rtExtended | rtInteger, 32, 0, iregECX },
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{ SzDH, rtCPU | rtInvisible | rtInteger, 8, 0, iregDH },
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{ SzDL, rtCPU | rtInvisible | rtInteger, 8, 0, iregDL },
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{ SzDX, rtCPU | rtRegular | rtInteger, 16, 0, iregDX },
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{ SzEDX, rtCPU | rtExtended | rtInteger, 32, 0, iregEDX },
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{ SzSI, rtCPU | rtRegular | rtInteger, 16, 0, iregSI },
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{ SzESI, rtCPU | rtExtended | rtInteger, 32, 0, iregESI },
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{ SzDI, rtCPU | rtRegular | rtInteger, 16, 0, iregDI },
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{ SzEDI, rtCPU | rtExtended | rtInteger, 32, 0, iregEDI },
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{ SzIP, rtCPU | rtRegular | rtInteger | rtPC | rtNewLine, 16, 0, iregIP },
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{ SzEIP, rtCPU | rtExtended | rtInteger | rtPC | rtNewLine, 32, 0, iregEIP },
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{ SzSP, rtCPU | rtRegular | rtInteger | rtFrame, 16, 0, iregSP },
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{ SzESP, rtCPU | rtExtended | rtInteger | rtFrame, 32, 0, iregESP },
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{ SzBP, rtCPU | rtRegular | rtInteger | rtFrame, 16, 0, iregBP },
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{ SzEBP, rtCPU | rtExtended | rtInteger | rtFrame, 32, 0, iregEBP },
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{ SzFlags, rtCPU | rtRegular | rtInteger, 16, 0, iregFLAGS },
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{ SzEFlags, rtCPU | rtExtended | rtInteger, 32, 0, iregEFLAGS },
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{ SzCS, rtCPU | rtExtended | rtRegular | rtInteger | rtPC | rtNewLine, 16, 0, iregCS },
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{ SzDS, rtCPU | rtExtended | rtRegular | rtInteger, 16, 0, iregDS },
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{ SzES, rtCPU | rtExtended | rtRegular | rtInteger, 16, 0, iregES },
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{ SzSS, rtCPU | rtExtended | rtRegular | rtInteger | rtFrame, 16, 0, iregSS },
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{ SzFS, rtCPU | rtExtended | rtRegular | rtInteger, 16, 0, iregFS },
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{ SzGS, rtCPU | rtExtended | rtRegular | rtInteger, 16, 0, iregGS },
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{ SzCr0, rtCPU | rtSpecial | rtKmode | rtInteger | rtNewLine, 32, 0, CV_REG_CR0 },
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{ SzCr2, rtCPU | rtSpecial | rtKmode | rtInteger, 32, 0, CV_REG_CR2 },
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{ SzCr3, rtCPU | rtSpecial | rtKmode | rtInteger, 32, 0, CV_REG_CR3 },
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{ SzCr4, rtCPU | rtSpecial | rtKmode | rtInteger, 32, 0, CV_REG_CR4 },
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{ SzDr0, rtCPU | rtSpecial | rtInteger | rtNewLine, 32, 0, CV_REG_DR0 },
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{ SzDr1, rtCPU | rtSpecial | rtInteger, 32, 0, CV_REG_DR1 },
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{ SzDr2, rtCPU | rtSpecial | rtInteger, 32, 0, CV_REG_DR2 },
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{ SzDr3, rtCPU | rtSpecial | rtInteger, 32, 0, CV_REG_DR3 },
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{ SzDr6, rtCPU | rtSpecial | rtInteger, 32, 0, CV_REG_DR6 },
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{ SzDr7, rtCPU | rtSpecial | rtInteger, 32, 0, CV_REG_DR7 },
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{ SzGdtr, rtCPU | rtSpecial | rtKmode | rtInteger | rtNewLine, 32, 0, CV_REG_GDTR },
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{ SzGdtl, rtCPU | rtSpecial | rtKmode | rtInteger, 16, 0, CV_REG_GDTL },
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{ SzIdtr, rtCPU | rtSpecial | rtKmode | rtInteger, 32, 0, CV_REG_IDTR },
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{ SzIdtl, rtCPU | rtSpecial | rtKmode | rtInteger, 16, 0, CV_REG_IDTL },
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{ SzTr, rtCPU | rtSpecial | rtKmode | rtInteger, 16, 0, CV_REG_TR },
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{ SzLdtr, rtCPU | rtSpecial | rtKmode | rtInteger, 16, 0, CV_REG_LDTR },
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{ SzST0, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST0 },
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{ SzST1, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST1 },
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{ SzST2, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST2 },
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{ SzST3, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST3 },
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{ SzST4, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST4 },
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{ SzST5, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST5 },
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{ SzST6, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST6 },
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{ SzST7, rtFPU | rtRegular | rtExtended | rtFloat, 80, 0, iregST7 },
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{ SzCtrl, rtFPU | rtRegular | rtExtended | rtInteger | rtNewLine, 16, 0, iregCTRL },
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{ SzStat, rtFPU | rtRegular | rtExtended | rtInteger, 16, 0, iregSTAT },
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{ SzTag, rtFPU | rtRegular | rtExtended | rtInteger, 16, 0, iregTAG },
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{ SzFpIp, rtFPU | rtRegular | rtInteger, 16, 0, iregFPIP },
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{ SzFpEip, rtFPU | rtExtended | rtInteger, 32, 0, CV_REG_FPEIP },
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{ SzFpCs, rtFPU | rtRegular | rtExtended | rtInteger | rtNewLine, 16, 0, iregFPCS },
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{ SzFpDs, rtFPU | rtRegular | rtExtended | rtInteger, 16, 0, iregFPDS },
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{ SzFpEdo, rtFPU | rtExtended | rtInteger, 32, 0, CV_REG_FPEDO },
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{ SzFpDo, rtFPU | rtRegular | rtInteger, 16, 0, iregFPDO }
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