887 lines
19 KiB
C++
887 lines
19 KiB
C++
/*
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* Microsoft Disassembler
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*
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* Microsoft Confidential. Copyright 1994-1997 Microsoft Corporation.
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*
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* Component:
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*
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* File: dismips16.h
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*
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* File Comments:
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*
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* This file is a copy of the master version owned by richards.
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* Contact richards for any changes.
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*
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***********************************************************************/
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#pragma pack(push, 8)
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class DISMIPS16 : public DIS
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{
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public:
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enum TRMTA
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{
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trmtaUnknown = DIS::trmtaUnknown,
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trmtaFallThrough = DIS::trmtaFallThrough,
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trmtaTrap,
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trmtaBra,
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trmtaBraCc,
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trmtaBraIndDef,
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trmtaCallDef,
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trmtaCallIndDef,
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};
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enum REGA
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{
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regaR0 = 0,
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regaR1 = 1,
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regaR2 = 2,
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regaR3 = 3,
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regaR4 = 4,
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regaR5 = 5,
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regaR6 = 6,
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regaR7 = 7,
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regaR8 = 8,
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regaR9 = 9,
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regaR10 = 10,
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regaR11 = 11,
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regaR12 = 12,
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regaR13 = 13,
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regaR14 = 14,
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regaR15 = 15,
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regaR16 = 16,
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regaR17 = 17,
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regaR18 = 18,
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regaR19 = 19,
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regaR20 = 20,
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regaR21 = 21,
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regaR22 = 22,
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regaR23 = 23,
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regaR24 = 24,
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regaR25 = 25,
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regaR26 = 26,
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regaR27 = 27,
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regaR28 = 28,
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regaR29 = 29,
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regaR30 = 30,
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regaR31 = 31,
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regaZero = 0,
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regaAt = 1,
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regaV0 = 2,
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regaV1 = 3,
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regaA0 = 4,
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regaA1 = 5,
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regaA2 = 6,
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regaA3 = 7,
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regaT0 = 8,
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regaT1 = 9,
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regaT2 = 10,
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regaT3 = 11,
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regaT4 = 12,
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regaT5 = 13,
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regaT6 = 14,
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regaT7 = 15,
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regaS0 = 16,
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regaS1 = 17,
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regaS2 = 18,
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regaS3 = 19,
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regaS4 = 20,
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regaS5 = 21,
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regaS6 = 22,
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regaS7 = 23,
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regaT8 = 24,
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regaT9 = 25,
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regaK0 = 26,
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regaK1 = 27,
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regaGp = 28,
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regaSp = 29,
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regaS8 = 30,
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regaRa = 31,
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regaPc = 32,
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};
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DISDLL DISMIPS16(DIST);
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// Methods inherited from DIS
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ADDR AddrOperand(size_t) const;
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ADDR AddrTarget() const;
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size_t Cb() const;
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size_t CbDisassemble(ADDR, const void *, size_t);
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size_t CbJumpEntry() const;
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size_t CbOperand(size_t) const;
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size_t CchFormatBytes(char *, size_t) const;
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size_t CchFormatBytesMax() const;
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size_t Coperand() const;
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void FormatAddr(std::ostream&, ADDR) const;
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void FormatInstr(std::ostream&) const;
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MEMREFT Memreft(size_t) const;
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TRMT Trmt() const;
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DIS::TRMTA Trmta() const;
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private:
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union IW // Instruction Word
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{
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WORD w;
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struct
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{
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WORD Immediate : 11;
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WORD Opcode : 5;
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} i_format;
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struct
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{
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WORD Immediate : 8;
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WORD Rx : 3;
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WORD Opcode : 5;
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} ri_format;
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struct
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{
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WORD Func : 5;
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WORD Ry : 3;
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WORD Rx : 3;
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WORD Opcode : 5;
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} rr_format;
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struct
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{
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WORD Immediate : 5;
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WORD Ry : 3;
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WORD Rx : 3;
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WORD Opcode : 5;
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} rri_format;
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struct
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{
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WORD Func : 2;
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WORD Rz : 3;
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WORD Ry : 3;
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WORD Rx : 3;
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WORD Opcode : 5;
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} rrr_format;
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struct
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{
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WORD Immediate : 4;
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WORD Func : 1;
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WORD Ry : 3;
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WORD Rx : 3;
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WORD Opcode : 5;
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} rria_format;
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struct
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{
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WORD Func : 2;
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WORD Shift : 3;
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WORD Ry : 3;
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WORD Rx : 3;
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WORD Opcode : 5;
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} shift_format;
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struct
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{
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WORD Immediate : 8;
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WORD Func : 3;
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WORD Opcode : 5;
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} i8_format;
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struct
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{
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WORD R32 : 5;
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WORD Ry : 3;
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WORD Func : 3;
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WORD Opcode : 5;
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} mover32_format;
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struct
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{
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WORD Rw : 3;
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WORD R323 : 2; // mangled
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WORD R320 : 3;
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WORD Func : 3;
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WORD Opcode : 5;
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} move32r_format;
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struct
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{
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WORD Immediate : 8;
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WORD Func : 3;
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WORD Opcode : 5;
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} i64_format;
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struct
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{
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WORD Immediate : 5;
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WORD Ry : 3;
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WORD Func : 3;
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WORD Opcode : 5;
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} ri64_format;
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struct
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{
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WORD Target21 : 5;
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WORD Target16 : 5;
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WORD Ext : 1;
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WORD Opcode : 5;
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} j_format;
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struct
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{
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WORD Func : 5;
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WORD Ry : 3;
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WORD Shift : 3;
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WORD Opcode : 5;
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} shift64_format;
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struct
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{
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WORD Zero1 : 5;
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WORD Func : 3;
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WORD Rx : 3;
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WORD Opcode : 5;
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} jr_format;
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struct
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{
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WORD Break : 5;
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WORD Code : 6;
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WORD Opcode : 5;
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} break_format;
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};
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union EW // Extend word
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{
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WORD w;
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struct
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{
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WORD Immediate11 : 5;
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WORD Immediate5 : 6;
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WORD Opcode : 5;
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} ei_format;
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struct
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{
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WORD Immediate11 : 4;
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WORD Immediate4 : 7;
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WORD Opcode : 5;
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} erria_format;
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struct
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{
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WORD Zero : 5;
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WORD Shift5 : 1;
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WORD Shift0 : 5;
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WORD Opcode : 5;
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} eshift_format;
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};
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enum OPCLS // Operand Class
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{
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opclsNone, // No operand
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opclsSp, // SP register
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opclsPc, // PC register
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opclsRa, // RA register
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opclsRx, // MIPS16 general register Rx
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opclsRy, // MIPS16 general register Ry
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opclsRz, // MIPS16 general register Rz
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opclsRw, // MIPS16 general register Rw
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opclsMemRxB_r, // Memory Rx with 5bit byte offset (read)
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opclsMemRxH_r, // Memory Rx with 5bit halfword offset (read)
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opclsMemRxW_r, // Memory Rx with 5bit word offset (read)
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opclsMemRxD_r, // Memory Rx with 5bit dword offset (read)
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opclsMemPcW_r, // Memory PC with 8bit word offset (read)
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opclsMemPcD_r, // Memory PC with 5bit dword offset (read)
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opclsMemSpW_r, // Memory SP with 8bit word offset (read)
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opclsMemSpD5_r, // Memory SP with 5bit dword offset (read)
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opclsMemSpD8_r, // Memory SP with 8bit dword offset (read)
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opclsMemRxB_w, // Memory Rx with 5bit byte offset (write)
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opclsMemRxH_w, // Memory Rx with 5bit halfword offset (write)
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opclsMemRxW_w, // Memory Rx with 5bit word offset (write)
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opclsMemRxD_w, // Memory Rx with 5bit dword offset (write)
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opclsMemSpW_w, // Memory SP with 8bit word offset (write)
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opclsMemSpD5_w, // Memory SP with 5bit dword offset (write)
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opclsMemSpD8_w, // Memory SP with 8bit dword offset (write)
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opclsImmSB4, // Signed 4bit byte immediate
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opclsImmSB5, // Signed 5bit byte immediate
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opclsImmSB8, // Signed 8bit byte immediate
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opclsImmSD8, // Signed 8bit dword immediate
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opclsImmUB8, // Unsigned 8bit byte immediate
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opclsImmUB8U, // Unsigned 8bit byte immediate (unsigned even on extend)
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opclsImmUW5, // Unsigned 5bit word immediate
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opclsImmUW8, // Unsigned 8bit word immediate
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opclsShift0, // Shift amount type 0
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opclsShift1, // Shift amount type 1
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opclsShift2, // Shift amount type 2
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opclsR32Src, // MIPS32 general register source
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opclsR32Dst, // MIPS32 general register destination
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opclsAddrJmp, // Jump instruction target
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opclsAddrBraC, // Conditional branch instruction target
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opclsAddrBraU, // Unconditional branch instruction target
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opclsBrkImm, // Immediate value for break instruction
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};
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enum ICLS // Instruction Class
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{
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// Invalid Class
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iclsInvalid,
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// Rx-offset Load Byte Class
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// Text Format: LB ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Ry
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iclsRxLoadByte,
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// Rx-offset Load Halfword Class
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// Text Format: LH ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Ry
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iclsRxLoadHalfword,
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// Rx-offset Load Word Class
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// Text Format: LW ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Ry
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iclsRxLoadWord,
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// PC-offset Load Word Class
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// Text Format: LW rx,offset(pc)
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// Termination Type: trmtaFallThrough
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// Registers Used: PC
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// Registers Set: Rx
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iclsPcLoadWord,
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// SP-offset Load Word Class
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// Text Format: LW rx,offset(sp)
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// Termination Type: trmtaFallThrough
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// Registers Used: SP
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// Registers Set: Rx
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iclsSpLoadWord,
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// Rx-offset Load DWord Class
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// Text Format: LD ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Ry
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iclsRxLoadDword,
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// PC-offset Load DWord Class
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// Text Format: LD ry,offset(pc)
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// Termination Type: trmtaFallThrough
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// Registers Used: PC
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// Registers Set: Ry
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iclsPcLoadDword,
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// SP-offset Load DWord Class
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// Text Format: LD ry,offset(sp)
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// Termination Type: trmtaFallThrough
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// Registers Used: SP
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// Registers Set: Ry
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iclsSpLoadDword,
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// Rx-offset Store Byte Class
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// Text Format: SB ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, Ry
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// Registers Set:
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iclsRxStoreByte,
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// Rx-offset Store Halfword Class
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// Text Format: SH ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, Ry
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// Registers Set:
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iclsRxStoreHalfword,
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// Rx-offset Store Word Class
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// Text Format: SW ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, Ry
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// Registers Set:
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iclsRxStoreWord,
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// SP-offset Store Word Class
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// Text Format: SW ry,offset(sp)
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// Termination Type: trmtaFallThrough
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// Registers Used: SP, Rx
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// Registers Set:
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iclsSpStoreWord,
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// SP-offset Store RA Word Class
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// Text Format: SW ra,offset(sp)
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// Termination Type: trmtaFallThrough
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// Registers Used: SP, RA
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// Registers Set:
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iclsSpStoreRaWord,
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// Rx-offset Store DWord Class
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// Text Format: SD ry,offset(rx)
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, Ry
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// Registers Set:
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iclsRxStoreDword,
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// SP-offset Store DWord Class
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// Text Format: SD ry,offset(sp)
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// Termination Type: trmtaFallThrough
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// Registers Used: SP, Ry
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// Registers Set:
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iclsSpStoreDword,
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// SP-offset Store RA DWord Class
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// Text Format: SD ra,offset(sp)
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// Termination Type: trmtaFallThrough
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// Registers Used: SP, RA
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// Registers Set:
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iclsSpStoreRaDword,
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// Immediate Type 3 Class
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// Text Format: SLTI rx,imm
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// Termination Type: trmtaFallThrough
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// Registers Used:
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// Registers Set: Rx
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iclsImmediate3,
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// Immediate Type 0 Class
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// Text Format: ADDIU ry,rx,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Ry
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iclsImmediate0,
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// Immediate Type 1 Class
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// Text Format: ADDIU rx,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Rx
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iclsImmediate1,
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// Immediate Type 4 Class
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// Text Format: LI rx,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx
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// Registers Set: Rx
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iclsImmediate4,
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// Immediate SP Class
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// Text Format: ADDIU sp,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: SP
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// Registers Set: SP
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iclsImmSp,
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// Immediate Rx-PC Class
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// Text Format: ADDIU rx,pc,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, PC
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// Registers Set: Rx
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iclsImmRxPc,
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// Immediate Ry-PC Class
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// Text Format: DADDIU ry,pc,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Ry, PC
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// Registers Set: Ry
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iclsImmRyPc,
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// Immediate Rx-SP Class
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// Text Format: ADDIU rx,sp,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, SP
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// Registers Set: Rx
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iclsImmRxSp,
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// Immediate Type 2 Class
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// Text Format: DADDIU ry,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Ry
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// Registers Set: Ry
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iclsImmediate2,
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// Immediate Ry-SP Class
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// Text Format: DADDIU ry,sp,imm
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// Termination Type: trmtaFallThrough
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// Registers Used: Ry, SP
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// Registers Set: Ry
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iclsImmRySp,
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// Two Operand Class
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// Text Format: CMP rx,ry
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, Ry
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// Registers Set:
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iclsOp2,
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// Three Operand Class
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// Text Format: ADDU rz,rx,ry
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// Termination Type: trmtaFallThrough
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// Registers Used: Rx, Ry
|
|
// Registers Set: Rz
|
|
|
|
iclsOp3,
|
|
|
|
// Move Ry,R32 Class
|
|
|
|
// Text Format: MOVE Ry,R32
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used: R32
|
|
// Registers Set: Ry
|
|
|
|
iclsMoveR32,
|
|
|
|
// Move R32,Rw Class
|
|
|
|
// Text Format: MOVE R32,Rw
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used: Rw
|
|
// Registers Set: R32
|
|
|
|
iclsMove32R,
|
|
|
|
// Shift Type 0 Class
|
|
|
|
// Text Format: SLL ry,rx,imm
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used: Ry
|
|
// Registers Set: Rx
|
|
|
|
iclsShift0,
|
|
|
|
// Shift Variable Class
|
|
|
|
// Text Format: SLLV ry,rx
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used: Rx, Ry
|
|
// Registers Set: Ry
|
|
|
|
iclsShiftVar,
|
|
|
|
// Shift Type 1 Class
|
|
|
|
// Text Format: DSRL ry,imm
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used: Ry
|
|
// Registers Set: Ry
|
|
|
|
iclsShift1,
|
|
|
|
// Shift Type 2 Class
|
|
|
|
// Text Format: DSLL rx,ry,imm
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used: Ry
|
|
// Registers Set: Rx
|
|
|
|
iclsShift2,
|
|
|
|
// Move From HI/LO Class
|
|
|
|
// Text Format: MFHI rx
|
|
|
|
// Termination Type: trmtaFallThrough
|
|
|
|
// Registers Used:
|
|
// Registers Set: Rx
|
|
|
|
iclsMoveHiLo,
|
|
|
|
// Call Class
|
|
|
|
// Text Format: JAL target
|
|
|
|
// Termination Type: trmtaCallDef
|
|
|
|
// Registers Used:
|
|
// Registers Set: RA
|
|
|
|
iclsCall,
|
|
|
|
// Jump Register Rx Class
|
|
|
|
// Text Format: JR rx
|
|
|
|
// Termination Type: trmtaBraInd
|
|
|
|
// Registers Used: Rx
|
|
// Registers Set:
|
|
|
|
iclsJumpReg,
|
|
|
|
// Jump Register RA Class
|
|
|
|
// Text Format: JR ra
|
|
|
|
// Termination Type: trmtaBraInd
|
|
|
|
// Registers Used: RA
|
|
// Registers Set:
|
|
|
|
iclsJumpRegRa,
|
|
|
|
// Call Register Class
|
|
|
|
// Text Format: JALR ra,rx
|
|
|
|
// Termination Type: trmtaCallInd
|
|
|
|
// Registers Used: Rx
|
|
// Registers Set: RA
|
|
|
|
iclsCallReg,
|
|
|
|
// Branch Conditional Type 0
|
|
|
|
// Text Format: BEQZ rx,target
|
|
|
|
// Termination Type: trmtaBraCc
|
|
|
|
// Registers Used: Rx
|
|
// Registers Set: RA
|
|
|
|
iclsBraCc0,
|
|
|
|
// Branch Conditional Type 1
|
|
|
|
// Text Format: BTEQZ target
|
|
|
|
// Termination Type: trmtaBraCc
|
|
|
|
// Registers Used: T
|
|
// Registers Set:
|
|
|
|
iclsBraCc1,
|
|
|
|
// Branch Unconditional
|
|
|
|
// Text Format: B target
|
|
|
|
// Termination Type: trmtaBra
|
|
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsBra,
|
|
|
|
// Trap
|
|
|
|
// Text Format: BREAK imm
|
|
|
|
// Termination Type: trmtaTrap
|
|
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsTrap,
|
|
|
|
// Nop
|
|
|
|
// Text Format: NOP
|
|
|
|
// Termination Type: trmtaTrap
|
|
|
|
// Registers Used:
|
|
// Registers Set:
|
|
|
|
iclsNop,
|
|
};
|
|
|
|
struct CLS
|
|
{
|
|
TRMTA trmta;
|
|
OPCLS rgopcls[3]; // Operand class for each operand
|
|
};
|
|
|
|
struct OPCD
|
|
{
|
|
const char *szMnemonic;
|
|
ICLS icls;
|
|
};
|
|
|
|
static const TRMT mptrmtatrmt[];
|
|
|
|
static const CLS rgcls[];
|
|
|
|
static const OPCD rgopcd[];
|
|
static const OPCD rgopcdJal[];
|
|
static const OPCD rgopcdShift[];
|
|
static const OPCD rgopcdRria[];
|
|
static const OPCD rgopcdI8[];
|
|
static const OPCD rgopcdRrr[];
|
|
static const OPCD rgopcdRr[];
|
|
static const OPCD rgopcdI64[];
|
|
static const OPCD rgopcdJr[];
|
|
static const OPCD rgopcdNop;
|
|
|
|
static const char * const rgszGpr[];
|
|
|
|
static const REGA rgiMap[];
|
|
|
|
bool FCalcOffsetReg(OPCLS, DWORD *, REGA *) const;
|
|
void FormatImmediate (std::ostream&, DWORD) const;
|
|
void FormatOffsetReg(std::ostream&, DWORD, REGA) const;
|
|
void FormatOperand(std::ostream&, OPCLS) const;
|
|
bool FValidOperand(size_t) const;
|
|
static const OPCD *PopcdDecode(IW);
|
|
|
|
IW m_iw; // current instruction word
|
|
EW m_ew; // current extend word
|
|
WORD m_nw; // next word
|
|
DWORD m_imm4; // sign extended 4-bit immediate
|
|
DWORD m_imm5; // sign extended 5-bit immediate
|
|
DWORD m_imm8; // sign extended 8-bit immediate
|
|
DWORD m_imm11; // sign extended 11-bit immediate
|
|
ADDR m_basePc; // value of PC for this instruction
|
|
bool m_fExtend; // this instruction was extended
|
|
const OPCD *m_popcd;
|
|
};
|
|
|
|
#pragma pack(pop)
|