889 lines
31 KiB
C
889 lines
31 KiB
C
/*++
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Copyright (c) 1993 IBM Corporation and Microsoft Corporation
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Module Name:
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alignem.c
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Abstract:
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This module implements the code necessary to emulate unaligned data
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references.
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Author:
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Rick Simpson 4-Aug-1993
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Based on MIPS version by David N. Cutler (davec) 17-Jun-1991
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "ki.h"
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VOID
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KiSetFloatRegisterValue (
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IN ULONG,
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IN DOUBLE,
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OUT PKEXCEPTION_FRAME,
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OUT PKTRAP_FRAME
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);
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DOUBLE
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KiGetFloatRegisterValue (
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IN ULONG,
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IN PKEXCEPTION_FRAME,
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IN PKTRAP_FRAME
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);
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/*++
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When PowerPC takes an Alignment Interrupt, the hardware loads the following:
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SRR 0 <- Address of instruction causing the interrupt
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SRR 1 <- MSR
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DAR <- Effective address of the misaligned reference as computed
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by the instruction that caused the interrupt
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DSISR <- Several fields relevant to the failing instruction:
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Bits 12..13 <- Extended op-code (XO) if instr is DS-form
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Bits 15..21 <- Index into the table below, identifying
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(for the most part) the failing instr
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Bits 22..26 <- RT/RS/FRT/FRS field (reg no.) of instr
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Bits 27..31 <- RA (reg no.) field for update-form instrs
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For the most part, it is not necessary to retrieve the actual instruction
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in order to emulate the effects of an unaligned load or store. Enough
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information is in the DSISR to distinguish most cases. Special processing
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is required for certain instructions -- the DSISR does not have enough
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information for them.
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It is unnecessary to compute the failing effective address by emulating
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the instruction's addressing arithmetic, because the value required is
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contained in the DAR.
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The table here is indexed by bits 15..21 of the DSISR.
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The "escape" flag indicates that some sort of special handling is needed,
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for one of the following reasons:
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1) More than one instruction maps to the same DSISR value
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(ld/ldu/lwa, std/stdu)
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2) The instruction is load-and-reserve or store-conditional,
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and misalignment should not be "fixed up"
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3) The instruction is a byte-reversed load or store
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4) The instruction is "ecowx" or "eciwx"
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5) The instruction is "dcbz"
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6) The instruction is "stfiwx"
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NOTE: Even though lwz and lwarx share the same DSISR value (0), the
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table entry for position 0 is used only for lwz. This is so that the
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most likely case (load word from unaligned address) can take the
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mainline path. The less likely case (load word and reserve from
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unaligned address) is ignored and treated as if it were simply load
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word. Unaligned addresses are not supported for lwarx/stwcx. in the
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PowerPC architecture. The implementation here (allowing lwarx to
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proceed as if it were lwx, without establishing a reservation) is
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allowable according to the architecture; a matching store conditional
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(stwcx.) to the same unaligned address will fail (return FALSE from
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this routine), so the incorrect reservation address will be caught
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then.
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--*/
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typedef struct _ALFAULT {
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ULONG Valid : 1; // Valid DSISR value (1) vs. Should not occur (0)
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ULONG Load : 1; // Load (1) vs. Store (0)
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ULONG Length : 2; // Length: 2 bytes (1), 4 bytes (2), 8 bytes (3)
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ULONG Signed : 1; // Sign-extended (1) vs. Zero-extended (0)
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ULONG Fixed : 1; // Fixed point (1) vs. Floating point (0)
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ULONG Update : 1; // Update-form (1) vs. Non-Update-form (0)
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ULONG Escape : 1; // Needs special processing (1) vs. Regular (0)
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} ALFAULT, *PALFAULT;
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// Table indices for instructions needing special handling
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#define LDARX_INDEX_VALUE 1
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#define LD_INDEX_VALUE 13
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#define STD_INDEX_VALUE 15
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#define STWCX_INDEX_VALUE 66
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#define STDCX_INDEX_VALUE 67
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#define LWBRX_INDEX_VALUE 72
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#define STWBRX_INDEX_VALUE 74
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#define LHBRX_INDEX_VALUE 76
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#define STHBRX_INDEX_VALUE 78
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#define ECIWX_INDEX_VALUE 84
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#define ECOWX_INDEX_VALUE 86
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#define DCBZ_INDEX_VALUE 95
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#define STFIWX_INDEX_VALUE 111
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static ALFAULT AlFault[128] = {
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// Valid Load Length Signed Fixed Update Escape
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{ 1, 1, 2, 0, 1, 0, 0 }, // 0 lwz, lwarx
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{ 1, 1, 3, 0, 1, 0, 1 }, // 1 ldarx
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{ 1, 0, 2, 0, 1, 0, 0 }, // 2 stw
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{ 0, 0, 0, 0, 0, 0, 0 }, // 3
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{ 1, 1, 1, 0, 1, 0, 0 }, // 4 lhz
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{ 1, 1, 1, 1, 1, 0, 0 }, // 5 lha
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{ 1, 0, 1, 0, 1, 0, 0 }, // 6 sth
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{ 0, 0, 0, 0, 0, 0, 0 }, // 7
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{ 1, 1, 2, 0, 0, 0, 0 }, // 8 lfs
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{ 1, 1, 3, 0, 0, 0, 0 }, // 9 lfd
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{ 1, 0, 2, 0, 0, 0, 0 }, // 10 stfs
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{ 1, 0, 3, 0, 0, 0, 0 }, // 11 stfd
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{ 0, 0, 0, 0, 0, 0, 0 }, // 12
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{ 1, 1, 0, 0, 0, 0, 1 }, // 13 ld, ldu, lwa
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{ 0, 0, 0, 0, 0, 0, 0 }, // 14
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{ 1, 0, 0, 0, 0, 0, 1 }, // 15 std, stdu
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{ 1, 1, 2, 0, 1, 1, 0 }, // 16 lwzu
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{ 0, 0, 0, 0, 0, 0, 0 }, // 17
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{ 1, 0, 2, 0, 1, 1, 0 }, // 18 stwu
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{ 0, 0, 0, 0, 0, 0, 0 }, // 19
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{ 1, 1, 1, 0, 1, 1, 0 }, // 20 lhzu
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{ 1, 1, 1, 1, 1, 1, 0 }, // 21 lhau
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{ 1, 0, 1, 0, 1, 1, 0 }, // 22 sthu
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{ 0, 0, 0, 0, 0, 0, 0 }, // 23
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{ 1, 1, 2, 0, 0, 1, 0 }, // 24 lfsu
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{ 1, 1, 3, 0, 0, 1, 0 }, // 25 lfdu
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{ 1, 0, 2, 0, 0, 1, 0 }, // 26 stfsu
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{ 1, 0, 3, 0, 0, 1, 0 }, // 27 stfdu
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{ 0, 0, 0, 0, 0, 0, 0 }, // 28
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{ 0, 0, 0, 0, 0, 0, 0 }, // 29
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{ 0, 0, 0, 0, 0, 0, 0 }, // 30
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{ 0, 0, 0, 0, 0, 0, 0 }, // 31
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{ 1, 1, 3, 0, 1, 0, 0 }, // 32 ldx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 33
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{ 1, 0, 3, 0, 1, 0, 0 }, // 34 stdx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 35
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{ 0, 0, 0, 0, 0, 0, 0 }, // 36
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{ 1, 1, 2, 1, 1, 0, 0 }, // 37 lwax
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{ 0, 0, 0, 0, 0, 0, 0 }, // 38
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{ 0, 0, 0, 0, 0, 0, 0 }, // 39
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{ 0, 0, 0, 0, 0, 0, 0 }, // 40
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{ 0, 0, 0, 0, 0, 0, 0 }, // 41
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{ 0, 0, 0, 0, 0, 0, 0 }, // 42
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{ 0, 0, 0, 0, 0, 0, 0 }, // 43
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{ 0, 0, 0, 0, 0, 0, 0 }, // 44
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{ 0, 0, 0, 0, 0, 0, 0 }, // 45
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{ 0, 0, 0, 0, 0, 0, 0 }, // 46
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{ 0, 0, 0, 0, 0, 0, 0 }, // 47
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{ 1, 1, 3, 0, 1, 1, 0 }, // 48 ldux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 49
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{ 1, 0, 3, 0, 1, 1, 0 }, // 50 stdux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 51
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{ 0, 0, 0, 0, 0, 0, 0 }, // 52
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{ 1, 1, 2, 1, 1, 1, 0 }, // 53 lwaux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 54
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{ 0, 0, 0, 0, 0, 0, 0 }, // 55
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{ 0, 0, 0, 0, 0, 0, 0 }, // 56
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{ 0, 0, 0, 0, 0, 0, 0 }, // 57
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{ 0, 0, 0, 0, 0, 0, 0 }, // 58
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{ 0, 0, 0, 0, 0, 0, 0 }, // 59
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{ 0, 0, 0, 0, 0, 0, 0 }, // 60
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{ 0, 0, 0, 0, 0, 0, 0 }, // 61
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{ 0, 0, 0, 0, 0, 0, 0 }, // 62
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{ 0, 0, 0, 0, 0, 0, 0 }, // 63
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{ 0, 0, 0, 0, 0, 0, 0 }, // 64
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{ 0, 0, 0, 0, 0, 0, 0 }, // 65
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{ 1, 0, 2, 0, 1, 0, 1 }, // 66 stwcx.
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{ 1, 0, 3, 0, 1, 0, 1 }, // 67 stdcx.
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{ 0, 0, 0, 0, 0, 0, 0 }, // 68
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{ 0, 0, 0, 0, 0, 0, 0 }, // 69
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{ 0, 0, 0, 0, 0, 0, 0 }, // 70
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{ 0, 0, 0, 0, 0, 0, 0 }, // 71
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{ 1, 1, 2, 0, 1, 0, 1 }, // 72 lwbrx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 73
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{ 1, 0, 2, 0, 1, 0, 1 }, // 74 stwbrx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 75
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{ 1, 1, 1, 0, 1, 0, 1 }, // 76 lhbrx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 77
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{ 1, 0, 1, 0, 1, 0, 1 }, // 78 sthbrx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 79
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{ 0, 0, 0, 0, 0, 0, 0 }, // 80
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{ 0, 0, 0, 0, 0, 0, 0 }, // 81
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{ 0, 0, 0, 0, 0, 0, 0 }, // 82
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{ 0, 0, 0, 0, 0, 0, 0 }, // 83
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{ 1, 1, 2, 0, 1, 0, 1 }, // 84 eciwx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 85
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{ 1, 0, 2, 0, 1, 0, 1 }, // 86 ecowx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 87
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{ 0, 0, 0, 0, 0, 0, 0 }, // 88
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{ 0, 0, 0, 0, 0, 0, 0 }, // 89
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{ 0, 0, 0, 0, 0, 0, 0 }, // 90
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{ 0, 0, 0, 0, 0, 0, 0 }, // 91
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{ 0, 0, 0, 0, 0, 0, 0 }, // 92
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{ 0, 0, 0, 0, 0, 0, 0 }, // 93
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{ 0, 0, 0, 0, 0, 0, 0 }, // 94
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{ 1, 0, 0, 0, 0, 0, 1 }, // 95 dcbz
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{ 1, 1, 2, 0, 1, 0, 0 }, // 96 lwzx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 97
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{ 1, 0, 2, 0, 1, 0, 0 }, // 98 stwzx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 99
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{ 1, 1, 1, 0, 1, 0, 0 }, // 100 lhzx
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{ 1, 1, 1, 1, 1, 0, 0 }, // 101 lhax
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{ 1, 0, 1, 0, 1, 0, 0 }, // 102 sthx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 103
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{ 1, 1, 2, 0, 0, 0, 0 }, // 104 lfsx
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{ 1, 1, 3, 0, 0, 0, 0 }, // 105 lfdx
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{ 1, 0, 2, 0, 0, 0, 0 }, // 106 stfsx
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{ 1, 0, 3, 0, 0, 0, 0 }, // 107 stfdx
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{ 0, 0, 0, 0, 0, 0, 0 }, // 108
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{ 0, 0, 0, 0, 0, 0, 0 }, // 109
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{ 0, 0, 0, 0, 0, 0, 0 }, // 110
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{ 1, 0, 2, 0, 1, 0, 1 }, // 111 stfiwx
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{ 1, 1, 2, 0, 1, 1, 0 }, // 112 lwzux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 113
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{ 1, 0, 2, 0, 1, 1, 0 }, // 114 stwux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 115
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{ 1, 1, 1, 0, 1, 1, 0 }, // 116 lhzux
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{ 1, 1, 1, 1, 1, 1, 0 }, // 117 lhaux
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{ 1, 0, 1, 0, 1, 1, 0 }, // 118 sthux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 119
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{ 1, 1, 2, 0, 0, 1, 0 }, // 120 lfsux
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{ 1, 1, 3, 0, 0, 1, 0 }, // 121 lfdux
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{ 1, 0, 2, 0, 0, 1, 0 }, // 122 stfsux
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{ 1, 0, 3, 0, 0, 1, 0 }, // 123 stfdux
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{ 0, 0, 0, 0, 0, 0, 0 }, // 124
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{ 0, 0, 0, 0, 0, 0, 0 }, // 125
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{ 0, 0, 0, 0, 0, 0, 0 }, // 126
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{ 0, 0, 0, 0, 0, 0, 0 } // 127
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};
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BOOLEAN
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KiEmulateReference (
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IN OUT PEXCEPTION_RECORD ExceptionRecord,
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IN OUT PKEXCEPTION_FRAME ExceptionFrame,
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IN OUT PKTRAP_FRAME TrapFrame
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)
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/*++
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Routine Description:
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This function is called to emulate an unaligned data reference to an
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address in the user part of the address space.
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Arguments:
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ExceptionRecord - Supplies a pointer to an exception record.
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ExceptionFrame - Supplies a pointer to an exception frame.
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TrapFrame - Supplies a pointer to a trap frame.
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Return Value:
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A value of TRUE is returned if the data reference is successfully
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emulated. Otherwise, a value of FALSE is returned.
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--*/
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{
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ULONG BranchAddress;
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PUCHAR DataAddress;
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union {
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DOUBLE Double;
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float Float;
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ULONG Long;
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SHORT Short;
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} DataReference;
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PUCHAR DataValue = (PUCHAR) &DataReference;
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PVOID ExceptionAddress;
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DSISR DsisrValue;
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ULONG TableIndex;
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ULONG DataRegNum;
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ALFAULT Info;
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KIRQL OldIrql;
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// Call out to profile interrupt if alignment profiling is active
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if (KiProfileAlignmentFixup) {
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if (++KiProfileAlignmentFixupCount >= KiProfileAlignmentFixupInterval) {
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KeRaiseIrql(PROFILE_LEVEL, &OldIrql);
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KiProfileAlignmentFixupCount = 0;
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KeProfileInterruptWithSource(TrapFrame, ProfileAlignmentFixup);
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KeLowerIrql(OldIrql);
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}
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}
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// Save the original exception address in case another exception
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// occurs.
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ExceptionAddress = ExceptionRecord->ExceptionAddress;
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// Any exception that occurs during the attempted emulation of the
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// unaligned reference causes the emulation to be aborted. The new
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// exception code and information is copied to the original exception
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// record and a value of FALSE is returned.
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try {
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// PowerPC has no branch-delay-slot complexities like MIPS
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BranchAddress = TrapFrame->Iar + 4;
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// The effective address of the reference from the DAR was saved
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// in the exception record. Check to make sure it is within the
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// user part of the address space. Alignment exceptions take
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// precedence over memory management exceptions (this is true
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// for PowerPC as well as MIPS) and the address could be a
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// system address.
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DataAddress = (PUCHAR) (ExceptionRecord->ExceptionInformation[1]);
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if ((ULONG)DataAddress < MM_USER_PROBE_ADDRESS) {
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// Get information about the failing instruction from saved DSISR.
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DsisrValue = *(DSISR*) &(ExceptionRecord->ExceptionInformation[2]);
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TableIndex = DsisrValue.Index;
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DataRegNum = DsisrValue.DataReg;
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Info = AlFault[TableIndex];
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// If table entry is marked invalid, we have some sort of logic error.
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if (!Info.Valid)
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return FALSE;
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// If table entry does not indicate special processing needed,
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// emulate the execution of the instruction
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if (!Info.Escape) {
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// Integer or float load or store
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if (Info.Fixed) {
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// Integer register
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if (Info.Load) {
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// Integer load
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switch (Info.Length) {
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// Halfword integer load
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case 1:
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DataValue[0] = DataAddress[0];
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DataValue[1] = DataAddress[1];
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KiSetRegisterValue
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(DataRegNum,
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Info.Signed ? // sign extension ...
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(ULONG) ((LONG) DataReference.Short) :
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(ULONG) ((USHORT) DataReference.Short),
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ExceptionFrame,
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TrapFrame);
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break;
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// Fullword integer load
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case 2:
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DataValue[0] = DataAddress[0];
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DataValue[1] = DataAddress[1];
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DataValue[2] = DataAddress[2];
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DataValue[3] = DataAddress[3];
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KiSetRegisterValue
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(DataRegNum,
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DataReference.Long,
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ExceptionFrame,
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TrapFrame);
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break;
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// Doubleword integer load
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case 3:
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return FALSE; // Have no 8-byte integer regs yet
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}
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} else {
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// Integer store
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switch (Info.Length) {
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// Halfword integer store
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case 1:
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DataReference.Short = (SHORT)
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KiGetRegisterValue
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(DataRegNum,
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ExceptionFrame,
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TrapFrame);
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DataAddress[0] = DataValue[0];
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DataAddress[1] = DataValue[1];
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break;
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// Fullword integer store
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case 2: // Word
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DataReference.Long =
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KiGetRegisterValue
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(DataRegNum,
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ExceptionFrame,
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TrapFrame);
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DataAddress[0] = DataValue[0];
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DataAddress[1] = DataValue[1];
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DataAddress[2] = DataValue[2];
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DataAddress[3] = DataValue[3];
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break;
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// Doubleword integer store
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case 3:
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return FALSE; // Have no 8-byte integer regs yet
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}
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}
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} else { // Floating point
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// Floating-point register
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if (Info.Load) { // Floating point load
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// Floating-point load
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if (Info.Length == 2) {
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// Floating-point single precision load
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DataValue[0] = DataAddress[0];
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DataValue[1] = DataAddress[1];
|
|
DataValue[2] = DataAddress[2];
|
|
DataValue[3] = DataAddress[3];
|
|
KiSetFloatRegisterValue
|
|
(DataRegNum,
|
|
(DOUBLE) DataReference.Float,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
|
|
} else {
|
|
|
|
|
|
// Floating-point double precision load
|
|
|
|
DataValue[0] = DataAddress[0];
|
|
DataValue[1] = DataAddress[1];
|
|
DataValue[2] = DataAddress[2];
|
|
DataValue[3] = DataAddress[3];
|
|
DataValue[4] = DataAddress[4];
|
|
DataValue[5] = DataAddress[5];
|
|
DataValue[6] = DataAddress[6];
|
|
DataValue[7] = DataAddress[7];
|
|
KiSetFloatRegisterValue
|
|
(DataRegNum,
|
|
DataReference.Double,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
}
|
|
} else {
|
|
|
|
|
|
// Floating-point store
|
|
|
|
|
|
if (Info.Length == 2) {
|
|
|
|
|
|
// Floating-point single precision store
|
|
|
|
|
|
DataReference.Float = (float)
|
|
KiGetFloatRegisterValue
|
|
(DataRegNum,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
DataAddress[0] = DataValue[0];
|
|
DataAddress[1] = DataValue[1];
|
|
DataAddress[2] = DataValue[2];
|
|
DataAddress[3] = DataValue[3];
|
|
|
|
} else {
|
|
|
|
|
|
// Floating-point double precision store
|
|
|
|
DataReference.Double =
|
|
KiGetFloatRegisterValue
|
|
(DataRegNum,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
DataAddress[0] = DataValue[0];
|
|
DataAddress[1] = DataValue[1];
|
|
DataAddress[2] = DataValue[2];
|
|
DataAddress[3] = DataValue[3];
|
|
DataAddress[4] = DataValue[4];
|
|
DataAddress[5] = DataValue[5];
|
|
DataAddress[6] = DataValue[6];
|
|
DataAddress[7] = DataValue[7];
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// See if "update" (post-increment) form of addressing
|
|
|
|
|
|
if (Info.Update)
|
|
KiSetRegisterValue // Store effective addr back into base reg
|
|
(DsisrValue.UpdateReg,
|
|
(ULONG) DataAddress,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
|
|
}
|
|
|
|
|
|
// Table indicates that special processing is needed, either because
|
|
// the DSISR does not contain enough information to disambiguate the
|
|
// failing instruction, or the instruction is not a load or store,
|
|
// or the instruction has some other unusual requirement.
|
|
|
|
|
|
else { // Info.Escape == 1
|
|
switch (TableIndex) {
|
|
|
|
|
|
// Doubleword integers not yet supported
|
|
|
|
|
|
case LD_INDEX_VALUE:
|
|
case STD_INDEX_VALUE:
|
|
return FALSE;
|
|
|
|
|
|
// Load-and-reserve, store-conditional not supported
|
|
// for misaligned addresses
|
|
|
|
|
|
case LDARX_INDEX_VALUE:
|
|
case STWCX_INDEX_VALUE:
|
|
case STDCX_INDEX_VALUE:
|
|
return FALSE;
|
|
|
|
|
|
// Integer byte-reversed fullword load
|
|
|
|
|
|
case LWBRX_INDEX_VALUE:
|
|
DataValue[0] = DataAddress[3];
|
|
DataValue[1] = DataAddress[2];
|
|
DataValue[2] = DataAddress[1];
|
|
DataValue[3] = DataAddress[0];
|
|
KiSetRegisterValue
|
|
(DataRegNum,
|
|
DataReference.Long,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
break;
|
|
|
|
|
|
// Integer byte-reversed fullword store
|
|
|
|
|
|
case STWBRX_INDEX_VALUE:
|
|
DataReference.Long =
|
|
KiGetRegisterValue
|
|
(DataRegNum,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
DataAddress[0] = DataValue[3];
|
|
DataAddress[1] = DataValue[2];
|
|
DataAddress[2] = DataValue[1];
|
|
DataAddress[3] = DataValue[0];
|
|
break;
|
|
|
|
|
|
// Integer byte-reversed halfword load
|
|
|
|
|
|
case LHBRX_INDEX_VALUE:
|
|
DataValue[0] = DataAddress[1];
|
|
DataValue[1] = DataAddress[0];
|
|
KiSetRegisterValue
|
|
(DataRegNum,
|
|
Info.Signed ? // sign extension ...
|
|
(ULONG) ((LONG) DataReference.Short) :
|
|
(ULONG) ((USHORT) DataReference.Short),
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
break;
|
|
|
|
|
|
// Integer byte-reversed halfword store
|
|
|
|
|
|
case STHBRX_INDEX_VALUE:
|
|
DataReference.Short = (SHORT)
|
|
KiGetRegisterValue
|
|
(DataRegNum,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
DataAddress[0] = DataValue[1];
|
|
DataAddress[1] = DataValue[0];
|
|
break;
|
|
|
|
|
|
// Special I/O instructions not supported yet
|
|
|
|
|
|
case ECIWX_INDEX_VALUE:
|
|
case ECOWX_INDEX_VALUE:
|
|
return FALSE;
|
|
|
|
|
|
// Data Cache Block Zero
|
|
|
|
// dcbz causes an alignment fault if cache is disabled
|
|
// for the address range covered by the block.
|
|
|
|
// A data cache block is 32 bytes long, we emulate this
|
|
// instruction by storing 8 zero integers a the address
|
|
// specified.
|
|
|
|
// Note, dcbz zeros the block "containing" the address
|
|
// so we round down first.
|
|
|
|
|
|
case DCBZ_INDEX_VALUE: {
|
|
PULONG DcbAddress = (PULONG)((ULONG)DataAddress & ~0x1f);
|
|
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
break;
|
|
}
|
|
|
|
|
|
// Store Floating as Integer
|
|
|
|
|
|
case STFIWX_INDEX_VALUE:
|
|
DataReference.Double =
|
|
KiGetFloatRegisterValue
|
|
(DataRegNum,
|
|
ExceptionFrame,
|
|
TrapFrame);
|
|
DataAddress[0] = DataValue[0];
|
|
DataAddress[1] = DataValue[1];
|
|
DataAddress[2] = DataValue[2];
|
|
DataAddress[3] = DataValue[3];
|
|
}
|
|
}
|
|
|
|
TrapFrame->Iar = BranchAddress;
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
// If an exception occurs, then copy the new exception information to the
|
|
// original exception record and handle the exception.
|
|
|
|
|
|
} except (KiCopyInformation(ExceptionRecord,
|
|
(GetExceptionInformation())->ExceptionRecord)) {
|
|
|
|
|
|
// Preserve the original exception address.
|
|
|
|
|
|
ExceptionRecord->ExceptionAddress = ExceptionAddress;
|
|
}
|
|
|
|
|
|
// Return a value of FALSE.
|
|
|
|
|
|
return FALSE;
|
|
}
|
|
|
|
BOOLEAN
|
|
KiEmulateDcbz (
|
|
IN OUT PEXCEPTION_RECORD ExceptionRecord,
|
|
IN OUT PKEXCEPTION_FRAME ExceptionFrame,
|
|
IN OUT PKTRAP_FRAME TrapFrame
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is called to emulate a Data Cache Block Zero instruction.
|
|
The PowerPC hardware will raise an alignment exception if a DCBZ is
|
|
attempted on non-cached memory. We need to emulate this even in kernel
|
|
mode so we can debug h/w problems by disabling the data cache.
|
|
|
|
Arguments:
|
|
|
|
ExceptionRecord - Supplies a pointer to an exception record.
|
|
|
|
ExceptionFrame - Supplies a pointer to an exception frame.
|
|
|
|
TrapFrame - Supplies a pointer to a trap frame.
|
|
|
|
Return Value:
|
|
|
|
A value of TRUE is returned if the data reference is successfully
|
|
emulated. Otherwise, a value of FALSE is returned.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
PUCHAR DataAddress;
|
|
PVOID ExceptionAddress;
|
|
DSISR DsisrValue;
|
|
ULONG TableIndex;
|
|
ULONG DataRegNum;
|
|
ALFAULT Info;
|
|
|
|
|
|
// Save the original exception address in case another exception
|
|
// occurs.
|
|
|
|
|
|
ExceptionAddress = ExceptionRecord->ExceptionAddress;
|
|
|
|
|
|
// Any exception that occurs during the attempted emulation of the
|
|
// unaligned reference causes the emulation to be aborted. The new
|
|
// exception code and information is copied to the original exception
|
|
// record and a value of FALSE is returned.
|
|
|
|
|
|
try {
|
|
|
|
|
|
// The effective address of the reference from the DAR was saved
|
|
// in the exception record. Check to make sure it is within the
|
|
// user part of the address space. Alignment exceptions take
|
|
// precedence over memory management exceptions (this is true
|
|
// for PowerPC as well as MIPS) and the address could be a
|
|
// system address.
|
|
|
|
|
|
DataAddress = (PUCHAR) (ExceptionRecord->ExceptionInformation[1]);
|
|
|
|
|
|
// Get information about the failing instruction from saved DSISR.
|
|
|
|
|
|
DsisrValue = *(DSISR*) &(ExceptionRecord->ExceptionInformation[2]);
|
|
TableIndex = DsisrValue.Index;
|
|
DataRegNum = DsisrValue.DataReg;
|
|
Info = AlFault[TableIndex];
|
|
|
|
|
|
// If table entry is valid and does not indicate special processing
|
|
// needed, and is a DCBZ instruction, emulate the execution of the
|
|
// instruction
|
|
|
|
|
|
if (Info.Valid && Info.Escape && (TableIndex == DCBZ_INDEX_VALUE)) {
|
|
|
|
|
|
// Data Cache Block Zero
|
|
|
|
// A data cache block is 32 bytes long, we emulate this
|
|
// instruction by storing 8 zero integers a the address
|
|
// specified.
|
|
|
|
// Note, dcbz zeros the block "containing" the address
|
|
// so we round down first.
|
|
|
|
|
|
PULONG DcbAddress = (PULONG)((ULONG)DataAddress & ~0x1f);
|
|
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
*DcbAddress++ = 0;
|
|
|
|
|
|
// Bump instruction address to next instruction.
|
|
|
|
|
|
TrapFrame->Iar += 4;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
// If an exception occurs, then copy the new exception information to the
|
|
// original exception record and handle the exception.
|
|
|
|
|
|
} except (KiCopyInformation(ExceptionRecord,
|
|
(GetExceptionInformation())->ExceptionRecord)) {
|
|
|
|
|
|
// Preserve the original exception address.
|
|
|
|
|
|
ExceptionRecord->ExceptionAddress = ExceptionAddress;
|
|
}
|
|
|
|
|
|
// Return a value of FALSE.
|
|
|
|
|
|
return FALSE;
|
|
}
|