297 lines
11 KiB
C
297 lines
11 KiB
C
/*++
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Copyright (C) Microsoft Corporation, 1993 - 1999
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Module Name:
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ecp.c
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Abstract:
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Enhanced Capabilities Port (ECP)
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This module contains the common routines that aue used/ reused
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by swecp and hwecp.
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Author:
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Robbie Harris (Hewlett-Packard) - May 27, 1998
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Environment:
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Kernel mode
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Revision History :
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--*/
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#include "pch.h"
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//=========================================================
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// ECP::EnterForwardPhase
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//
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// Description : Do what is necessary to enter forward phase for ECP
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//
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// Input Parameters : Controller, pPortInfoStruct
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//
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// Modifies : ECR, DCR
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//
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//=========================================================
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NTSTATUS
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ParEcpEnterForwardPhase(IN PPDO_EXTENSION Pdx)
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{
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P5SetPhase( Pdx, PHASE_FORWARD_IDLE );
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return STATUS_SUCCESS;
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}
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// =========================================================
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// ECP::EnterReversePhase
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//
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// Description : Move from the common phase (FwdIdle, wPortHWMode=PS2)
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// to ReversePhase.
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//
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// Input Parameters : Controller, pPortInfoStruct
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//
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// Modifies : pPortInfoStruct->CurrentPhase, DCR
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//
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// Pre-conditions : CurrentPhase == PHASE_FORWARD_IDLE
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// wPortHWMode == HW_MODE_PS2
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//
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// Post-conditions : Bus is in ECP State 40
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// CurrentPhase = PHASE_REVERSE_IDLE
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//
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// Returns : status of operation
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//
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//=========================================================
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NTSTATUS ParEcpEnterReversePhase(IN PPDO_EXTENSION Pdx)
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{
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// Assume that we are in the common entry phase (FWDIDLE, and ECR mode=PS/2)
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// EnterReversePhase assumes that we are in PHASE_FORWARD_IDLE,
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// and that the ECPMode is set to PS/2 mode at entry.
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// Setup the status to indicate successful
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NTSTATUS status = STATUS_SUCCESS;
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PUCHAR wPortDCR; // I/O address of Device Control Register
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PUCHAR wPortECR; // I/O address of ECR
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UCHAR dcr;
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// Calculate I/O port addresses for common registers
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wPortDCR = Pdx->Controller + OFFSET_DCR;
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wPortECR = Pdx->EcrController + ECR_OFFSET;
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// Now, Check the current state to make sure that we are ready for
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// a change to reverse phase.
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if ( PHASE_FORWARD_IDLE == Pdx->CurrentPhase ) {
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// Okay, we are ready to proceed. Set the CurrentPhase and go on to
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// state 47
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//----------------------------------------------------------------------
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// Set CurrentPhase to indicate Forward To Reverse Mode.
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//----------------------------------------------------------------------
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P5SetPhase( Pdx, PHASE_FWD_TO_REV );
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//----------------------------------------------------------------------
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// Set Dir=1 in DCR for reading.
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//----------------------------------------------------------------------
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dcr = P5ReadPortUchar(wPortDCR); // Get content of DCR.
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dcr = UPDATE_DCR( dcr, DIR_READ, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE );
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P5WritePortUchar(wPortDCR, dcr);
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// Set the data port bits to 1 so that other circuits can control them
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//P5WritePortUchar(Controller + OFFSET_DATA, 0xFF);
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//----------------------------------------------------------------------
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// Assert HostAck low. (ECP State 38)
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//----------------------------------------------------------------------
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Pdx->CurrentEvent = 38;
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dcr = UPDATE_DCR( dcr, DIR_READ, DONT_CARE, DONT_CARE, DONT_CARE, INACTIVE, DONT_CARE );
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P5WritePortUchar(wPortDCR, dcr);
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// REVISIT: Should use TICKCount to get a finer granularity.
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// According to the spec we need to delay at least .5 us
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KeStallExecutionProcessor((ULONG) 1); // Stall for 1 us
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//----------------------------------------------------------------------
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// Assert nReverseRequest low. (ECP State 39)
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//----------------------------------------------------------------------
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Pdx->CurrentEvent = 39;
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dcr = UPDATE_DCR( dcr, DIR_READ, DONT_CARE, DONT_CARE, INACTIVE, DONT_CARE, DONT_CARE );
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P5WritePortUchar(wPortDCR, dcr);
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// NOTE: Let the caller check for State 40, since the error handling for
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// State 40 is different between hwecp and swecp.
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} else {
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DD((PCE)Pdx,DDE,"ParEcpEnterReversePhase - Invalid Phase on entry - broken state machine\n");
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PptAssertMsg("ParEcpEnterReversePhase - Invalid Phase on entry - broken state machine",FALSE);
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status = STATUS_LINK_FAILED;
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}
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return status;
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}
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//=========================================================
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// ECP::ExitReversePhase
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//
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// Description : Transition from the ECP reverse Phase to the
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// common phase for all entry functions
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//
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// Input Parameters : Controller - offset to the I/O ports
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// pPortInfoStruct - pointer to port information
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//
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// Modifies : CurrentPhase, DCR
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//
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// Pre-conditions :
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//
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// Post-conditions : NOTE: This function does not completely move to
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// the common phase for entry functions. Both the
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// HW and SW ECP classes must do extra work
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//
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// Returns : Status of the operation
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//
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//=========================================================
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NTSTATUS ParEcpExitReversePhase(IN PPDO_EXTENSION Pdx)
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{
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NTSTATUS status = STATUS_SUCCESS;
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PUCHAR Controller = Pdx->Controller;
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PUCHAR wPortDCR; // I/O address of Device Control Register
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PUCHAR wPortECR; // I/O address of ECR
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UCHAR dcr;
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wPortDCR = Controller + OFFSET_DCR;
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wPortECR = Pdx->EcrController + ECR_OFFSET;
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//----------------------------------------------------------------------
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// Set status byte to indicate Reverse To Forward Mode.
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//----------------------------------------------------------------------
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P5SetPhase( Pdx, PHASE_REV_TO_FWD );
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//----------------------------------------------------------------------
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// Set HostAck high
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//----------------------------------------------------------------------
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dcr = P5ReadPortUchar(wPortDCR);
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dcr = UPDATE_DCR( dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE, DONT_CARE );
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P5WritePortUchar(wPortDCR, dcr);
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//----------------------------------------------------------------------
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// Set nReverseRequest high. (State 47)
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//----------------------------------------------------------------------
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Pdx->CurrentEvent = 47;
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dcr = UPDATE_DCR( dcr, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE, DONT_CARE, DONT_CARE );
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P5WritePortUchar(wPortDCR, dcr);
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//----------------------------------------------------------------------
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// Check first for PeriphAck low and PeriphClk high. (State 48)
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//----------------------------------------------------------------------
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Pdx->CurrentEvent = 48;
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if( ! CHECK_DSR(Controller, INACTIVE, ACTIVE, DONT_CARE, ACTIVE, DONT_CARE, IEEE_MAXTIME_TL) ) {
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// Bad things happened - timed out on this state,
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// Mark Status as bad and let our mgr kill ECP mode.
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// status = SLP_RecoverPort( pSDCB, RECOVER_18 ); // Reset port.
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status = STATUS_LINK_FAILED;
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DD((PCE)Pdx,DDE,"ParEcpExitReversePhase - state 48 Timeout\n");
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goto ParEcpExitReversePhase;
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}
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//----------------------------------------------------------------------
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// Check next for nAckReverse high. (State 49)
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//----------------------------------------------------------------------
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Pdx->CurrentEvent = 49;
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if ( ! CHECK_DSR(Controller ,INACTIVE, ACTIVE, ACTIVE, ACTIVE, DONT_CARE, IEEE_MAXTIME_TL ) ) {
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// Bad things happened - timed out on this state,
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// Mark Status as bad and let our mgr kill ECP mode.
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//nError = RecoverPort( pSDCB, RECOVER_19 ); // Reset port.
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status = STATUS_LINK_FAILED;
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DD((PCE)Pdx,DDE,"ParEcpExitReversePhase:state 49 Timeout\n");
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goto ParEcpExitReversePhase;
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}
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// Warning: Don't assume that the ECR is in PS/2 mode here.
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// You cannot change the direction in this routine. It must be
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// done elsewhere (SWECP or HWECP).
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ParEcpExitReversePhase:
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DD((PCE)Pdx,DDT,"ParEcpExitReversePhase - exit w/status=%x\n",status);
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return status;
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}
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BOOLEAN
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ParEcpHaveReadData (
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IN PPDO_EXTENSION Pdx
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)
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{
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return ( (UCHAR)0 == (P5ReadPortUchar(Pdx->Controller + OFFSET_DSR) & DSR_NOT_PERIPH_REQUEST) );
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}
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NTSTATUS
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ParEcpSetupPhase(
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IN PPDO_EXTENSION Pdx
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)
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/*++
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Routine Description:
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This routine performs 1284 Setup Phase.
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Arguments:
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Controller - Supplies the port address.
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Return Value:
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STATUS_SUCCESS - Successful negotiation.
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otherwise - Unsuccessful negotiation.
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--*/
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{
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PUCHAR Controller;
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UCHAR dcr;
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// The negotiation succeeded. Current mode and phase.
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//
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P5SetPhase( Pdx, PHASE_SETUP );
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Controller = Pdx->Controller;
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// Negoiate leaves us in state 6, we need to be in state 30 to
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// begin transfer. Note that I am assuming that the controller
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// is already set as it should be for state 6.
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//
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// *************** State 30 Setup Phase ***************8
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// DIR = Don't Care
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// IRQEN = Don't Care
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// 1284/SelectIn = High
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// nReverseReq/**(ECP only)= High
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// HostAck/HostBusy = Low (Signals state 30)
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// HostClk/nStrobe = High
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//
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Pdx->CurrentEvent = 30;
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dcr = P5ReadPortUchar(Controller + OFFSET_DCR);
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dcr = UPDATE_DCR(dcr, DONT_CARE, DONT_CARE, ACTIVE, ACTIVE, INACTIVE, ACTIVE);
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P5WritePortUchar(Controller + OFFSET_DCR, dcr);
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// *************** State 31 Setup Phase ***************8
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// PeriphAck/PtrBusy = low
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// PeriphClk/PtrClk = high
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// nAckReverse/AckDataReq = high (Signals state 31)
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// XFlag = high
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// nPeriphReq/nDataAvail = Don't Care
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Pdx->CurrentEvent = 31;
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if (!CHECK_DSR(Controller, INACTIVE, ACTIVE, ACTIVE, ACTIVE, DONT_CARE, IEEE_MAXTIME_TL)) {
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// Bad things happened - timed out on this state.
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// Set status to an error and let PortTuple kill ECP mode (Terminate).
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DD((PCE)Pdx,DDE,"ParEcpSetupPhase - State 31 Failed - dcr=%x\n",dcr);
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P5SetPhase( Pdx, PHASE_UNKNOWN );
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return STATUS_IO_DEVICE_ERROR;
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}
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P5SetPhase( Pdx, PHASE_FORWARD_IDLE );
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DD((PCE)Pdx,DDT,"ParEcpSetupPhase - exit - STATUS_SUCCESS\n");
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return STATUS_SUCCESS;
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}
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