906 lines
24 KiB
C
906 lines
24 KiB
C
/*++
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Copyright (C) Microsoft Corporation, 1993 - 2000
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Module Name:
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swecp.c
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Abstract:
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Enhanced Capabilities Port (ECP)
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This module contains the code to perform all ECP related tasks (including
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ECP Software and ECP Hardware modes.)
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Author:
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Tim Wells (WESTTEK) - April 16, 1997
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Environment:
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Kernel mode
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Revision History :
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--*/
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#include "pch.h"
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BOOLEAN
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ParIsEcpSwWriteSupported(
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IN PPDO_EXTENSION Pdx
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)
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/*++
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Routine Description:
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This routine determines whether or not ECP mode is suported
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in the write direction by trying to negotiate when asked.
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Arguments:
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Pdx - The device extension.
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Return Value:
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BOOLEAN.
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--*/
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{
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NTSTATUS Status;
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//
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// Has a client driver or user mode app told us to avoid this mode
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// for this device via IOCTL_PAR_GET_DEVICE_CAPS?
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//
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if( Pdx->BadProtocolModes & ECP_SW ) {
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return FALSE;
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}
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//
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// Have we previously checked for and found that this mode is
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// supported with this device?
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//
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if( Pdx->ProtocolModesSupported & ECP_SW ) {
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return TRUE;
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}
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//
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// Determine if the mode is supported by trying to negotiate the
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// device the device into the requested mode.
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//
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// RMT - DVDF - 000709 - the following 2 lines really handle two distinct operations
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// each: (1) negotiating the peripheral into ECP, and (2) setting/clearing our
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// driver state machine. Consider breaking these operations out into two
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// distinct functions each.
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Status = ParEnterEcpSwMode( Pdx, FALSE );
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ParTerminateEcpMode( Pdx );
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if( NT_SUCCESS(Status) ) {
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Pdx->ProtocolModesSupported |= ECP_SW;
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return TRUE;
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} else {
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return FALSE;
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}
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}
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BOOLEAN
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ParIsEcpSwReadSupported(
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IN PPDO_EXTENSION Pdx
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)
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/*++
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Routine Description:
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This routine determines whether or not ECP mode is suported
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in the read direction (need to be able to float the data register
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drivers in order to do byte wide reads) by trying negotiate when asked.
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Arguments:
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Pdx - The device extension.
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Return Value:
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BOOLEAN.
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--*/
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{
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NTSTATUS Status;
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if( !(Pdx->HardwareCapabilities & PPT_ECP_PRESENT) &&
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!(Pdx->HardwareCapabilities & PPT_BYTE_PRESENT) ) {
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// Only use ECP Software in the reverse direction if an
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// ECR is present or we know that we can put the data register into Byte mode.
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return FALSE;
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}
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if (Pdx->BadProtocolModes & ECP_SW)
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return FALSE;
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if (Pdx->ProtocolModesSupported & ECP_SW)
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return TRUE;
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// Must use SWECP Enter and Terminate for this test.
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// Internel state machines will fail otherwise. --dvrh
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Status = ParEnterEcpSwMode (Pdx, FALSE);
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ParTerminateEcpMode (Pdx);
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if (NT_SUCCESS(Status)) {
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Pdx->ProtocolModesSupported |= ECP_SW;
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return TRUE;
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}
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return FALSE;
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}
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NTSTATUS
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ParEnterEcpSwMode(
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IN PPDO_EXTENSION Pdx,
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IN BOOLEAN DeviceIdRequest
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)
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/*++
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Routine Description:
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This routine performs 1284 negotiation with the peripheral to the
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ECP mode protocol.
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Arguments:
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Controller - Supplies the port address.
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DeviceIdRequest - Supplies whether or not this is a request for a device id.
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Return Value:
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STATUS_SUCCESS - Successful negotiation.
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otherwise - Unsuccessful negotiation.
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--*/
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{
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NTSTATUS status = STATUS_SUCCESS;
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if( Pdx->ModeSafety == SAFE_MODE ) {
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if( DeviceIdRequest ) {
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status = IeeeEnter1284Mode( Pdx, ECP_EXTENSIBILITY | DEVICE_ID_REQ );
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} else {
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status = IeeeEnter1284Mode( Pdx, ECP_EXTENSIBILITY );
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}
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} else {
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DD((PCE)Pdx,DDT,"ParEnterEcpSwMode: In UNSAFE_MODE\n");
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Pdx->Connected = TRUE;
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}
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if( NT_SUCCESS(status) ) {
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status = ParEcpSetupPhase( Pdx );
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}
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return status;
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}
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VOID
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ParCleanupSwEcpPort(
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IN PPDO_EXTENSION Pdx
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)
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/*++
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Routine Description:
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Cleans up prior to a normal termination from ECP mode. Puts the
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port HW back into Compatibility mode.
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Arguments:
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Controller - Supplies the parallel port's controller address.
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Return Value:
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None.
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--*/
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{
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PUCHAR Controller;
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UCHAR dcr; // Contents of DCR
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Controller = Pdx->Controller;
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//----------------------------------------------------------------------
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// Set data bus for output
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//----------------------------------------------------------------------
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dcr = P5ReadPortUchar(Controller + OFFSET_DCR); // Get content of DCR
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dcr = UPDATE_DCR( dcr, DIR_WRITE, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE );
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P5WritePortUchar( Controller + OFFSET_DCR, dcr );
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return;
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}
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VOID
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ParTerminateEcpMode(
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IN PPDO_EXTENSION Pdx
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)
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/*++
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Routine Description:
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This routine terminates the interface back to compatibility mode.
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Arguments:
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Controller - Supplies the parallel port's controller address.
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Return Value:
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None.
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--*/
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{
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ParCleanupSwEcpPort(Pdx);
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if ( Pdx->ModeSafety == SAFE_MODE ) {
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IeeeTerminate1284Mode (Pdx);
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} else {
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DD((PCE)Pdx,DDT,"ParTerminateEcpMode: In UNSAFE_MODE\n");
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Pdx->Connected = FALSE;
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}
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return;
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}
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NTSTATUS
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ParEcpSetAddress(
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IN PPDO_EXTENSION Pdx,
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IN UCHAR Address
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)
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/*++
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Routine Description:
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Sets the ECP Address.
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Arguments:
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Pdx - Supplies the device extension.
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Address - The bus address to be set.
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Return Value:
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None.
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--*/
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{
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PUCHAR Controller;
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PUCHAR DCRController;
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UCHAR dcr;
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DD((PCE)Pdx,DDT,"ParEcpSetAddress: Start: Channel [%x]\n", Address);
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Controller = Pdx->Controller;
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DCRController = Controller + OFFSET_DCR;
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//
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// Event 34
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//
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// HostAck low indicates a command byte
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Pdx->CurrentEvent = 34;
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dcr = P5ReadPortUchar(DCRController);
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dcr = UPDATE_DCR( dcr, DIR_WRITE, DONT_CARE, DONT_CARE, DONT_CARE, INACTIVE, DONT_CARE );
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P5WritePortUchar(DCRController, dcr);
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// Place the channel address on the bus
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// Bit 7 of the byte sent must be 1 to indicate that this is an address
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// instead of run length count.
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//
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P5WritePortUchar(Controller + DATA_OFFSET, (UCHAR)(Address | 0x80));
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//
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// Event 35
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//
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// Start handshake by dropping HostClk
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Pdx->CurrentEvent = 35;
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dcr = UPDATE_DCR( dcr, DIR_WRITE, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, INACTIVE );
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P5WritePortUchar(DCRController, dcr);
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// =============== Periph State 36 ===============8
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// PeriphAck/PtrBusy = High (signals state 36)
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// PeriphClk/PtrClk = Don't Care
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// nAckReverse/AckDataReq = Don't Care
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// XFlag = Don't Care
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// nPeriphReq/nDataAvail = Don't Care
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Pdx->CurrentEvent = 35;
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if (!CHECK_DSR(Controller,
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ACTIVE, DONT_CARE, DONT_CARE,
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DONT_CARE, DONT_CARE,
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DEFAULT_RECEIVE_TIMEOUT))
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{
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DD((PCE)Pdx,DDE,"ECP::SendChannelAddress:State 36 Failed: Controller %x\n", Controller);
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// Make sure both HostAck and HostClk are high before leaving
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// HostClk should be high in forward transfer except when handshaking
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// HostAck should be high to indicate that what follows is data (not commands)
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//
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dcr = UPDATE_DCR( dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE, ACTIVE );
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P5WritePortUchar(DCRController, dcr);
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return STATUS_IO_DEVICE_ERROR;
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}
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//
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// Event 37
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//
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// Finish handshake by raising HostClk
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// HostClk is high when it's 0
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//
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Pdx->CurrentEvent = 37;
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dcr = UPDATE_DCR( dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE );
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P5WritePortUchar(DCRController, dcr);
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// =============== Periph State 32 ===============8
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// PeriphAck/PtrBusy = Low (signals state 32)
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// PeriphClk/PtrClk = Don't Care
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// nAckReverse/AckDataReq = Don't Care
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// XFlag = Don't Care
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// nPeriphReq/nDataAvail = Don't Care
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Pdx->CurrentEvent = 32;
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if (!CHECK_DSR(Controller,
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INACTIVE, DONT_CARE, DONT_CARE,
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DONT_CARE, DONT_CARE,
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DEFAULT_RECEIVE_TIMEOUT))
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{
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DD((PCE)Pdx,DDE,"ECP::SendChannelAddress:State 32 Failed: Controller %x\n", Controller);
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// Make sure both HostAck and HostClk are high before leaving
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// HostClk should be high in forward transfer except when handshaking
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// HostAck should be high to indicate that what follows is data (not commands)
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//
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dcr = UPDATE_DCR( dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE, ACTIVE );
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P5WritePortUchar(DCRController, dcr);
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return STATUS_IO_DEVICE_ERROR;
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}
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// Make sure both HostAck and HostClk are high before leaving
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// HostClk should be high in forward transfer except when handshaking
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// HostAck should be high to indicate that what follows is data (not commands)
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//
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dcr = UPDATE_DCR( dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE, ACTIVE );
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P5WritePortUchar(DCRController, dcr);
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DD((PCE)Pdx,DDT,"ParEcpSetAddress, Exit [%d]\n", NT_SUCCESS(STATUS_SUCCESS));
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return STATUS_SUCCESS;
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}
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NTSTATUS
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ParEcpSwWrite(
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IN PPDO_EXTENSION Pdx,
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IN PVOID Buffer,
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IN ULONG BufferSize,
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OUT PULONG BytesTransferred
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)
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/*++
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Routine Description:
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Writes data to the peripheral using the ECP protocol under software
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control.
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Arguments:
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Pdx - Supplies the device extension.
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Buffer - Supplies the buffer to write from.
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BufferSize - Supplies the number of bytes in the buffer.
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BytesTransferred - Returns the number of bytes transferred.
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Return Value:
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None.
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--*/
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{
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PUCHAR Controller;
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NTSTATUS Status = STATUS_SUCCESS;
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PUCHAR pBuffer;
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LARGE_INTEGER Timeout;
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LARGE_INTEGER StartWrite;
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LARGE_INTEGER Wait;
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LARGE_INTEGER Start;
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LARGE_INTEGER End;
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UCHAR dsr;
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UCHAR dcr;
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ULONG i = 0;
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Controller = Pdx->Controller;
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pBuffer = Buffer;
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Status = ParTestEcpWrite(Pdx);
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if( !NT_SUCCESS(Status) ) {
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P5SetPhase( Pdx, PHASE_UNKNOWN );
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Pdx->Connected = FALSE;
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DD((PCE)Pdx,DDE,"ParEcpSwWrite: Invalid Entry State\n");
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goto ParEcpSwWrite_ExitLabel;
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}
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Wait.QuadPart = DEFAULT_RECEIVE_TIMEOUT * 10 * 1000 + KeQueryTimeIncrement();
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Timeout.QuadPart = Pdx->AbsoluteOneSecond.QuadPart * Pdx->TimerStart;
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KeQueryTickCount(&StartWrite);
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dcr = GetControl (Controller);
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// clear direction bit - enable output
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dcr &= ~(DCR_DIRECTION);
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StoreControl(Controller, dcr);
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KeStallExecutionProcessor(1);
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for (i = 0; i < BufferSize; i++) {
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//
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// Event 34
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//
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Pdx->CurrentEvent = 34;
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P5WritePortUchar(Controller + DATA_OFFSET, *pBuffer++);
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//
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// Event 35
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//
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Pdx->CurrentEvent = 35;
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dcr &= ~DCR_AUTOFEED;
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dcr |= DCR_STROBE;
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StoreControl (Controller, dcr);
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//
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// Waiting for Event 36
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//
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Pdx->CurrentEvent = 36;
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while (TRUE) {
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KeQueryTickCount(&End);
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dsr = GetStatus(Controller);
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if (!(dsr & DSR_NOT_BUSY)) {
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break;
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}
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if ((End.QuadPart - StartWrite.QuadPart) *
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KeQueryTimeIncrement() > Timeout.QuadPart) {
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dsr = GetStatus(Controller);
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if (!(dsr & DSR_NOT_BUSY)) {
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break;
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}
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//
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// Return the device to Idle.
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//
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dcr &= ~(DCR_STROBE);
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StoreControl (Controller, dcr);
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*BytesTransferred = i;
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Pdx->log.SwEcpWriteCount += *BytesTransferred;
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return STATUS_DEVICE_BUSY;
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}
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}
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//
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// Event 37
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//
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Pdx->CurrentEvent = 37;
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dcr &= ~DCR_STROBE;
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StoreControl (Controller, dcr);
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//
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// Waiting for Event 32
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//
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Pdx->CurrentEvent = 32;
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KeQueryTickCount(&Start);
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while (TRUE) {
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KeQueryTickCount(&End);
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dsr = GetStatus(Controller);
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if (dsr & DSR_NOT_BUSY) {
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break;
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}
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if ((End.QuadPart - Start.QuadPart) * KeQueryTimeIncrement() >
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Wait.QuadPart) {
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dsr = GetStatus(Controller);
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if (dsr & DSR_NOT_BUSY) {
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break;
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}
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#if DVRH_BUS_RESET_ON_ERROR
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BusReset(Controller+OFFSET_DCR); // Pass in the dcr address
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#endif
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*BytesTransferred = i;
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Pdx->log.SwEcpWriteCount += *BytesTransferred;
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return STATUS_IO_DEVICE_ERROR;
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}
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}
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}
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ParEcpSwWrite_ExitLabel:
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*BytesTransferred = i;
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Pdx->log.SwEcpWriteCount += *BytesTransferred;
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return Status;
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}
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NTSTATUS
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ParEcpSwRead(
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IN PPDO_EXTENSION Pdx,
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IN PVOID Buffer,
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IN ULONG BufferSize,
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OUT PULONG BytesTransferred
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)
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/*++
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Routine Description:
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This routine performs a 1284 ECP mode read under software control
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into the given buffer for no more than 'BufferSize' bytes.
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Arguments:
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Pdx - Supplies the device extension.
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Buffer - Supplies the buffer to read into.
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BufferSize - Supplies the number of bytes in the buffer.
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BytesTransferred - Returns the number of bytes transferred.
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--*/
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{
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PUCHAR Controller;
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PUCHAR pBuffer;
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USHORT usTime;
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UCHAR dcr;
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ULONG i;
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UCHAR ecr = 0;
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Controller = Pdx->Controller;
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pBuffer = Buffer;
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dcr = GetControl (Controller);
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P5SetPhase( Pdx, PHASE_REVERSE_XFER );
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//
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// Put ECR into PS/2 mode and float the drivers.
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//
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if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
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// Save off the ECR register
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ecr = P5ReadPortUchar(Controller + ECR_OFFSET);
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}
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dcr |= DCR_DIRECTION;
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StoreControl (Controller, dcr);
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KeStallExecutionProcessor(1);
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for (i = 0; i < BufferSize; i++) {
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// dvtw - READ TIMEOUTS
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//
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// If it is the first byte then give it more time
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//
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if (!(GetStatus (Controller) & DSR_NOT_FAULT) || i == 0) {
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usTime = DEFAULT_RECEIVE_TIMEOUT;
|
||
|
||
} else {
|
||
|
||
usTime = IEEE_MAXTIME_TL;
|
||
}
|
||
|
||
// *************** State 43 Reverse Phase ***************8
|
||
// PeriphAck/PtrBusy = DONT CARE
|
||
// PeriphClk/PtrClk = LOW ( State 43 )
|
||
// nAckReverse/AckDataReq = LOW
|
||
// XFlag = HIGH
|
||
// nPeriphReq/nDataAvail = DONT CARE
|
||
|
||
Pdx->CurrentEvent = 43;
|
||
if (!CHECK_DSR(Controller, DONT_CARE, INACTIVE, INACTIVE, ACTIVE, DONT_CARE,
|
||
usTime)) {
|
||
|
||
P5SetPhase( Pdx, PHASE_UNKNOWN );
|
||
|
||
dcr &= ~DCR_DIRECTION;
|
||
StoreControl (Controller, dcr);
|
||
|
||
// restore ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
*BytesTransferred = i;
|
||
Pdx->log.SwEcpReadCount += *BytesTransferred;
|
||
return STATUS_IO_DEVICE_ERROR;
|
||
|
||
}
|
||
|
||
// *************** State 44 Setup Phase ***************8
|
||
// DIR = DONT CARE
|
||
// IRQEN = DONT CARE
|
||
// 1284/SelectIn = DONT CARE
|
||
// nReverseReq/**(ECP only)= DONT CARE
|
||
// HostAck/HostBusy = HIGH ( State 44 )
|
||
// HostClk/nStrobe = DONT CARE
|
||
//
|
||
Pdx->CurrentEvent = 44;
|
||
dcr = P5ReadPortUchar(Controller + OFFSET_DCR);
|
||
dcr = UPDATE_DCR(dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, ACTIVE, DONT_CARE);
|
||
P5WritePortUchar(Controller + OFFSET_DCR, dcr);
|
||
|
||
// *************** State 45 Reverse Phase ***************8
|
||
// PeriphAck/PtrBusy = DONT CARE
|
||
// PeriphClk/PtrClk = HIGH ( State 45 )
|
||
// nAckReverse/AckDataReq = LOW
|
||
// XFlag = HIGH
|
||
// nPeriphReq/nDataAvail = DONT CARE
|
||
Pdx->CurrentEvent = 45;
|
||
if (!CHECK_DSR(Controller, DONT_CARE, ACTIVE, INACTIVE, ACTIVE, DONT_CARE,
|
||
IEEE_MAXTIME_TL)) {
|
||
|
||
P5SetPhase( Pdx, PHASE_UNKNOWN );
|
||
|
||
dcr &= ~DCR_DIRECTION;
|
||
StoreControl (Controller, dcr);
|
||
|
||
// restore ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
*BytesTransferred = i;
|
||
Pdx->log.SwEcpReadCount += *BytesTransferred;
|
||
return STATUS_IO_DEVICE_ERROR;
|
||
|
||
}
|
||
|
||
//
|
||
// Read the data
|
||
//
|
||
*pBuffer = P5ReadPortUchar (Controller + DATA_OFFSET);
|
||
pBuffer++;
|
||
|
||
// *************** State 46 Setup Phase ***************8
|
||
// DIR = DONT CARE
|
||
// IRQEN = DONT CARE
|
||
// 1284/SelectIn = DONT CARE
|
||
// nReverseReq/**(ECP only)= DONT CARE
|
||
// HostAck/HostBusy = LOW ( State 46 )
|
||
// HostClk/nStrobe = DONT CARE
|
||
//
|
||
Pdx->CurrentEvent = 46;
|
||
dcr = P5ReadPortUchar(Controller + OFFSET_DCR);
|
||
dcr = UPDATE_DCR(dcr, DONT_CARE, DONT_CARE, DONT_CARE, DONT_CARE, INACTIVE, DONT_CARE);
|
||
P5WritePortUchar(Controller + OFFSET_DCR, dcr);
|
||
|
||
}
|
||
|
||
P5SetPhase( Pdx, PHASE_REVERSE_IDLE );
|
||
|
||
dcr &= ~DCR_DIRECTION;
|
||
StoreControl (Controller, dcr);
|
||
|
||
// restore ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
*BytesTransferred = i;
|
||
Pdx->log.SwEcpReadCount += *BytesTransferred;
|
||
return STATUS_SUCCESS;
|
||
|
||
}
|
||
|
||
NTSTATUS
|
||
ParEcpForwardToReverse(
|
||
IN PPDO_EXTENSION Pdx
|
||
)
|
||
|
||
/*++
|
||
|
||
Routine Description:
|
||
|
||
This routine reverses the channel (ECP).
|
||
|
||
Arguments:
|
||
|
||
Pdx - Supplies the device extension.
|
||
|
||
--*/
|
||
|
||
{
|
||
PUCHAR Controller;
|
||
LARGE_INTEGER Wait35ms;
|
||
LARGE_INTEGER Start;
|
||
LARGE_INTEGER End;
|
||
UCHAR dsr;
|
||
UCHAR dcr;
|
||
UCHAR ecr;
|
||
|
||
Controller = Pdx->Controller;
|
||
|
||
Wait35ms.QuadPart = 10*35*1000 + KeQueryTimeIncrement();
|
||
|
||
dcr = GetControl (Controller);
|
||
|
||
//
|
||
// Put ECR into PS/2 mode to flush the FIFO.
|
||
//
|
||
|
||
// Save off the ECR register
|
||
|
||
// Note: Don't worry about checking to see if it's
|
||
// safe to touch the ecr since we've already checked
|
||
// that before we allowed this mode to be activated.
|
||
ecr = P5ReadPortUchar(Controller + ECR_OFFSET);
|
||
|
||
//
|
||
// Event 38
|
||
//
|
||
Pdx->CurrentEvent = 38;
|
||
dcr |= DCR_AUTOFEED;
|
||
StoreControl (Controller, dcr);
|
||
KeStallExecutionProcessor(1);
|
||
|
||
//
|
||
// Event 39
|
||
//
|
||
Pdx->CurrentEvent = 39;
|
||
dcr &= ~DCR_NOT_INIT;
|
||
StoreControl (Controller, dcr);
|
||
|
||
//
|
||
// Wait for Event 40
|
||
//
|
||
Pdx->CurrentEvent = 40;
|
||
KeQueryTickCount(&Start);
|
||
while (TRUE) {
|
||
|
||
KeQueryTickCount(&End);
|
||
|
||
dsr = GetStatus(Controller);
|
||
if (!(dsr & DSR_PERROR)) {
|
||
break;
|
||
}
|
||
|
||
if ((End.QuadPart - Start.QuadPart) * KeQueryTimeIncrement() > Wait35ms.QuadPart) {
|
||
|
||
dsr = GetStatus(Controller);
|
||
if (!(dsr & DSR_PERROR)) {
|
||
break;
|
||
}
|
||
#if DVRH_BUS_RESET_ON_ERROR
|
||
BusReset(Controller+OFFSET_DCR); // Pass in the dcr address
|
||
#endif
|
||
// restore the ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
DD((PCE)Pdx,DDE,"ParEcpForwardToReverse: Failed to get State 40\n");
|
||
return STATUS_IO_DEVICE_ERROR;
|
||
}
|
||
}
|
||
|
||
// restore the ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
P5SetPhase( Pdx, PHASE_REVERSE_IDLE );
|
||
return STATUS_SUCCESS;
|
||
|
||
}
|
||
|
||
NTSTATUS
|
||
ParEcpReverseToForward(
|
||
IN PPDO_EXTENSION Pdx
|
||
)
|
||
/*++
|
||
|
||
Routine Description:
|
||
|
||
This routine puts the channel back into forward mode (ECP).
|
||
|
||
Arguments:
|
||
|
||
Pdx - Supplies the device extension.
|
||
|
||
--*/
|
||
{
|
||
PUCHAR Controller;
|
||
LARGE_INTEGER Wait35ms;
|
||
LARGE_INTEGER Start;
|
||
LARGE_INTEGER End;
|
||
UCHAR dsr;
|
||
UCHAR dcr;
|
||
UCHAR ecr;
|
||
|
||
Controller = Pdx->Controller;
|
||
|
||
Wait35ms.QuadPart = 10*35*1000 + KeQueryTimeIncrement();
|
||
|
||
dcr = GetControl (Controller);
|
||
|
||
//
|
||
// Put ECR into PS/2 mode to flush the FIFO.
|
||
//
|
||
|
||
// Save off the ECR register
|
||
|
||
// Note: Don't worry about checking to see if it's
|
||
// safe to touch the ecr since we've already checked
|
||
// that before we allowed this mode to be activated.
|
||
ecr = P5ReadPortUchar(Controller + ECR_OFFSET);
|
||
|
||
//
|
||
// Event 47
|
||
//
|
||
Pdx->CurrentEvent = 47;
|
||
dcr |= DCR_NOT_INIT;
|
||
StoreControl (Controller, dcr);
|
||
|
||
//
|
||
// Wait for Event 49
|
||
//
|
||
Pdx->CurrentEvent = 49;
|
||
KeQueryTickCount(&Start);
|
||
while (TRUE) {
|
||
|
||
KeQueryTickCount(&End);
|
||
|
||
dsr = GetStatus(Controller);
|
||
if (dsr & DSR_PERROR) {
|
||
break;
|
||
}
|
||
|
||
if ((End.QuadPart - Start.QuadPart) * KeQueryTimeIncrement() >
|
||
Wait35ms.QuadPart) {
|
||
|
||
dsr = GetStatus(Controller);
|
||
if (dsr & DSR_PERROR) {
|
||
break;
|
||
}
|
||
#if DVRH_BUS_RESET_ON_ERROR
|
||
BusReset(Controller+OFFSET_DCR); // Pass in the dcr address
|
||
#endif
|
||
// Restore the ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
DD((PCE)Pdx,DDE,"ParEcpReverseToForward: Failed to get State 49\n");
|
||
return STATUS_IO_DEVICE_ERROR;
|
||
}
|
||
}
|
||
|
||
// restore the ecr register
|
||
if (Pdx->HardwareCapabilities & PPT_ECP_PRESENT) {
|
||
P5WritePortUchar(Controller + ECR_OFFSET, ecr);
|
||
}
|
||
|
||
P5SetPhase( Pdx, PHASE_FORWARD_IDLE );
|
||
return STATUS_SUCCESS;
|
||
}
|