327 lines
11 KiB
PHP
327 lines
11 KiB
PHP
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;/*
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;++
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;
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; Copyright (c) 1992 Intel Corporation
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; All rights reserved
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;
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; INTEL CORPORATION PROPRIETARY INFORMATION
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;
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; This software is supplied to Microsoft under the terms
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; of a license agreement with Intel Corporation and may not be
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; copied nor disclosed except in accordance with the terms
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; of that agreement.
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;
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;
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; Module Name:
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;
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; apic.inc
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;
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; Abstract:
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;
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; This module contains the definitions used by HAL to manipulate
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; APIC interrupt controller and APIC-specific constants.
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;
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; WARNING: This file is included by both ASM and C files.
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;
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; Author:
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;
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; Hugh Bynum and Ron Mosgrove Aug-1992
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;
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;--
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if 0 ; Begin C only code */
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typedef volatile ULONG *PVULONG;
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//
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// APIC Version Register (both IO Unit and Local Units)
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//
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struct ApicVersion {
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UCHAR Version; // either 0.x or 1.x
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UCHAR Reserved1;
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UCHAR MaxRedirEntries; // Number of INTIs on unit
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UCHAR Reserved2;
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};
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typedef struct ApicVersion APIC_VERSION, *PAPIC_VERSION;
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//
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// IO Unit definition
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//
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struct ApicIoUnit {
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volatile ULONG RegisterSelect; // Write register number to access register
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volatile ULONG Reserved1[3];
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volatile ULONG RegisterWindow; // Data read/written here
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};
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typedef struct ApicIoUnit IO_APIC_UNIT, *PIO_APIC_UNIT;
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//
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// APIC defines for C code
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// BE SURE TO CHANGE THESE VALUES IN BOTH TABLES!
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//
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//
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// Default Physical addresses of the APICs in a PC+MP system
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//
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#define IO_BASE_ADDRESS 0xFEC00000 // Default address of
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// 1st IO Apic
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#define LU_BASE_ADDRESS 0xFEE00000 // Default address
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// of Local Apic
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#define IO_REGISTER_SELECT 0x00000000 //
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#define IO_REGISTER_WINDOW 0x00000010 //
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#define IO_ID_REGISTER 0x00000000
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#define IO_VERS_REGISTER 0x00000001
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#define IO_ARB_ID_REGISTER 0x00000002
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#define IO_REDIR_00_LOW 0x00000010
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#define IO_REDIR_00_HIGH 0x00000011
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#define IO_MAX_REDIR_MASK 0x00FF0000
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#define IO_VERSION_MASK 0x000000FF
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#define LU_ID_REGISTER 0x00000020 //
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#define LU_VERS_REGISTER 0x00000030 //
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#define LU_TPR 0x00000080 //
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#define LU_APR 0x00000090 //
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#define LU_PPR 0x000000A0 //
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#define LU_EOI 0x000000B0 //
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#define LU_REMOTE_REGISTER 0x000000C0 //
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#define LU_LOGICAL_DEST 0x000000D0 //
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#define LU_LOGICAL_DEST_MASK 0xFF000000
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#define LU_DEST_FORMAT 0x000000E0 //
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#define LU_DEST_FORMAT_MASK 0xF0000000
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#define LU_DEST_FORMAT_FLAT 0xFFFFFFFF
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#define LU_DEST_FORMAT_CLUSTER 0x0FFFFFFF
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#define LU_SPURIOUS_VECTOR 0x000000F0 //
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#define LU_FAULT_VECTOR 0x00000370 //
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#define LU_UNIT_ENABLED 0x00000100
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#define LU_UNIT_DISABLED 0x00000000
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#define LU_ISR_0 0x00000100 //
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#define LU_TMR_0 0x00000180 //
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#define LU_IRR_0 0x00000200 //
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#define LU_ERROR_STATUS 0x00000280 //
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#define LU_INT_CMD_LOW 0x00000300 //
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#define LU_INT_CMD_HIGH 0x00000310 //
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#define LU_TIMER_VECTOR 0x00000320 //
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#define LU_PERF_VECTOR 0x00000340
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#define LU_INT_VECTOR_0 0x00000350 // TEMPORARY - do not use
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#define LU_INT_VECTOR_1 0x00000360 // TEMPORARY - do not use
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#define LU_INITIAL_COUNT 0x00000380 //
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#define LU_CURRENT_COUNT 0x00000390 //
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#define LU_DIVIDER_CONFIG 0x000003E0 //
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#define LU_DIVIDE_BY_1 0x0000000B //
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#define APIC_ID_MASK 0xFF000000
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#define APIC_ID_SHIFT 24
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#define INT_VECTOR_MASK 0x000000FF
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#define RESERVED_HIGH_INT 0x000000F8
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#define DELIVERY_MODE_MASK 0x00000700
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#define DELIVER_FIXED 0x00000000
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#define DELIVER_LOW_PRIORITY 0x00000100
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#define DELIVER_SMI 0x00000200
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#define DELIVER_REMOTE_READ 0x00000300
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#define DELIVER_NMI 0x00000400
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#define DELIVER_INIT 0x00000500
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#define DELIVER_STARTUP 0x00000600
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#define DELIVER_EXTINT 0x00000700
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#define PHYSICAL_DESTINATION 0x00000000
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#define LOGICAL_DESTINATION 0x00000800
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#define DELIVERY_PENDING 0x00001000
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#define ACTIVE_LOW 0x00002000
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#define ACTIVE_HIGH 0x00000000
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#define REMOTE_IRR 0x00004000
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#define LEVEL_TRIGGERED 0x00008000
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#define EDGE_TRIGGERED 0x00000000
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#define INTERRUPT_MASKED 0x00010000
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#define INTERRUPT_MOT_MASKED 0x00000000
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#define PERIODIC_TIMER 0x00020000
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#define ICR_LEVEL_ASSERTED 0x00004000
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#define ICR_LEVEL_DEASSERTED 0x00000000
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#define ICR_RR_STATUS_MASK 0x00030000
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#define ICR_RR_INVALID 0x00000000
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#define ICR_RR_IN_PROGRESS 0x00010000
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#define ICR_RR_VALID 0x00020000
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#define ICR_SHORTHAND_MASK 0x000C0000
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#define ICR_USE_DEST_FIELD 0x00000000
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#define ICR_SELF 0x00040000
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#define ICR_ALL_INCL_SELF 0x00080000
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#define ICR_ALL_EXCL_SELF 0x000C0000
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//
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// Special ICR request to reset a remote processor
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//
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#define LU_RESET_ASSERT ( DELIVER_INIT | LEVEL_TRIGGERED | ICR_LEVEL_ASSERTED | \
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ICR_USE_DEST_FIELD | PHYSICAL_DESTINATION)
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#define LU_RESET_DEASSERT ( DELIVER_INIT | LEVEL_TRIGGERED | ICR_LEVEL_DEASSERTED | \
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ICR_USE_DEST_FIELD | PHYSICAL_DESTINATION)
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//
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// Special ICR request to reset a remote processor
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//
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#define LU_INIT_DEASSERT (DELIVER_INIT | LEVEL_TRIGGERED | \
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ICR_ALL_INCL_SELF | ICR_LEVEL_DEASSERTED )
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//
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// Startup ICR Requset - OR in the VV value needed
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//
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#define LU_STARTUP_IPI ( DELIVER_STARTUP | ICR_USE_DEST_FIELD | \
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PHYSICAL_DESTINATION)
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#define DESTINATION_MASK 0xFF000000
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#define DESTINATION_SHIFT 24
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//
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// APIC IO unit redirection table, interrupt destination field: this field
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// is 32 bits for the 82489DX APIC; future APIC implementations will put the
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// destination field in the upper 8 bits of the entry, not the full 32 bits
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//
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#define DESTINATION_CPU_0 (ULONG) (1 << DESTINATION_SHIFT)
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#define DESTINATION_ALL_CPUS (ULONG) (0xff << DESTINATION_SHIFT)
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//
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// Io Apic Entry definitions
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//
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// Interrupt Types Possible in the PC+MP Table
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// valid for both local and Io Apics
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//
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#define INT_TYPE_INTR 0x0
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#define INT_TYPE_NMI 0x1
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#define INT_TYPE_SMI 0x2
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#define INT_TYPE_EXTINT 0x3
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/*
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endif
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; APIC defines for assembly code
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; BE SURE TO CHANGE THESE VALUES IN BOTH TABLES!
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;
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;
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; Default Physical addresses of the APICs in a PC+MP system
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;
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IO_BASE_ADDRESS equ 0FEC00000H ; Default address of
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; 1st IO Apic
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LU_BASE_ADDRESS equ 0FEE00000H ; Default address
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; of Local Apic
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IO_REGISTER_SELECT equ 00000000H ;
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IO_REGISTER_WINDOW equ 00000010H ;
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IO_ID_REGISTER equ 00000000H ;
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IO_VERS_REGISTER equ 00000001H ;
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IO_ARB_ID_REGISTER equ 00000002H ;
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IO_REDIR_00_LOW equ 00000010H ;
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IO_REDIR_00_HIGH equ 00000011H ;
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IO_MAX_REDIR_MASK equ 00FF0000H ;
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IO_VERSION_MASK equ 000000FFH ;
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LU_ID_REGISTER equ 00000020H ;
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LU_VERS_REGISTER equ 00000030H ;
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LU_TPR equ 00000080H ;
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LU_APR equ 00000090H ;
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LU_PPR equ 000000A0H ;
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LU_EOI equ 000000B0H ;
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LU_REMOTE_REGISTER equ 000000C0H ;
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LU_LOGICAL_DEST equ 000000D0H ;
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LU_LOGICAL_DEST_MASK equ 0FF000000H ;
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LU_DEST_FORMAT equ 000000E0H ;
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LU_DEST_FORMAT_MASK equ 0F0000000H ;
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LU_DEST_FORMAT_FLAT equ 0FFFFFFFFH ;
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LU_DEST_FORMAT_CLUSTER equ 0FFFFFFFH
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LU_SPURIOUS_VECTOR equ 000000F0H ;
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LU_FAULT_VECTOR equ 00000370H ;
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LU_UNIT_ENABLED equ 00000100H ;
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LU_UNIT_DISABLED equ 00000000H ;
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LU_ISR_0 equ 00000100H ;
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LU_TMR_0 equ 00000180H ;
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LU_IRR_0 equ 00000200H ;
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LU_ERROR_STATUS equ 00000280H ;
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LU_INT_CMD_LOW equ 00000300H ;
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LU_INT_CMD_HIGH equ 00000310H ;
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LU_TIMER_VECTOR equ 00000320H ;
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LU_PERF_VECTOR equ 00000340H ;
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LU_INT_VECTOR_0 equ 00000350H ; TEMPORARY - do not use
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LU_INT_VECTOR_1 equ 00000360H ; TEMPORARY - do not use
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LU_INITIAL_COUNT equ 00000380H ;
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LU_CURRENT_COUNT equ 00000390H ;
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LU_DIVIDER_CONFIG equ 000003E0H ;
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LU_DIVIDE_BY_1 equ 0000000BH ;
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LU_DIVIDE_BY_2 equ 00000000H ;
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LU_DIVIDE_BY_4 equ 00000001H ;
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LU_DIVIDE_BY_8 equ 00000002H ;
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LU_DIVIDE_BY_16 equ 00000003H ;
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LU_DIVIDE_BY_32 equ 00000008H ;
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LU_DIVIDE_BY_64 equ 00000009H ;
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LU_DIVIDE_BY_128 equ 0000000AH ;
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APIC_ID_MASK equ 0FF000000H ;
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APIC_ID_SHIFT equ 24 ;
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INT_VECTOR_MASK equ 000000FFH ;
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RESERVED_HIGH_INT equ 000000F8H ;
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DELIVERY_MODE_MASK equ 00000700H ;
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DELIVER_FIXED equ 00000000H ;
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DELIVER_LOW_PRIORITY equ 00000100H ;
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DELIVER_SMI equ 00000200H ;
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DELIVER_REMOTE_READ equ 00000300H ;
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DELIVER_NMI equ 00000400H ;
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DELIVER_INIT equ 00000500H ;
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DELIVER_STARTUP equ 00000600H ;
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DELIVER_EXTINT equ 00000700H ;
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PHYSICAL_DESTINATION equ 00000000H ;
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LOGICAL_DESTINATION equ 00000800H ;
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DELIVERY_PENDING equ 00001000H ;
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ACTIVE_LOW equ 00002000H ;
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ACTIVE_HIGH equ 00000000H ;
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REMOTE_IRR equ 00004000H ;
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LEVEL_TRIGGERED equ 00008000H ;
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EDGE_TRIGGERED equ 00000000H ;
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INTERRUPT_MASKED equ 00010000H ;
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INTERRUPT_MOT_MASKED equ 00000000H ;
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PERIODIC_TIMER equ 00020000H ;
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ICR_LEVEL_ASSERTED equ 00004000H ;
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ICR_LEVEL_DEASSERTED equ 00000000H ;
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ICR_RR_STATUS_MASK equ 00030000H ;
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ICR_RR_INVALID equ 00000000H ;
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ICR_RR_IN_PROGRESS equ 00010000H ;
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ICR_RR_VALID equ 00020000H ;
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ICR_SHORTHAND_MASK equ 000C0000H ;
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ICR_USE_DEST_FIELD equ 00000000H ;
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ICR_SELF equ 00040000H ;
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ICR_ALL_INCL_SELF equ 00080000H ;
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ICR_ALL_EXCL_SELF equ 000C0000H ;
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DESTINATION_MASK equ 0FF000000H ;
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DESTINATION_SHIFT equ 24 ; shift count for dest. mask
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;
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; APIC IO unit redirection table, interrupt destination field: this field
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; is 32 bits for the 82489DX APIC; future APIC implementations will put the
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; destination field in the upper 8 bits of the entry, not the full 32 bits
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;
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DESTINATION_CPU_0 equ 1 SHL DESTINATION_SHIFT
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DESTINATION_ALL_CPUS equ 0FFH SHL DESTINATION_SHIFT
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;
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; Interrupt Types Possible in the PC+MP Table
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;
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INT_TYPE_INTR equ 0H
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INT_TYPE_NMI equ 01H
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INT_TYPE_SMI equ 02H
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INT_TYPE_EXTINT equ 03H
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;*/
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