23973 lines
1.9 MiB
23973 lines
1.9 MiB
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/* NVidia Corporation */
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/* basis: nv4 manuals
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built on Fri Jan 26 12:29:10 PST 2001*/
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#ifndef _NV_REF_H_
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#define _NV_REF_H_
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#define DEVICE_BASE(d) (0?d)
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#define DEVICE_EXTENT(d) (1?d)
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#define DRF_SHIFT(drf) ((0?drf) % 32)
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#define DRF_MASK(drf) (0xFFFFFFFF>>(31-((1?drf) % 32)+((0?drf) % 32)))
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#define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV ## d ## r ## f))
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#define DRF_NUM(d,r,f,n) (((n)&DRF_MASK(NV ## d ## r ## f))<<DRF_SHIFT(NV ## d ## r ## f))
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#define DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f))
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#define REF_VAL(drf,v) (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf))
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#define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf))
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#define BIT(b) (1<<(b))
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//#define UPDATE_REG(a,b,c,d) ((a)=(~(((a)<<(31-(d))>>(31-(d)+(c)))<<(c))&(a))|((b)<<(c)))
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#define UPDATE_REG(a,b,c,d) ((a)=(~(((a)<<(31-(d))>>(31-(d)+(c)))<<(c))&(a))|((((unsigned int)b)<<(31-(d)+(c)))>>(31-(d))))
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#define GETVAL(a,b,c) (((a)<<(31-(c)))>>(31-(c)+(b)))
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#define DRF_SHIFT_RT(drf) ((1?drf) % 32)
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// The macro below takes defines of the type 7:5 as the bit field for (c)
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// and updates the input (a) similar to UPDATE_REG
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#define UPDATE_VAL(a,b,c) \
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((a)=(~(((a)<<(31-(DRF_SHIFT_RT(c)))>>(31-(DRF_SHIFT_RT(c))+DRF_SHIFT(c)))<< DRF_SHIFT(c))&(a))|((b)<<DRF_SHIFT(c)))
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// Similar to above, allows use of a macro to pick the bit range as in 7:5 for (b)
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#define GETVAL_RANGE(a,b) \
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(((a)<<(31-(DRF_SHIFT_RT(b))))>>(31-(DRF_SHIFT_RT(b))+(DRF_SHIFT(b))))
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/* dev_bus.ref */
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#define NV_SPACE 0x01FFFFFF:0x00000000 /* RW--D */
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/* dev_bus.ref */
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#define NV_TSPACE 0x0007FFFF:0x00000000 /* RW--D */
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/* dev_bus.ref */
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#define NV_MSPACE 0x1FFFFFFF:0x00000000 /* RW--D */
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/* dev_bus.ref */
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#define NV_RSPACE 0x00FFFFFF:0x00000000 /* RW--D */
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/* dev_bus.ref */
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#define NV_CONFIG 0x000000FF:0x00000000 /* RW--D */
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#define NV_CONFIG_PCI_NV_32 0x00000080 /* R--4R */
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#define NV_CONFIG_PCI_NV_33 0x00000084 /* RW-4R */
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#define NV_CONFIG_PCI_NV_34 0x00000088 /* RW-4R */
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#define NV_CONFIG_PCI_NV_0 0x00000000 /* R--4R */
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#define NV_CONFIG_PCI_NV_0__ALIAS_1 NV_PBUS_PCI_NV_0 /* */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID 31:16 /* C--UF */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV01_A 0x00000009 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV01_B_B02_B03_C01 0x00000008 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV02_A01 0x00000010 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV03_NOACPI 0x00000018 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV03_ACPI 0x00000019 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV04 0x00000020 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV05_DEVID0 0x00000028 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV05_DEVID1 0x00000029 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV05_DEVID2 0x0000002A /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV05_DEVID3 0x0000002B /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV06_DEVID0 0x0000002C /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV06_DEVID1 0x0000002D /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV06_DEVID2 0x0000002E /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV06_DEVID3 0x0000002F /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV0A_DEVID0 0x000000A0 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV0A_DEVID1 0x000000A1 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV0A_DEVID2 0x000000A2 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV0A_DEVID3 0x000000A3 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV10_DEVID0 0x00000100 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV10_DEVID1 0x00000101 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV10_DEVID2 0x00000102 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV10_DEVID3 0x00000103 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV15_DEVID0 0x00000150 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV15_DEVID1 0x00000151 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV15_DEVID2 0x00000152 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV15_DEVID3 0x00000153 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV20_DEVID0 0x00000200 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV20_DEVID1 0x00000201 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV20_DEVID2 0x00000202 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV20_DEVID3 0x00000203 /* ----V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV2A_DEVID0 0x000002A0 /* C---V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV2A_DEVID1 0x000002A1 /* C---V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV2A_DEVID2 0x000002A2 /* C---V */
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#define NV_CONFIG_PCI_NV_0_DEVICE_ID_NV2A_DEVID3 0x000002A3 /* C---V */
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#define NV_CONFIG_PCI_NV_1 0x00000004 /* RW-4R */
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#define NV_CONFIG_PCI_NV_1__ALIAS_1 NV_PBUS_PCI_NV_1 /* */
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#define NV_CONFIG_PCI_NV_2 0x00000008 /* R--4R */
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#define NV_CONFIG_PCI_NV_2__ALIAS_1 NV_PBUS_PCI_NV_2 /* */
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#define NV_CONFIG_PCI_NV_3 0x0000000C /* RW-4R */
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#define NV_CONFIG_PCI_NV_3__ALIAS_1 NV_PBUS_PCI_NV_3 /* */
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#define NV_CONFIG_PCI_NV_4 0x00000010 /* RW-4R */
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#define NV_CONFIG_PCI_NV_4__ALIAS_1 NV_PBUS_PCI_NV_4 /* */
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#define NV_CONFIG_PCI_NV_5 0x00000014 /* RW-4R */
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#define NV_CONFIG_PCI_NV_5__ALIAS_1 NV_PBUS_PCI_NV_5 /* */
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#define NV_CONFIG_PCI_NV_6 0x00000018 /* RW-4R */
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#define NV_CONFIG_PCI_NV_6__ALIAS_1 NV_PBUS_PCI_NV_6 /* */
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#define NV_CONFIG_PCI_NV_7(i) (0x0000001C+(i)*4) /* R--4A */
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#define NV_CONFIG_PCI_NV_7__SIZE_1 4 /* */
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#define NV_CONFIG_PCI_NV_7__ALIAS_1 NV_PBUS_PCI_NV_7 /* */
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#define NV_CONFIG_PCI_NV_11 0x0000002C /* R--4R */
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#define NV_CONFIG_PCI_NV_11__ALIAS_1 NV_PBUS_PCI_NV_11 /* */
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#define NV_CONFIG_PCI_NV_12 0x00000030 /* RW-4R */
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#define NV_CONFIG_PCI_NV_12__ALIAS_1 NV_PBUS_PCI_NV_12 /* */
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#define NV_CONFIG_PCI_NV_13 0x00000034 /* RW-4R */
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#define NV_CONFIG_PCI_NV_13__ALIAS_1 NV_PBUS_PCI_NV_13 /* */
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#define NV_CONFIG_PCI_NV_14 0x00000038 /* R--4R */
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#define NV_CONFIG_PCI_NV_14__ALIAS_1 NV_PBUS_PCI_NV_14 /* */
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#define NV_CONFIG_PCI_NV_15 0x0000003C /* RW-4R */
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#define NV_CONFIG_PCI_NV_15__ALIAS_1 NV_PBUS_PCI_NV_15 /* */
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#define NV_CONFIG_PCI_NV_16 0x00000040 /* RW-4R */
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#define NV_CONFIG_PCI_NV_16__ALIAS_1 NV_PBUS_PCI_NV_16 /* */
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#define NV_CONFIG_PCI_NV_17 0x00000044 /* RW-4R */
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#define NV_CONFIG_PCI_NV_17__ALIAS_1 NV_PBUS_PCI_NV_17 /* */
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#define NV_CONFIG_PCI_NV_18 0x00000048 /* RW-4R */
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#define NV_CONFIG_PCI_NV_18__ALIAS_1 NV_PBUS_PCI_NV_18 /* */
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#define NV_CONFIG_PCI_NV_19 0x0000004C /* RW-4R */
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#define NV_CONFIG_PCI_NV_19__ALIAS_1 NV_PBUS_PCI_NV_19 /* */
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#define NV_CONFIG_PCI_NV_20 0x00000050 /* RW-4R */
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#define NV_CONFIG_PCI_NV_20__ALIAS_1 NV_PBUS_PCI_NV_20 /* */
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#define NV_CONFIG_PCI_NV_21 0x00000054 /* RW-4R */
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#define NV_CONFIG_PCI_NV_21__ALIAS_1 NV_PBUS_PCI_NV_21 /* */
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#define NV_CONFIG_PCI_NV_22 0x00000058 /* RW-4R */
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#define NV_CONFIG_PCI_NV_22__ALIAS_1 NV_PBUS_PCI_NV_22 /* */
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#define NV_CONFIG_PCI_NV_23 0x0000005C /* RW-4R */
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#define NV_CONFIG_PCI_NV_23__ALIAS_1 NV_PBUS_PCI_NV_23 /* */
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#define NV_CONFIG_PCI_NV_24 0x00000060 /* RW-4R */
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#define NV_CONFIG_PCI_NV_24__ALIAS_1 NV_PBUS_PCI_NV_24 /* */
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#define NV_CONFIG_PCI_NV_25 0x00000064 /* RW-4R */
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#define NV_CONFIG_PCI_NV_25__ALIAS_1 NV_PBUS_PCI_NV_25 /* */
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#define NV_CONFIG_PCI_NV_26(i) (0x00000068+(i)*4) /* R--4A */
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#define NV_CONFIG_PCI_NV_26__SIZE_1 38 /* */
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#define NV_CONFIG_PCI_NV_26__ALIAS_1 NV_PBUS_PCI_NV_25 /* */
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/* dev_bus.ref */
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/* dev_bus.ref */
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/* dev_bus.ref */
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#define NV_PRMIO_RMA_ID 0x00007100 /* R--4R */
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#define NV_PRMIO_RMA_ID_CODE 31:0 /* C--UF */
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#define NV_PRMIO_RMA_ID_CODE_VALID 0x2B16D065 /* C---V */
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#define NV_PRMIO_RMA_PTR 0x00007104 /* RW-4R */
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#define NV_PRMIO_RMA_PTR_SPACE 31:31 /* RWIVF */
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#define NV_PRMIO_RMA_PTR_SPACE_REGISTER 0x00000000 /* RWI-V */
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#define NV_PRMIO_RMA_PTR_SPACE_MEMORY 0x00000001 /* RW--V */
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#define NV_PRMIO_RMA_PTR_ADDRESS 28:2 /* RWIUF */
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#define NV_PRMIO_RMA_PTR_ADDRESS_0 0x00000000 /* RWI-V */
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#define NV_PRMIO_RMA_DATA 0x00007108 /* RW-4R */
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#define NV_PRMIO_RMA_DATA_PORT 31:0 /* RWXUF */
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#define NV_PRMIO_RMA_DATA32 0x0000710C /* RW-4R */
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#define NV_PRMIO_RMA_DATA32_BYTE2 23:16 /* RWXUF */
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#define NV_PRMIO_RMA_DATA32_BYTE1 15:8 /* RWXUF */
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#define NV_PRMIO_RMA_DATA32_BYTE0 7:0 /* RWXUF */
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/* dev_bus.ref */
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#define NV_EXPROM 0x0000FFFF:0x00000000 /* R---D */
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#define NV_EXPROM_BIOS_ROM008(i) (0x00000000+(i)) /* RW-1A */
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#define NV_EXPROM_BIOS_ROM008__SIZE_1 65536 /* */
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#define NV_EXPROM_BIOS_ROM008_VALUE 7:0 /* RW-VF */
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#define NV_EXPROM_BIOS_ROM016(i) (0x00000000+(i)*2) /* RW-2A */
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#define NV_EXPROM_BIOS_ROM016__SIZE_1 32768 /* */
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#define NV_EXPROM_BIOS_ROM016_VALUE 15:0 /* RW-VF */
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#define NV_EXPROM_BIOS_ROM032(i) (0x00000000+(i)*4) /* RW-4A */
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#define NV_EXPROM_BIOS_ROM032__SIZE_1 16384 /* */
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#define NV_EXPROM_BIOS_ROM032_VALUE 31:0 /* RW-VF */
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/* dev_bus.ref */
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#define NV_MEMORY 0xFFFFFFFF:0x00000000 /* RW--D */
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/* dev_bus.ref */
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#define NV_IO 0xFFFFFFFF:0x00000000 /* RW--D */
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/* dev_dac.ref */
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#define NV_PRAMDAC 0x00680FFF:0x00680300 /* RW--D */
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#define NV_PRAMDAC_CU_START_POS 0x00680300 /* RW-4R */
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#define NV_PRAMDAC_CU_START_POS_X 11:0 /* RWXSF */
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#define NV_PRAMDAC_CU_START_POS_Y 27:16 /* RWXSF */
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#define NV_PRAMDAC_CURSOR_CNTRL 0x00680320 /* RWI4R */
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#define NV_PRAMDAC_CURSOR_CNTRL_ADDRESS 3:0 /* RW--F */
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#define NV_PRAMDAC_CURSOR_CNTRL_RAM 8:8 /* -W--F */
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#define NV_PRAMDAC_CURSOR_CNTR_TESTMODE 16:16 /* -W--F */
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#define NV_PRAMDAC_CURSOR_CNTR_TESTMODE_ENABLE 1 /* RW--V */
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#define NV_PRAMDAC_CURSOR_CNTR_TESTMODE_DISABLE 0 /* RW--V */
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#define NV_PRAMDAC_CURSOR_DATA_31_0 0x00680324 /* RWI4R */
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#define NV_PRAMDAC_CURSOR_DATA_31_0_VAL 31:0 /* RW--F */
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#define NV_PRAMDAC_CURSOR_DATA_63_32 0x00680328 /* RWI4R */
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#define NV_PRAMDAC_CURSOR_DATA_63_32_VAL 31:0 /* RW--F */
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#define NV_PRAMDAC_CURSOR_DATA_95_64 0x0068032C /* RWI4R */
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#define NV_PRAMDAC_CURSOR_DATA_95_64_VAL 31:0 /* RW--F */
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#define NV_PRAMDAC_CURSOR_DATA_127_96 0x00680330 /* RWI4R */
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#define NV_PRAMDAC_CURSOR_DATA_127_96_VAL 31:0 /* RW--F */
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#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */
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#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */
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#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */
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#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */
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#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */
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#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */
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#define NV_PRAMDAC_VPLL2_COEFF 0x00680520 /* RW-4R */
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#define NV_PRAMDAC_VPLL2_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PRAMDAC_VPLL2_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PRAMDAC_VPLL2_COEFF_PDIV 18:16 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 0:0 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_XTAL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_VIP 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL2_SOURCE 2:2 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL2_SOURCE_XTAL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL2_SOURCE_VIP 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MSOURCE 8:8 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MSOURCE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MSOURCE_PROG 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_V1SOURCE 9:9 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_V1SOURCE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_V1SOURCE_PROG 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_NVSOURCE 10:10 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_NVSOURCE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_NVSOURCE_PROG 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_V2SOURCE 11:11 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_V2SOURCE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_V2SOURCE_PROG 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV 17:16 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_NONE 0x00000000 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_VSCLK 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_PCLK 0x00000002 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK_TV_BOTH 0x00000003 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK2_TV 19:18 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK2_TV_NONE 0x00000000 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK2_TV_VSCLK 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK2_TV_PCLK 0x00000002 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VS_PCLK2_TV_BOTH 0x00000003 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO 24:24 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB1 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_TVCLK_RATIO_DB2 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO 29:29 /* RWIVF */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB1 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510 /* RW-4R */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_VALUE 8:0 /* RWIVF */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_VAL 0x0000011C /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN 15:12 /* RWIVF */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_NONE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_MPLL 0x00000001 /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_VPLL 0x00000002 /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_NVPLL 0x00000004 /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_VPLL2 0x00000008 /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_ALL 0x0000000f /* RW--V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_ON 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_SETUP_CONTROL_PWRDWN_OFF 0x0000000f /* RW--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER 0x00680514 /* RW-4R */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_NOOFIPCLKS 9:0 /* -WIVF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VALUE 15:0 /* R--VF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_ENABLE 16:16 /* RWIVF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_ENABLE_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_ENABLE_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_RESET 20:20 /* RWIVF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_RESET_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE 26:24 /* RWIVF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE_NVCLK 0x00000000 /* RW--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE_VCLK 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE_MCLK 0x00000002 /* RWI-V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_SOURCE_VCLK2 0x00000004 /* -W--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_LOCK 27:27 /* R--VF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_NOTLOCKED 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL2_LOCKED 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_PDIV_RST 28:28 /* RWIVF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_PDIVRST_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCK 29:29 /* R--VF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_NOTLOCKED 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_NVPLL_LOCKED 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCK 30:30 /* R--VF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_NOTLOCKED 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_MPLL_LOCKED 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCK 31:31 /* R--VF */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_NOTLOCKED 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_TEST_COUNTER_VPLL_LOCKED 0x00000001 /* R---V */
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#define NV_PRAMDAC_PALETTE_TEST 0x00680518 /* RW-4R */
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#define NV_PRAMDAC_PALETTE_TEST_BLUE_DATA 7:0 /* R--VF */
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#define NV_PRAMDAC_PALETTE_TEST_GREEN_DATA 15:8 /* R--VF */
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#define NV_PRAMDAC_PALETTE_TEST_RED_DATA 23:16 /* R--VF */
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#define NV_PRAMDAC_PALETTE_TEST_MODE 24:24 /* RWIVF */
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#define NV_PRAMDAC_PALETTE_TEST_MODE_8BIT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PALETTE_TEST_MODE_24BIT 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PALETTE_TEST_ADDRINC 28:28 /* RWIVF */
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#define NV_PRAMDAC_PALETTE_TEST_ADDRINC_READWRITE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PALETTE_TEST_ADDRINC_WRITEONLY 0x00000001 /* RW--V */
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#define NV_PRAMDAC_SEL_CLK 0x00680524 /* RW-4R */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_NVPLL 0:0 /* RWIVF */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_NVPLL_OFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_NVPLL_ON 0x00000001 /* RW--V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_MPLL 2:2 /* RWIVF */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_MPLL_OFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_MPLL_ON 0x00000001 /* RW--V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_VPLL1 4:4 /* RWIVF */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_VPLL1_OFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_VPLL1_ON 0x00000001 /* RW--V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_VPLL2 6:6 /* RWIVF */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_VPLL2_OFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_SEL_CLK_SPREAD_SPECTRUM_VPLL2_ON 0x00000001 /* RW--V */
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#define NV_PRAMDAC_SEL_CLK_IFPCLK1 16:16 /* RWIVF */
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#define NV_PRAMDAC_SEL_CLK_IFPCLK1_SEL_FPCLK1 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_SEL_CLK_IFPCLK1_SEL_FPCLK2 0x00000001 /* RW--V */
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#define NV_PRAMDAC_SEL_CLK_IFPCLK2 18:18 /* RWIVF */
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#define NV_PRAMDAC_SEL_CLK_IFPCLK2_SEL_FPCLK1 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_SEL_CLK_IFPCLK2_SEL_FPCLK2 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT 0x00680528 /* RW-4R */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_MODE 1:0 /* RWIVF */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_MODE_MULTOFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_MODE_AUTO 0x00000002 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_MODE_MULTON 0x00000003 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_STAT 3:3 /* R--VF */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_STAT_OFF 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_NVPLL_DET_STAT_ON 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_MODE 5:4 /* RWIVF */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_MODE_MULTOFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_MODE_AUTO 0x00000002 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_MODE_MULTON 0x00000003 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_STAT 7:7 /* R--VF */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_STAT_OFF 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_MPLL_DET_STAT_ON 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_MODE 9:8 /* RWIVF */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_MODE_MULTOFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_MODE_AUTO 0x00000002 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_MODE_MULTON 0x00000003 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_STAT 11:11 /* R--VF */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_STAT_OFF 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL_DET_STAT_ON 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_MODE 13:12 /* RWIVF */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_MODE_MULTOFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_MODE_AUTO 0x00000002 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_MODE_MULTON 0x00000003 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_STAT 15:15 /* R--VF */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_STAT_OFF 0x00000000 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_VPLL2_DET_STAT_ON 0x00000001 /* R---V */
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#define NV_PRAMDAC_PLL_COMPAT_BLEND 23:23 /* RWIVF */
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#define NV_PRAMDAC_PLL_COMPAT_BLEND_NORMAL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PLL_COMPAT_BLEND_LSBBYPASS 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PLL_COMPAT_MPDIV_XOR 26:24 /* RWIVF */
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#define NV_PRAMDAC_PLL_COMPAT_MPDIV_XOR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT 0:0 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_24 0x00000001 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX32_BIT_31 0x00000000 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX 5:4 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_OFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_POS 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_NEG 0x00000002 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON 0x00000003 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSEL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE 12:12 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_NOTSEL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_15 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_16 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_24 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_30 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_LUT 21:21 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_LUT_8BITS 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_LUT_10BITS 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIPE 29:29 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIPE_SHORT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG 0x00000001 /* RW--V */
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#define NV_PRAMDAC_GENERAL_CONTROL_CUR_32B_ROP 30:30 /* RWIVF */
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#define NV_PRAMDAC_GENERAL_CONTROL_CUR_32B_ROP_DISABLE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_GENERAL_CONTROL_CUR_32B_ROP_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PALETTE_RECOVERY 0x00680604 /* R--4R */
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#define NV_PRAMDAC_PALETTE_RECOVERY_ACTIVE_ADDRESS 7:0 /* R--UF */
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#define NV_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER 10:8 /* R--VF */
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#define NV_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_RED 0x00000001 /* R---V */
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#define NV_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_GREEN 0x00000002 /* R---V */
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#define NV_PRAMDAC_PALETTE_RECOVERY_RGB_POINTER_BLUE 0x00000004 /* R---V */
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#define NV_PRAMDAC_PALETTE_RECOVERY_DAC_STATE 13:12 /* R--VF */
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#define NV_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_WRITE 0x00000000 /* R---V */
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#define NV_PRAMDAC_PALETTE_RECOVERY_DAC_STATE_READ 0x00000003 /* R---V */
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#define NV_PRAMDAC_PALETTE_RECOVERY_RED_DATA 23:16 /* R--VF */
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#define NV_PRAMDAC_PALETTE_RECOVERY_GREEN_DATA 31:24 /* R--VF */
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#define NV_PRAMDAC_PALETTE_LUT_INDEX 0x00680620 /* RW-4R */
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#define NV_PRAMDAC_PALETTE_LUT_INDEX_ADDR 7:0 /* RW-VF */
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#define NV_PRAMDAC_PALETTE_LUT_INDEX_ADDRINC 12:12 /* RWIVF */
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#define NV_PRAMDAC_PALETTE_LUT_INDEX_ADDRINC_ENABLE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_PALETTE_LUT_INDEX_ADDRINC_DISABLE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_PALETTE_LUT_DATA 0x00680624 /* RW-4R */
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#define NV_PRAMDAC_PALETTE_LUT_DATA_BLUE 9:0 /* RW-VF */
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#define NV_PRAMDAC_PALETTE_LUT_DATA_GREEN 19:10 /* RW-VF */
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#define NV_PRAMDAC_PALETTE_LUT_DATA_RED 29:20 /* RW-VF */
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#define NV_PRAMDAC_TEST_CONTROL 0x00680608 /* RW-4R */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_RESET 0:0 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_RESET_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_ENABLE 4:4 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CHANNEL 9:8 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_BLUE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_GREEN 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CHANNEL_RED 0x00000002 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CAPTURE 10:10 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CAPTURE_ALWAYS 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_CRC_CAPTURE_ONE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN 12:12 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC 16:16 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_ON 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_DACTM 20:20 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_DACTM_NORMAL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_DACTM_TEST 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_TPATH1 24:24 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_TPATH1_CLEAR 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_TPATH1_SET 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_TPATH31 25:25 /* RWIVF */
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#define NV_PRAMDAC_TEST_CONTROL_TPATH31_CLEAR 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TEST_CONTROL_TPATH31_SET 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TEST_CONTROL_SENSEB 28:28 /* R--VF */
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#define NV_PRAMDAC_TEST_CONTROL_SENSEB_SOMELO 0x00000000 /* R---V */
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#define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI 0x00000001 /* R---V */
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#define NV_PRAMDAC_CHECKSUM 0x0068060C /* R--4R */
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#define NV_PRAMDAC_CHECKSUM_STATUS 24:24 /* R--VF */
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#define NV_PRAMDAC_CHECKSUM_STATUS_CAPTURED 0x00000001 /* R---V */
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#define NV_PRAMDAC_CHECKSUM_STATUS_WAITING 0x00000000 /* R---V */
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#define NV_PRAMDAC_CHECKSUM_VALUE 23:0 /* R--VF */
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#define NV_PRAMDAC_TESTPOINT_DATA 0x00680610 /* -W-4R */
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#define NV_PRAMDAC_TESTPOINT_DATA_RED 9:0 /* -W-VF */
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#define NV_PRAMDAC_TESTPOINT_DATA_GREEN 19:10 /* -W-VF */
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#define NV_PRAMDAC_TESTPOINT_DATA_BLUE 29:20 /* -W-VF */
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#define NV_PRAMDAC_TESTPOINT_DATA_BLACK 30:30 /* -W-VF */
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#define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK 31:31 /* -W-VF */
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#define NV_PRAMDAC_COMPOSITE 0x00680630 /* RW-4R */
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#define NV_PRAMDAC_COMPOSITE_MODE 1:0 /* RWIVF */
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#define NV_PRAMDAC_COMPOSITE_MODE_RGB 0x00000000 /* RW--V */
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#define NV_PRAMDAC_COMPOSITE_MODE_RESERVED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_COMPOSITE_MODE_YCBCR_601_OUT 0x00000002 /* RWI-V */
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#define NV_PRAMDAC_COMPOSITE_MODE_YCBCR_709_OUT 0x00000003 /* RW--V */
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#define NV_PRAMDAC_COMPOSITE_RESERVED 31:2 /* RWIVF */
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#define NV_PRAMDAC_COMPOSITE_RESERVED_INITIAL 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_LGS_HSYNC_NUMERATOR 0x00680680 /* RW-4R */
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#define NV_PRAMDAC_LGS_HSYNC_NUMERATOR_VALUE 23:0 /* RWIUF */
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#define NV_PRAMDAC_LGS_HSYNC_NUMERATOR_VALUE_ZERO 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_LGS_HSYNC_DENOMINATOR 0x00680684 /* RW-4R */
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#define NV_PRAMDAC_LGS_HSYNC_DENOMINATOR_VALUE 10:0 /* RWIUF */
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#define NV_PRAMDAC_LGS_HSYNC_DENOMINATOR_VALUE_ZERO 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_LGS_HSYNC_HIGH 0x00680688 /* RW-4R */
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#define NV_PRAMDAC_LGS_HSYNC_HIGH_CYCLES 11:0 /* RWIUF */
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#define NV_PRAMDAC_LGS_HSYNC_HIGH_CYCLES_ZERO 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_LGS_HSYNC_HIGH_VSYNC 0x0068068c /* RW-4R */
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#define NV_PRAMDAC_LGS_HSYNC_HIGH_VSYNC_CYCLES 11:0 /* RWIUF */
|
|
#define NV_PRAMDAC_LGS_HSYNC_HIGH_VSYNC_CYCLES_ZERO 0x00000000 /* RWI-V */
|
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#define NV_PRAMDAC_LGS_SWITCHES 0x00680690 /* RW-4R */
|
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#define NV_PRAMDAC_LGS_SWITCHES_ENCODER_MODE 0:0 /* RWIVF */
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|
#define NV_PRAMDAC_LGS_SWITCHES_ENCODER_MODE_NON_BYPASS 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_LGS_SWITCHES_ENCODER_MODE_BYPASS 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_LGS_TRANSFER 0x006806a0 /* RW-4R */
|
|
#define NV_PRAMDAC_LGS_TRANSFER_LOAD_VALUES 0:0 /* RWIVF */
|
|
#define NV_PRAMDAC_LGS_TRANSFER_LOAD_VALUES_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_LGS_TRANSFER_LOAD_VALUES_ONE 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_LGS_TRANSFER_LOADED_VALUES 4:4 /* R-IVF */
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|
#define NV_PRAMDAC_LGS_TRANSFER_LOADED_VALUES_ZERO 0x00000000 /* R-I-V */
|
|
#define NV_PRAMDAC_LGS_TRANSFER_LOADED_VALUES_ONE 0x00000001 /* R---V */
|
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#define NV_PRAMDAC_TV_SETUP 0x00680700 /* RW-4R */
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|
#define NV_PRAMDAC_TV_SETUP_DEV_TYPE 1:0 /* RWIVF */
|
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#define NV_PRAMDAC_TV_SETUP_DEV_TYPE_SLAVE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_TV_SETUP_DEV_TYPE_MASTER 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_TV_SETUP_DEV_TYPE_SLAVE_ALT 0x00000002 /* RW--V */
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#define NV_PRAMDAC_TV_SETUP_DEV_TYPE_MASTER_ALT 0x00000003 /* RW--V */
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#define NV_PRAMDAC_TV_SETUP_DATA_SRC 9:8 /* RWIVF */
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#define NV_PRAMDAC_TV_SETUP_DATA_SRC_COMP 0x00000000 /* RWI-V */
|
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#define NV_PRAMDAC_TV_SETUP_DATA_SRC_SCALER 0x00000001 /* RW--V */
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|
#define NV_PRAMDAC_TV_SETUP_DATA_SRC_VIP 0x00000002 /* RW--V */
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#define NV_PRAMDAC_TV_SETUP_DATA_SRC_NONE 0x00000003 /* RW--V */
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#define NV_PRAMDAC_TV_SETUP_SYNC_POL 17:16 /* RWIVF */
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#define NV_PRAMDAC_TV_SETUP_SYNC_POL_NEG_NONE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TV_SETUP_SYNC_POL_NEG_HSYNC 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TV_SETUP_SYNC_POL_NEG_VSYNC 0x00000002 /* RW--V */
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#define NV_PRAMDAC_TV_SETUP_SYNC_POL_NEG_BOTH 0x00000003 /* RW--V */
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#define NV_PRAMDAC_BLANK_COLOR 0x00680714 /* RW-4R */
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#define NV_PRAMDAC_BLANK_COLOR_VAL 23:0 /* RWIVF */
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#define NV_PRAMDAC_BLANK_COLOR_EN 31:30 /* RWIVF */
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#define NV_PRAMDAC_BLANK_COLOR_EN_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_BLANK_COLOR_EN_BLANK 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_BLANK_COLOR_EN_ALWAYS 0x00000003 /* RW--V */
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#define NV_PRAMDAC_TV_VTOTAL 0x00680720 /* RW-4R */
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#define NV_PRAMDAC_TV_VTOTAL_VAL 10:0 /* RWIVF */
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|
#define NV_PRAMDAC_TV_VSYNC_START 0x00680724 /* RW-4R */
|
|
#define NV_PRAMDAC_TV_VSYNC_START_VAL 10:0 /* RWIVF */
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#define NV_PRAMDAC_TV_VSYNC_END 0x00680728 /* RW-4R */
|
|
#define NV_PRAMDAC_TV_VSYNC_END_VAL 10:0 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_HTOTAL 0x0068072C /* RW-4R */
|
|
#define NV_PRAMDAC_TV_HTOTAL_VAL 10:0 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_HSYNC_START 0x00680730 /* RW-4R */
|
|
#define NV_PRAMDAC_TV_HSYNC_START_VAL 10:0 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_HSYNC_END 0x00680734 /* RW-4R */
|
|
#define NV_PRAMDAC_TV_HSYNC_END_VAL 10:0 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_CHECKSUM 0x00680718 /* RW-4R */
|
|
#define NV_PRAMDAC_TV_CHECKSUM_VAL 23:0 /* R--VF */
|
|
#define NV_PRAMDAC_TV_CHECKSUM_STATUS 24:24 /* R--VF */
|
|
#define NV_PRAMDAC_TV_CHECKSUM_STATUS_CAPTURED 0x00000001 /* R---V */
|
|
#define NV_PRAMDAC_TV_CHECKSUM_STATUS_WAITING 0x00000000 /* R---V */
|
|
#define NV_PRAMDAC_TV_VSYNC 28:28 /* R--VF */
|
|
#define NV_PRAMDAC_TV_VSYNC_LOW 0x00000000 /* R---V */
|
|
#define NV_PRAMDAC_TV_VSYNC_HIGH 0x00000001 /* R---V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL 0x0068071c /* RW-4R */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_RESET 0:0 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_DEASSERTED 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_RESET_ASSERTED 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE 4:4 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL 9:8 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_7_0 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_15_8 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CHANNEL_23_16 0x00000002 /* RW--V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CAPTURE 10:10 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CAPTURE_ALWAYS 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_TV_TEST_CONTROL_CRC_CAPTURE_ONE 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_TV_SYNC_DELAY 0x00680738 /* RW-4R */
|
|
#define NV_PRAMDAC_TV_SYNC_DELAY_HSYNC 7:0 /* RWIVF */
|
|
#define NV_PRAMDAC_TV_SYNC_DELAY_VSYNC 23:16 /* RWIVF */
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|
#define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VDISPLAY_END_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_VTOTAL 0x00680804 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VTOTAL_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_VCRTC 0x00680808 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VCRTC_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_VSYNC_START 0x0068080c /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VSYNC_START_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_VSYNC_END 0x00680810 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VSYNC_END_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_VVALID_START 0x00680814 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VVALID_START_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_VVALID_END 0x00680818 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_VVALID_END_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HDISPLAY_END_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HTOTAL 0x00680824 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HTOTAL_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HCRTC 0x00680828 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HCRTC_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HSYNC_START 0x0068082c /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HSYNC_START_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HSYNC_END 0x00680830 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HSYNC_END_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HVALID_START 0x00680834 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HVALID_START_VAL 15:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_HVALID_END 0x00680838 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_HVALID_END_VAL 15:0 /* RWIVF */
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|
#define NV_PRAMDAC_FP_CHECKSUM 0x00680840 /* RW-4R */
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|
#define NV_PRAMDAC_FP_CHECKSUM_VAL 23:0 /* R--VF */
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#define NV_PRAMDAC_FP_CHECKSUM_STATUS 24:24 /* R--VF */
|
|
#define NV_PRAMDAC_FP_CHECKSUM_STATUS_CAPTURED 0x00000001 /* R---V */
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|
#define NV_PRAMDAC_FP_CHECKSUM_STATUS_WAITING 0x00000000 /* R---V */
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|
#define NV_PRAMDAC_FP_VSYNC 28:28 /* R--VF */
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#define NV_PRAMDAC_FP_VSYNC_LOW 0x00000000 /* R---V */
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#define NV_PRAMDAC_FP_VSYNC_HIGH 0x00000001 /* R---V */
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#define NV_PRAMDAC_FP_TEST_CONTROL 0x00680844 /* RW-4R */
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|
#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_RESET 0:0 /* RWIVF */
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|
#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_RESET_DEASSERTED 0x00000000 /* RWI-V */
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|
#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_ENABLE 4:4 /* RWIVF */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_ENABLE_DEASSERTED 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_ENABLE_ASSERTED 0x00000001 /* RW--V */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CHANNEL 9:8 /* RWIVF */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CHANNEL_7_0 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CHANNEL_15_8 0x00000001 /* RW--V */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CHANNEL_23_16 0x00000002 /* RW--V */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CAPTURE 10:10 /* RWIVF */
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#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CAPTURE_ALWAYS 0x00000000 /* RWI-V */
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|
#define NV_PRAMDAC_FP_TEST_CONTROL_CRC_CAPTURE_ONE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_FP_TG_CONTROL 0x00680848 /* RW-4R */
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#define NV_PRAMDAC_FP_TG_CONTROL_VSYNC 1:0 /* RWIVF */
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#define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_NEG 0x00000000 /* RW--V */
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#define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS 0x00000001 /* RWI-V */
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#define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE 0x00000002 /* RW--V */
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#define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_RSVD 0x00000003 /* RW--V */
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#define NV_PRAMDAC_FP_TG_CONTROL_HSYNC 5:4 /* RWIVF */
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#define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_NEG 0x00000000 /* RW--V */
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#define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS 0x00000001 /* RWI-V */
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#define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE 0x00000002 /* RW--V */
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#define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_RSVD 0x00000003 /* RWI-V */
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|
#define NV_PRAMDAC_FP_TG_CONTROL_MODE 9:8 /* RWIVF */
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#define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE 0x00000002 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_CENTER 13:12 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_CENTER_NONE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_CENTER_HORIZ 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_CENTER_VERT 0x00000002 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_CENTER_BOTH 0x00000003 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_NATIVE 17:16 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_NATIVE_NONE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_NATIVE_HORIZ 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_NATIVE_VERT 0x00000002 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_NATIVE_BOTH 0x00000003 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_READ 20:20 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_READ_ACTUAL 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_READ_PROG 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_WIDTH 24:24 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_24 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN 29:28 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_NEG 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE 0x00000002 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_RSVD 0x00000003 /* RW--V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_FPCLK_RATIO 31:31 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_FPCLK_RATIO_DB1 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_TG_CONTROL_FPCLK_RATIO_DB2 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR 0x0068084C /* RW-4R */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR_BLUE 7:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR_BLUE_DEFAULT 0x80 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR_GREEN 15:8 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR_GREEN_DEFAULT 0x10 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR_RED 23:16 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_INACTIVE_PXL_COLOR_RED_DEFAULT 0x80 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0 0x00680880 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XSCALE 0:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XSCALE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XSCALE_STEP_AUTO 2:2 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XSCALE_STEP_AUTO_EN 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XSCALE_STEP_AUTO_DIS 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YSCALE 4:4 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YSCALE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YSCALE_STEP_AUTO 6:6 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YSCALE_STEP_AUTO_EN 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YSCALE_STEP_AUTO_DIS 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XINTERP 8:8 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XINTERP_TRUNCATE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YINTERP 12:12 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YINTERP_TRUNCATE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_VCNTR 17:16 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_TEST_NONE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_TEST_VCNTR 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_TEST_NEWPIX 0x00000002 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_TEST_BOTH 0x00000003 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT 20:20 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_TRUNCATE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT 24:24 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_TRUNCATE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN 28:28 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_NONE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL 29:29 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_TMDS_PLL_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_1 0x00680884 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE 12:12 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE 27:16 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE 28:28 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_2 0x00680888 /* RW-4R */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_HTOTAL_VALUE 11:0 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_HTOTAL_TESTMODE 12:12 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_HTOTAL_TESTMODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_HTOTAL_TESTMODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_VTOTAL_VALUE 27:16 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_VTOTAL_TESTMODE 28:28 /* RWIVF */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_VTOTAL_TESTMODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRAMDAC_FP_DEBUG_2_VTOTAL_TESTMODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRAMDAC_FP_DEBUG_3 0x0068088c /* R--4R */
|
|
#define NV_PRAMDAC_FP_DEBUG_3_XSTEPSIZE 12:0 /* R--VF */
|
|
#define NV_PRAMDAC_FP_DEBUG_3_YSTEPSIZE 28:16 /* R--VF */
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#define NV_PRAMDAC_FP_DEBUG_4 0x00680890 /* R--4R */
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#define NV_PRAMDAC_FP_DEBUG_4_XSTEPSIZE 28:11 /* R--VF */
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#define NV_PRAMDAC_FP_DEBUG_5 0x00680894 /* R--4R */
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#define NV_PRAMDAC_FP_DEBUG_5_YSTEPSIZE 28:11 /* R--VF */
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#define NV_PRAMDAC_FP_DEBUG_6 0x00680898 /* RW-4R */
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#define NV_PRAMDAC_FP_DEBUG_6_XSCALE_VALUE 28:11 /* RWIVF */
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#define NV_PRAMDAC_FP_DEBUG_6_XSCALE_VALUE_NOSCALE 0x10000000 /* RWI-V */
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#define NV_PRAMDAC_FP_DEBUG_7 0x0068089c /* RW-4R */
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#define NV_PRAMDAC_FP_DEBUG_7_YSCALE_VALUE 28:11 /* RWIVF */
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#define NV_PRAMDAC_FP_DEBUG_7_YSCALE_VALUE_NOSCALE 0x10000000 /* RWI-V */
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#define NV_PRAMDAC_FP_RAM_CONTROL 0x006808A0 /* RW-4R */
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#define NV_PRAMDAC_FP_RAM_CONTROL_ADDRESS 8:0 /* RW-VF */
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#define NV_PRAMDAC_FP_RAM_CONTROL_TESTMODE 16:16 /* RWIVF */
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#define NV_PRAMDAC_FP_RAM_CONTROL_TESTMODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_FP_RAM_CONTROL_TESTMODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_FP_RAM_DATA_0 0x006808A4 /* RWI4R */
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#define NV_PRAMDAC_FP_RAM_DATA_0_VAL 31:0 /* RW--F */
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#define NV_PRAMDAC_FP_RAM_DATA_1 0x006808A8 /* RWI4R */
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#define NV_PRAMDAC_FP_RAM_DATA_1_VAL 31:0 /* RW--F */
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#define NV_PRAMDAC_FP_RAM_DATA_2 0x006808AC /* RWI4R */
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#define NV_PRAMDAC_FP_RAM_DATA_2_VAL 7:0 /* RW--F */
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#define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808B0 /* RW-4R */
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#define NV_PRAMDAC_FP_TMDS_CONTROL_ADDRESS 7:0 /* RW-VF */
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#define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE 16:16 /* RWIVF */
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#define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE 0x00000001 /* RWI-V */
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#define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_ENABLE 0x00000000 /* RW--V */
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#define NV_PRAMDAC_FP_TMDS_DATA 0x006808B4 /* RW-4R */
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#define NV_PRAMDAC_FP_TMDS_DATA_DATA 7:0 /* RW-VF */
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#define NV_PRAMDAC_TVO_SETUP 0x006808C0 /* RW-4R */
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#define NV_PRAMDAC_TVO_SETUP_DEV_TYPE 0:0 /* RWIVF */
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#define NV_PRAMDAC_TVO_SETUP_DEV_TYPE_SLAVE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_SETUP_DEV_TYPE_MASTER 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_SETUP_DATA_FORMAT 5:4 /* RWIVF */
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#define NV_PRAMDAC_TVO_SETUP_DATA_FORMAT_MODE_1X00 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_SETUP_DATA_FORMAT_MODE_0110 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_SETUP_DATA_FORMAT_MODE_0000 0x00000002 /* RW--V */
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#define NV_PRAMDAC_TVO_SETUP_DATA_FORMAT_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_PRAMDAC_TVO_SETUP_DATA_OUT 8:8 /* RWIVF */
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#define NV_PRAMDAC_TVO_SETUP_DATA_OUT_IS_TVO 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_SETUP_DATA_OUT_IS_FP 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_BLANK_COLOR 0x006808C4 /* RW-4R */
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#define NV_PRAMDAC_TVO_BLANK_COLOR_VAL 23:0 /* RWIVF */
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#define NV_PRAMDAC_TVO_BLANK_COLOR_VAL_DEFAULT 0x00801080 /* RWI-V */
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#define NV_PRAMDAC_TVO_BLANK_COLOR_EN 31:30 /* RWIVF */
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#define NV_PRAMDAC_TVO_BLANK_COLOR_EN_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_BLANK_COLOR_EN_BLANK 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_BLANK_COLOR_EN_ALWAYS 0x00000003 /* RW--V */
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#define NV_PRAMDAC_TVO_SYNC_DELAY 0x006808C8 /* RW-4R */
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#define NV_PRAMDAC_TVO_SYNC_DELAY_HSYNC 7:0 /* RWIVF */
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#define NV_PRAMDAC_TVO_SYNC_DELAY_VSYNC 23:16 /* RWIVF */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL 0x006808CC /* RW-4R */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_HSYNC_BYPASS 0:0 /* RWIVF */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_HSYNC_BYPASS_DIS 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_HSYNC_BYPASS_EN 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_HSYNC_VAL 4:4 /* RWIVF */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_HSYNC_VAL_ZERO 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_HSYNC_VAL_ONE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_VSYNC_BYPASS 16:16 /* RWIVF */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_VSYNC_BYPASS_DIS 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_VSYNC_BYPASS_EN 0x00000001 /* RW--V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_VSYNC_VAL 20:20 /* RWIVF */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_VSYNC_VAL_ZERO 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_TVO_TESTMODE_CTRL_VSYNC_VAL_ONE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL 0x00680900 /* RW-4R */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_DISP 1:0 /* RW-VF */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_DISP_NEVER 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_DISP_ODD 0x00000001 /* RW--V */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_DISP_EVEN 0x00000002 /* RW--V */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_DISP_ALWAYS 0x00000003 /* RW--V */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_PROG 4:4 /* RW-VF */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_PROG_DISABLE 0x00000000 /* RWI-V */
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#define NV_PRAMDAC_MCHIP_GENERAL_CONTROL_PROG_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMDAC_MCHIP_VDISPLAY_FIELD 0x00680904 /* RW-4R */
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#define NV_PRAMDAC_MCHIP_VDISPLAY_FIELD_START 11:0 /* RW-VF */
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#define NV_PRAMDAC_MCHIP_VDISPLAY_FIELD_END 27:16 /* RW-VF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0 0x00 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_SEL10UA 0:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_SEL10UA_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_SEL50UA 1:1 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_SEL50UA_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_SEL100UA 2:2 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_SEL100UA_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_FILSEL 5:3 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_FILSEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_CONF 7:6 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL0_CONF_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1 0x01 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_RSEL 2:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_RSEL_RESET 0x7 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_CSEL 4:3 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_CSEL_RESET 0x3 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_IOCTRL1 5:5 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_IOCTRL1_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_DIVBY10 6:6 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_DIVBY10_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_IRSEL 7:7 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL1_IRSEL_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2 0x02 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_DIVBY1 0:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_DIVBY1_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_DIVBY7 1:1 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_DIVBY7_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_ALTCLK 2:2 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_ALTCLK_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_AUX 7:3 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_PLL2_AUX_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_IDLY 0x03 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_IDLY_IDEL 3:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_IDLY_IDEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_IDLY_CDEL 7:4 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_IDLY_CDEL_RESET 0x3 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE 0x04 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LVDSMODE 0:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LVDSMODE_TMDS 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LVDSMODE_LVDS 0x1 /* RW--V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL 3:3 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_NORMAL 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_ALTERNATE 0x1 /* RW--V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LINKACT 7:7 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LINKACT_DISABLE 0x0 /* RW--V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LINKACT_ENABLE 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LVDSMODE_RESET 0x0 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_RESET 0x0 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_DINRISE 0x0 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_DINFALL 0x1 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_DALTRISE 0x2 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_DINSEL_DALTFALL 0x3 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_MODE_LINKACT_RESET 0x1 /* RW-- */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS 0x05 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODESWAPCTL 0:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODESWAPCTL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEHS 1:1 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEHS_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEVS 2:2 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEVS_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEDEN 3:3 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEDEN_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEBALANCED 4:4 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEBALANCED_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODE24B 5:5 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODE24B_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEUPPER 6:6 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_LVDS_MODEUPPER_RESET 0x1 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG0 0x06 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG0_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG0_VAL_RESET 0x00 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG1 0x07 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG1_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG1_VAL_RESET 0x00 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG2 0x08 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG2_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_TRIG2_VAL_RESET 0x00 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC0 0x09 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC0_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC1 0x0a /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC1_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC2 0x0b /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC2_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC3 0x0c /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC3_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC4 0x0d /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC4_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC5 0x0e /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_VCRC5_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA0 0x0f /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA0_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA1 0x10 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA1_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA2 0x11 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA2_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA3 0x12 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_IDATA3_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA0 0x13 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA0_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA1 0x14 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA1_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA2 0x15 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA2_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA3 0x16 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA3_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA4 0x17 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_EDATA4_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CNTL0 0x18 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CNTL0_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CNTH0 0x19 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CNTH0_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CNTL1 0x1a /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CNTL1_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CNTH1 0x1b /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CNTH1_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CNTL2 0x1c /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CNTL2_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CNTH2 0x1d /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CNTH2_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR0 0x1e /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR0_THISPAR 3:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR0_RUNPAR 7:4 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR1 0x1f /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR1_THISPAR 3:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR1_RUNPAR 7:4 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR2 0x20 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR2_THISPAR 3:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR2_RUNPAR 7:4 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR3 0x21 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR3_THISPAR 3:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPAR3_RUNPAR 7:4 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPARCK 0x22 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_DISPARCK_THISPAR 3:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_DISPARCK_RUNPAR 7:4 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC0 0x23 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC0_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC1 0x24 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC1_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC2 0x25 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC2_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC3 0x26 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC3_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC4 0x27 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC4_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC5 0x28 /* R--1R */
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#define NV_PRAMDAC_INDIR_TMDS_CCRC5_VAL 7:0 /* R--VF */
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#define NV_PRAMDAC_INDIR_TMDS_ROTCK 0x29 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_ROTCK_ROTVAL 3:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_ROTCK_RSEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0 0x30 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0_ICHPMP 3:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0_ICHPMP_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0_FILSEL 6:4 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0_FILSEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0_ICLKSEL 7:7 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL0_ICLKSEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1 0x31 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_CSEL 1:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_CSEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_RSEL 5:2 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_RSEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_FBACK_SEL 6:6 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_FBACK_SEL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_SEL1UA 7:7 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL1_SEL1UA_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL2 0x32 /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL2_AUX 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_FE_PLL2_AUX_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL 0x3a /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL_TEST_DATA 0:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL_TEST_DATA_DISABLE 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL_TEST_DATA_ENABLE 0x1 /* RW--V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL_SYNC_LOAD_EN 7:7 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL_SYNC_LOAD_EN_OFF 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_CTL_SYNC_LOAD_EN_ON 0x1 /* RW--V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA0 0x3b /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA0_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA0_VAL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA1 0x3c /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA1_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA1_VAL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA2 0x3d /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA2_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA2_VAL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA3 0x3e /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA3_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA3_VAL_RESET 0x0 /* RWI-V */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA4 0x3f /* RW-1R */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA4_VAL 7:0 /* RWIVF */
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#define NV_PRAMDAC_INDIR_TMDS_DEBUG_DATA4_VAL_RESET 0x0 /* RWI-V */
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/* dev_dac.ref */
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#define NV_USER_DAC 0x00681FFF:0x00681200 /* RW--D */
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#define NV_USER_DAC_PIXEL_MASK 0x006813C6 /* RWI1R */
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#define NV_USER_DAC_PIXEL_MASK_VALUE 7:0 /* RWIVF */
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#define NV_USER_DAC_PIXEL_MASK_MASK 0x000000FF /* RWI-V */
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#define NV_USER_DAC_READ_MODE_ADDRESS 0x006813C7 /* RW-1R */
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#define NV_USER_DAC_READ_MODE_ADDRESS_VALUE 7:0 /* RW-VF */
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#define NV_USER_DAC_READ_MODE_ADDRESS_WO_VALUE 7:0 /* -W-VF */
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#define NV_USER_DAC_READ_MODE_ADDRESS_RW_STATE 1:0 /* R--VF */
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#define NV_USER_DAC_READ_MODE_ADDRESS_RW_STATE_WRITE 0x00000000 /* R---V */
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#define NV_USER_DAC_READ_MODE_ADDRESS_RW_STATE_READ 0x00000003 /* R---V */
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#define NV_USER_DAC_WRITE_MODE_ADDRESS 0x006813C8 /* RW-1R */
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#define NV_USER_DAC_WRITE_MODE_ADDRESS_VALUE 7:0 /* RW-VF */
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#define NV_USER_DAC_PALETTE_DATA 0x006813C9 /* RW-1R */
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#define NV_USER_DAC_PALETTE_DATA_VALUE 7:0 /* RW-VF */
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/* dev_dac.ref */
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#define NV_PDAC 0x00680FFF:0x00680000 /* RW--D */
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/* dev_dac.ref */
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#define NV_PRMDIO 0x00681FFF:0x00681000 /* RW--D */
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/* dev_md.ref */
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#define NV_PMD 0x0000bfff:0x0000b000 /* RW--D */
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#define NV_PMD_INTR 0x0000b100 /* RW-4R */
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#define NV_PMD_INTR_AWAKEN 0:0 /* RWIVF */
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#define NV_PMD_INTR_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMD_INTR_AWAKEN_PENDING 0x00000001 /* R---V */
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#define NV_PMD_INTR_AWAKEN_RESET 0x00000001 /* -W--C */
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#define NV_PMD_INTR_ERROR 4:4 /* RWIVF */
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#define NV_PMD_INTR_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMD_INTR_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PMD_INTR_ERROR_RESET 0x00000001 /* -W--C */
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#define NV_PMD_INTR_METHOD_PATCH 8:8 /* RWIVF */
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#define NV_PMD_INTR_METHOD_PATCH_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMD_INTR_METHOD_PATCH_PENDING 0x00000001 /* R---V */
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#define NV_PMD_INTR_METHOD_PATCH_RESET 0x00000001 /* -W--C */
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#define NV_PMD_INTR_BREAKPOINT 28:28 /* RWIVF */
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#define NV_PMD_INTR_BREAKPOINT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMD_INTR_BREAKPOINT_PENDING 0x00000001 /* R---V */
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#define NV_PMD_INTR_BREAKPOINT_RESET 0x00000001 /* -W--C */
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#define NV_PMD_INTR_EN 0x0000b140 /* RW-4R */
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#define NV_PMD_INTR_EN_ALL 0:0 /* RWIVF */
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#define NV_PMD_INTR_EN_ALL_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMD_INTR_EN_ALL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMD_ERROR 0x0000b200 /* R--4R */
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#define NV_PMD_ERROR_STATUS 31:0 /* R--VF */
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#define NV_PMD_ERROR_STATUS_INVALID_STATE 0x01000000 /* R---V */
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#define NV_PMD_ERROR_STATUS_BAD_ARGUMENT 0x02000000 /* R---V */
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#define NV_PMD_ERROR_STATUS_RESERVED_METHOD 0x08000000 /* R---V */
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#define NV_PMD_TIME_0 0x0000b210 /* R--4R */
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#define NV_PMD_TIME_0_VALUE 31:0 /* R-XUF */
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#define NV_PMD_TIME_1 0x0000b214 /* R--4R */
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#define NV_PMD_TIME_1_VALUE 31:0 /* R-XUF */
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#define NV_PMD_INSTANCE 0x0000b220 /* R--4R */
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#define NV_PMD_INSTANCE_VALUE 15:0 /* R-XUF */
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#define NV_PMD_METHOD 0x0000b224 /* R--4R */
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#define NV_PMD_METHOD_VALUE 12:2 /* R-XUF */
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#define NV_PMD_DATA 0x0000b228 /* R--4R */
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#define NV_PMD_DATA_VALUE 31:0 /* R-XVF */
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#define NV_PMD_CTX_DMA 0x0000b300 /* R--4R */
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#define NV_PMD_CTX_DMA_NOTIFIES_INSTANCE 15:0 /* R-IUF */
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#define NV_PMD_CTX_DMA_FRAMES_INSTANCE 31:16 /* R-IUF */
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#define NV_PMD_CONTEXT 0x0000b400 /* RW-4R */
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#define NV_PMD_CONTEXT_STATE 0:0 /* R-IVF */
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#define NV_PMD_CONTEXT_STATE_NOT_IDLE 0x00000000 /* R---V */
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#define NV_PMD_CONTEXT_STATE_IDLE 0x00000001 /* R-I-V */
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#define NV_PMD_CONTEXT_STATE_CHECK_IDLENESS 0x00000001 /* -W--C */
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#define NV_PMD_CONTEXT_STALL 4:4 /* RWIVF */
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#define NV_PMD_CONTEXT_STALL_INACTIVE 0x00000000 /* R-I-V */
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#define NV_PMD_CONTEXT_STALL_ACTIVE 0x00000001 /* R---V */
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#define NV_PMD_CONTEXT_STALL_RELEASE 0x00000001 /* -W--C */
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#define NV_PMD_CONTEXT_FLUSH_AND_INVALIDATE 0:0 /* RWIVF */
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#define NV_PMD_CONTEXT_FLUSH_AND_INVALIDATE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMD_CONTEXT_FLUSH_AND_INVALIDATE_PENDING 0x00000001 /* R---V */
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#define NV_PMD_CONTEXT_FLUSH_AND_INVALIDATE_NOW 0x00000001 /* -W--S */
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#define NV_PMD_DEBUG_FE 0x0000ba00 /* RW-4R */
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#define NV_PMD_DEBUG_FE_CYA_0 0:0 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_0_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_1 1:1 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_1_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_2 2:2 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_2_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_3 3:3 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_3_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_4 4:4 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_4_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_5 5:5 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_5_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_6 6:6 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_6_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_7 7:7 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_7_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_8 8:8 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_8_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_9 9:9 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_9_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_10 10:10 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_10_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_11 11:11 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_11_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_12 12:12 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_12_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_FE_CYA_13 13:13 /* RWIVF */
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#define NV_PMD_DEBUG_FE_CYA_13_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_P 0x0000ba08 /* ---4R */
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#define NV_PMD_DEBUG_PBCF 0x0000ba10 /* ---4R */
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#define NV_PMD_DEBUG_MC 0x0000ba18 /* ---4R */
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#define NV_PMD_DEBUG_PMB 0x0000ba20 /* ---4R */
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#define NV_PMD_DEBUG_IQ 0x0000ba28 /* ---4R */
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#define NV_PMD_DEBUG_TBB 0x0000ba30 /* RW-4R */
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#define NV_PMD_DEBUG_TBB_CYA_0 0:0 /* RWIVF */
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#define NV_PMD_DEBUG_TBB_CYA_0_FALSE 0x00000000 /* RWI-V */
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#define NV_PMD_DEBUG_IDCT 0x0000ba38 /* ---4R */
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#define NV_PMD_DEBUG_EBRF 0x0000ba40 /* ---4R */
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#define NV_PMD_DEBUG_M 0x0000ba48 /* ---4R */
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#define NV_PMD_DEBUG_FI 0x0000ba50 /* ---4R */
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#define NV_PMD_RAM_ADDR 0x0000bc00 /* RW-4R */
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#define NV_PMD_RAM_ADDR_VALUE 5:0 /* RWXVF */
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#define NV_PMD_RAM_PBC_A_0 0x0000bc10 /* RW-4R */
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#define NV_PMD_RAM_PBC_A_0_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PBC_A_1 0x0000bc14 /* RW-4R */
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#define NV_PMD_RAM_PBC_A_1_VALUE 29:0 /* RWXVF */
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#define NV_PMD_RAM_PBC_B_0 0x0000bc20 /* RW-4R */
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#define NV_PMD_RAM_PBC_B_0_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PBC_B_1 0x0000bc24 /* RW-4R */
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#define NV_PMD_RAM_PBC_B_1_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PBC_B_2 0x0000bc28 /* RW-4R */
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#define NV_PMD_RAM_PBC_B_2_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PBC_B_3 0x0000bc2c /* RW-4R */
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#define NV_PMD_RAM_PBC_B_3_VALUE 11:0 /* RWXVF */
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#define NV_PMD_RAM_INSTR 0x0000bc40 /* RW-4R */
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#define NV_PMD_RAM_INSTR_VALUE 9:0 /* RWXVF */
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#define NV_PMD_RAM_PMB_0 0x0000bc50 /* RW-4R */
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#define NV_PMD_RAM_RAM_0_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PMB_1 0x0000bc54 /* RW-4R */
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#define NV_PMD_RAM_RAM_1_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PMB_2 0x0000bc58 /* RW-4R */
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#define NV_PMD_RAM_RAM_2_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_PMB_3 0x0000bc5c /* RW-4R */
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#define NV_PMD_RAM_RAM_3_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_QM 0x0000bc70 /* RW-4R */
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#define NV_PMD_RAM_QM_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_TFB_0 0x0000bc80 /* RW-4R */
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#define NV_PMD_RAM_TFB_0_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_TFB_1 0x0000bc84 /* RW-4R */
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#define NV_PMD_RAM_TFB_1_VALUE 15:0 /* RWXVF */
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#define NV_PMD_RAM_TSB_0 0x0000bc90 /* RW-4R */
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#define NV_PMD_RAM_TSB_0_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_TSB_1 0x0000bc94 /* RW-4R */
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#define NV_PMD_RAM_TSB_1_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_TSB_2 0x0000bc98 /* RW-4R */
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#define NV_PMD_RAM_TSB_2_VALUE 3:0 /* RWXVF */
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#define NV_PMD_RAM_EBR_0 0x0000bca0 /* RW-4R */
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#define NV_PMD_RAM_EBR_0_VALUE 31:0 /* RWXVF */
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|
#define NV_PMD_RAM_EBR_1 0x0000bca4 /* RW-4R */
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#define NV_PMD_RAM_EBR_1_VALUE 31:0 /* RWXVF */
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#define NV_PMD_RAM_EBR_2 0x0000bca8 /* RW-4R */
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#define NV_PMD_RAM_EBR_2_VALUE 7:0 /* RWXVF */
|
|
/* dev_md.ref */
|
|
#define NV_MD_FESTATE1 0x0000bd00 /* RW-4R */
|
|
#define NV_MD_FESTATE1_FIELD1 3:0 /* RWIUF */
|
|
#define NV_MD_FESTATE1_FIELD1_FUN 0x00000008 /* RWI-V */
|
|
#define NV_MD_FESTATE1_FIELD2 4:4 /* RWIVF */
|
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#define NV_MD_FESTATE1_FIELD2_FUN 0x00000000 /* RWI-V */
|
|
#define NV_MD_FESTATE2 0x0000bd04 /* RW-4R */
|
|
#define NV_MD_FESTATE2_FIELD1 3:0 /* RWIUF */
|
|
#define NV_MD_FESTATE2_FIELD1_FUN 0x00000008 /* RWI-V */
|
|
#define NV_MD_FESTATE2_FIELD2 4:4 /* RWIVF */
|
|
#define NV_MD_FESTATE2_FIELD2_FUN 0x00000000 /* RWI-V */
|
|
#define NV_MD_VDEBUG1 0x0000bd08 /* RW-4R */
|
|
#define NV_MD_VDEBUG1_TRACEFE 0:0 /* RWIUF */
|
|
#define NV_MD_VDEBUG1_TRACEFE_OFF 0 /* RWI-V */
|
|
#define NV_MD_VDEBUG1_TRACEFE_ON 1 /* RWI-V */
|
|
/* dev_master.ref */
|
|
#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */
|
|
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
|
|
#define NV_PMC_BOOT_0_ID 31:0 /* R--VF */
|
|
#define NV_PMC_BOOT_0_ID_NV01_A 0x00010100 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV01_B 0x00010101 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV01_B02 0x00010102 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV01_B03 0x00010103 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV01_C01 0x00010104 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV02_A01 0x10020400 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV03_A01 0x00030100 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV03_B01 0x00030110 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV03T_A01 0x20030120 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV03T_A02 0x20030121 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV03T_A03_A04 0x20030122 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV04_A01_A02_A03 0x20004000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV04_A04 0x20034001 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV04_A05 0x20044001 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV05_NV06_A01 0x20104000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV05_NV06_A02 0x20114000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV05_NV06_A03 0x20124000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV05_NV06_B01 0x20204000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV05_NV06_B02 0x20214000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV05_NV06_B03 0x20224000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV0A_A01 0x20204000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV0A_A02 0x20214000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV0A_B01 0x20224000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A1_DEVID0 0x010000A1 /* C---V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A1_DEVID1 0x010100A1 /* C---V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A1_DEVID2 0x010200A1 /* C---V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A1_DEVID3 0x010300A1 /* C---V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A2_DEVID0 0x010000A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A2_DEVID1 0x010100A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A2_DEVID2 0x010200A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_A2_DEVID3 0x010300A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B1_DEVID0 0x010000B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B1_DEVID1 0x010100B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B1_DEVID2 0x010200B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B1_DEVID3 0x010300B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B2_DEVID0 0x010000B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B2_DEVID1 0x010100B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B2_DEVID2 0x010200B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV10_B2_DEVID3 0x010300B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_A1_DEVID0 0x020000A1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_A1_DEVID1 0x020100A1 /* ----V */
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|
#define NV_PMC_BOOT_0_ID_NV20_A1_DEVID2 0x020200A1 /* ----V */
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|
#define NV_PMC_BOOT_0_ID_NV20_A1_DEVID3 0x020300A1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_A2_DEVID0 0x020000A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_A2_DEVID1 0x020100A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_A2_DEVID2 0x020200A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_A2_DEVID3 0x020300A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_B1_DEVID0 0x020000B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_B1_DEVID1 0x020100B1 /* ----V */
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#define NV_PMC_BOOT_0_ID_NV20_B1_DEVID2 0x020200B1 /* ----V */
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#define NV_PMC_BOOT_0_ID_NV20_B1_DEVID3 0x020300B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_B2_DEVID0 0x020000B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_B2_DEVID1 0x020100B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_B2_DEVID2 0x020200B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV20_B2_DEVID3 0x020300B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_A1_DEVID0 0x02A000A1 /* C---V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_A1_DEVID1 0x02A100A1 /* C---V */
|
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#define NV_PMC_BOOT_0_ID_NV2A_A1_DEVID2 0x02A200A1 /* C---V */
|
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#define NV_PMC_BOOT_0_ID_NV2A_A1_DEVID3 0x02A300A1 /* C---V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_A2_DEVID0 0x02A000A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_A2_DEVID1 0x02A100A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_A2_DEVID2 0x02A200A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_A2_DEVID3 0x02A300A2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B1_DEVID0 0x02A000B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B1_DEVID1 0x02A100B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B1_DEVID2 0x02A200B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B1_DEVID3 0x02A300B1 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B2_DEVID0 0x02A000B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B2_DEVID1 0x02A100B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B2_DEVID2 0x02A200B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_ID_NV2A_B2_DEVID3 0x02A300B2 /* ----V */
|
|
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */
|
|
#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */
|
|
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */
|
|
#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */
|
|
#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */
|
|
#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */
|
|
#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* ----V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV10 0x00000010 /* ----V */
|
|
#define NV_PMC_BOOT_0_ARCHITECTURE_NV20 0x00000020 /* C---V */
|
|
#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */
|
|
#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */
|
|
#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */
|
|
#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */
|
|
#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */
|
|
#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */
|
|
#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */
|
|
#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */
|
|
#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */
|
|
#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */
|
|
#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */
|
|
#define NV_PMC_BOOT_1 0x00000004 /* R--4R */
|
|
#define NV_PMC_BOOT_1_ENDIAN00 0:0 /* R--VF */
|
|
#define NV_PMC_BOOT_1_ENDIAN00_LITTLE 0x00000000 /* R-I-V */
|
|
#define NV_PMC_BOOT_1_ENDIAN00_BIG 0x00000001 /* R---V */
|
|
#define NV_PMC_BOOT_1_ENDIAN24 24:24 /* RW-VF */
|
|
#define NV_PMC_BOOT_1_ENDIAN24_LITTLE 0x00000000 /* RWI-V */
|
|
#define NV_PMC_BOOT_1_ENDIAN24_BIG 0x00000001 /* RW--V */
|
|
#define NV_PMC_INTR_0 0x00000100 /* RW-4R */
|
|
#define NV_PMC_INTR_0_MD 0:0 /* R--VF */
|
|
#define NV_PMC_INTR_0_MD_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_MD_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */
|
|
#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */
|
|
#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_REMAPPER 9:9 /* R--VF */
|
|
#define NV_PMC_INTR_0_REMAPPER_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_REMAPPER_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */
|
|
#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */
|
|
#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */
|
|
#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */
|
|
#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */
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#define NV_PMC_INTR_0_PCRTC2 25:25 /* R--VF */
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|
#define NV_PMC_INTR_0_PCRTC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMC_INTR_0_PCRTC2_PENDING 0x00000001 /* R---V */
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#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */
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|
#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */
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#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */
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|
#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */
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#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */
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#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */
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#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */
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|
#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */
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|
#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */
|
|
#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */
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#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */
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|
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
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#define NV_PMC_ENABLE_BUF_RESET 0:0 /* RWIVF */
|
|
#define NV_PMC_ENABLE_BUF_RESET_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_BUF_RESET_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PMC_ENABLE_MD_RESET 1:1 /* RWIVF */
|
|
#define NV_PMC_ENABLE_MD_RESET_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_MD_RESET_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PCRTC2 25:25 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PCRTC2_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PMC_ENABLE_PCRTC2_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */
|
|
#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PMC_FRAME_PROTECT_MIN 0x00000300 /* RW-4R */
|
|
#define NV_PMC_FRAME_PROTECT_MIN_VAL 28:0 /* RWIVF */
|
|
#define NV_PMC_FRAME_PROTECT_MIN_VAL0 0x00000000 /* RWI-V */
|
|
#define NV_PMC_FRAME_PROTECT_EN 31:31 /* RWIVF */
|
|
#define NV_PMC_FRAME_PROTECT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PMC_FRAME_PROTECT_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_FRAME_PROTECT_MAX 0x00000304 /* RW-4R */
|
|
#define NV_PMC_FRAME_PROTECT_MAX_VAL 28:0 /* RWIVF */
|
|
#define NV_PMC_FRAME_PROTECT_MAX_VAL0 0x00000000 /* RWI-V */
|
|
/* dev_bus.ref */
|
|
#define NV_PBUS 0x00001FFF:0x00001000 /* RW--D */
|
|
#define NV_PBUS_DEBUG_0 0x00001080 /* RW-4R */
|
|
#define NV_PBUS_DEBUG_0_FBIO_SCLK_DELAY 3:0 /* RWIUF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_SCLK_DELAY_8 0x00000008 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_SCLK_PC 4:4 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_SCLK_PC_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_SCLK_PC_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_FBCLK_DELAY 11:8 /* RWIUF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_FBCLK_DELAY_4 0x00000004 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_FBCLK_DELAY_8 0x00000008 /* RW--V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_FBCLK_PC 12:12 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_FBCLK_PC_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_FBCLK_PC_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_ACLK_DELAY 19:16 /* RWIUF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_ACLK_DELAY_8 0x00000008 /* RW--V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_ACLK_DELAY_10 0x0000000A /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_ACLK_PC 20:20 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_ACLK_PC_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_ACLK_PC_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_RCLK_DELAY 27:24 /* RWIUF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_RCLK_DELAY_8 0x00000008 /* RW--V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_RCLK_DELAY_14 0x0000000E /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_RCLK_PC 28:28 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_0_FBIO_RCLK_PC_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_0_FBIO_RCLK_PC_OVERRIDE 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1 0x00001084 /* RW-4R */
|
|
#define NV_PBUS_DEBUG_1_PCIM_THROTTLE 0:0 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIM_THROTTLE_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIM_THROTTLE_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIM_CMD 1:1 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIM_CMD_SIZE_BASED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIM_CMD_MRL_ONLY 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_HASH_DECODE 2:2 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_HASH_DECODE_1FF 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_HASH_DECODE_2FF 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_AGPM_CMD 4:3 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_AGPM_CMD_HP_ON_1ST 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_AGPM_CMD_LP_ONLY 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_AGPM_CMD_HP_ONLY 0x00000002 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_WRITE 5:5 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIS_WRITE_0_CYCLE 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_WRITE_1_CYCLE 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_2_1 6:6 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIS_2_1_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_2_1_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_RETRY 7:7 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_RETRY_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_RETRY_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_RD_BURST 8:8 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIS_RD_BURST_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_RD_BURST_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_WR_BURST 9:9 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIS_WR_BURST_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_WR_BURST_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_EARLY_RTY 10:10 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIS_EARLY_RTY_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_EARLY_RTY_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_CPUQ 12:12 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_PCIS_CPUQ_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_PCIS_CPUQ_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_DPSH_DECODE 13:13 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_DPSH_DECODE_NV4 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_DPSH_DECODE_NV3 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_FBI_DIFFERENTIAL 14:14 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_FBI_DIFFERENTIAL_ENABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_FBI_DIFFERENTIAL_DISABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_AGPFW_DWOD 15:15 /* RWIVF */
|
|
#define NV_PBUS_DEBUG_1_AGPFW_DWOD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_1_AGPFW_DWOD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_DEBUG_1_OPENGL 16:16 /* R--VF */
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#define NV_PBUS_DEBUG_1_OPENGL_OFF 0x00000000 /* R---V */
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#define NV_PBUS_DEBUG_1_OPENGL_ON 0x00000001 /* R---V */
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#define NV_PBUS_DEBUG_1_SPARE2 17:17 /* RWIVF */
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#define NV_PBUS_DEBUG_1_SPARE2_ZERO 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_SPARE2_ONE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_ACQUIRE_TIMEOUT 18:18 /* RWIVF */
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#define NV_PBUS_DEBUG_1_ACQUIRE_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_ACQUIRE_TIMEOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_SPARE4 19:19 /* RWIVF */
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#define NV_PBUS_DEBUG_1_SPARE4_ZERO 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_SPARE4_ONE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_SPARE5 20:20 /* RWIVF */
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#define NV_PBUS_DEBUG_1_SPARE5_ZERO 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_SPARE5_ONE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_AGPFW_ADIS 21:21 /* RWIVF */
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#define NV_PBUS_DEBUG_1_AGPFW_ADIS_ENABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_AGPFW_ADIS_DISABLED 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_SPARE7 22:22 /* RWIVF */
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#define NV_PBUS_DEBUG_1_SPARE7_ZERO 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_SPARE7_ONE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_SPARE8 23:23 /* RWIVF */
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#define NV_PBUS_DEBUG_1_SPARE8_ZERO 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_SPARE8_ONE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_AGP_DIN_SEL_SRC 25:25 /* RWIVF */
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#define NV_PBUS_DEBUG_1_AGP_DIN_SEL_SRC_HOST 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_AGP_DIN_SEL_SRC_ADSTB 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_PLL_PWRDWN 26:26 /* RWIVF */
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#define NV_PBUS_DEBUG_1_PLL_PWRDWN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_PLL_PWRDWN_ENABLE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_PLL_STOPCLK 27:27 /* RWIVF */
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#define NV_PBUS_DEBUG_1_PLL_STOPCLK_DISABLE 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_PLL_STOPCLK_ENABLE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_1_CORE_SLOWDWN 30:29 /* RWIVF */
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#define NV_PBUS_DEBUG_1_CORE_SLOWDWN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_1_CORE_SLOWDWN_ENABLE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_2 0x00001088 /* RW-4R */
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#define NV_PBUS_DEBUG_2_AGP_VREF 0:0 /* RWIVF */
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#define NV_PBUS_DEBUG_2_AGP_VREF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_2_AGP_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_2_AGP_SB_STB_DELAY 9:4 /* RWIUF */
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#define NV_PBUS_DEBUG_2_AGP_SB_STB_DELAY_34 0x00000022 /* RWI-V */
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#define NV_PBUS_DEBUG_2_AGP_AD_STB_DSE 12:12 /* RWIVF */
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#define NV_PBUS_DEBUG_2_AGP_AD_STB_DSE_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_2_AGP_AD_STB_DSE_ON 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_2_SAGP_VREF 16:16 /* RWIVF */
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#define NV_PBUS_DEBUG_2_SAGP_VREF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_2_SAGP_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_2_SDSP_VREF 20:20 /* RWIVF */
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#define NV_PBUS_DEBUG_2_SDSP_VREF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_2_SDSP_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_3 0x0000108C /* RW-4R */
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#define NV_PBUS_DEBUG_3_AGP_MAX_SIZE 1:0 /* RWIVF */
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#define NV_PBUS_DEBUG_3_AGP_MAX_SIZE_UNLIMITED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_3_AGP_MAX_SIZE_32_BYTES 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_MAX_SIZE_64_BYTES 0x00000002 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK 7:4 /* RWIVF */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_66MHZ 0x00000005 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_73MHZ 0x00000006 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_80MHZ 0x00000007 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_87MHZ 0x00000008 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_94MHZ 0x00000009 /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_100MHZ 0x0000000A /* RWI-V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_106MHZ 0x0000000B /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_113MHZ 0x0000000C /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_120MHZ 0x0000000D /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_126MHZ 0x0000000E /* RW--V */
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#define NV_PBUS_DEBUG_3_AGP_4X_NVCLK_ABOVE_133MHZ 0x0000000F /* RW--V */
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#define NV_PBUS_DEBUG_CTL 0x00001090 /* RW-4R */
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#define NV_PBUS_DEBUG_CTL_MODE 0:0 /* RWIVF */
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#define NV_PBUS_DEBUG_CTL_MODE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTL_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTL_READ_SELECT 4:4 /* RWIVF */
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#define NV_PBUS_DEBUG_CTL_READ_SELECT_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTL_READ_SELECT_1 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_READ 0x00001094 /* R--4R */
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#define NV_PBUS_DEBUG_READ_DATA 31:0 /* R-XUF */
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#define NV_PBUS_DEBUG_HOST 0x0000109C /* RW-4R */
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#define NV_PBUS_DEBUG_HOST_SEL 3:0 /* RWXUF */
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#define NV_PBUS_DEBUG_SEL_0 0x000010A0 /* RW-4R */
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#define NV_PBUS_DEBUG_SEL_FIELD 3:0 /* RWXUF */
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#define NV_PBUS_DEBUG_SEL_1 0x000010A4 /* RW-4R */
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#define NV_PBUS_DEBUG_SEL_FIELD 3:0 /* RWXUF */
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#define NV_PBUS_DEBUG_SEL_2 0x000010A8 /* RW-4R */
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#define NV_PBUS_DEBUG_SEL_FIELD 3:0 /* RWXUF */
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#define NV_PBUS_DEBUG_SEL_3 0x000010AC /* RW-4R */
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#define NV_PBUS_DEBUG_SEL_FIELD 3:0 /* RWXUF */
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#define NV_PBUS_DEBUG_CTRIM_0 0x000010B0 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_0_INIT 0x06236035 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_OPTIMAL 0x06436013 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_NE_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_NE_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SE_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SE_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_NW_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_NW_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SW_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SW_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_M_NW_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_M_NW_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_M_SW_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_M_SW_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_U_NW_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_U_NW_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_U_SW_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_U_SW_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_NW_TRIM 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_NW_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_FE_TRIM 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_FE_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_CA_TRIM 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_CA_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_CS_TRIM 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_CS_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SH_TRIM 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SH_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SP_TRIM 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_SP_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_FB_TRIM 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_NV_FB_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_0_SPARE_0 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_0_SPARE_0_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1 0x000010B4 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_1_INIT 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_OPTIMAL 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_C0_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C0_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C1_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C1_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C2_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C2_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C3_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C4_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C4_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C5_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C5_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C6_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C6_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_C7_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_1_C7_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_M_SHAPE 3:0 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_M_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_M_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_N_SHAPE 7:4 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_N_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_N_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_PV1_SHAPE 11:8 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_PV1_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_PV1_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_PV2_SHAPE 15:12 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_PV2_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_PV2_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_FP1_SHAPE 19:16 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_FP1_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_FP1_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_FPDP_SHAPE 23:20 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_FPDP_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_FPDP_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_FPIO_SHAPE 27:24 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_FPIO_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_FPIO_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_1_FPION_SHAPE 31:28 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_1_FPION_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_1_FPION_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_2 0x000010B8 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_2_INIT 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_OPTIMAL 0x33333333 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_2_C0_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C0_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C1_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C1_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C2_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C2_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C3_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C4_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C4_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C5_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C5_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C6_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C6_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_2_C7_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_2_C7_DELAY_0 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_0_SHAPE 3:0 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_0_SHAPE_0 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_0_SHAPE_INIT 0x00000000 /* RW--V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_1_SHAPE 7:4 /* RWISF */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_1_SHAPE_0 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_1_SHAPE_INIT 0x00000000 /* RW--V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_2_SHAPE 11:8 /* RWISF */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2I_2_SHAPE_0 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2I_2_SHAPE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2I_3_SHAPE 15:12 /* RWISF */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_3_SHAPE_0 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2I_3_SHAPE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_0_SHAPE 19:16 /* RWISF */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2O_0_SHAPE_0 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2O_0_SHAPE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_1_SHAPE 23:20 /* RWISF */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2O_1_SHAPE_0 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_2_M2O_1_SHAPE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_2_SHAPE 27:24 /* RWISF */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_2_SHAPE_0 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_2_SHAPE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_3_SHAPE 31:28 /* RWISF */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_3_SHAPE_0 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_DEBUG_CTRIM_2_M2O_3_SHAPE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_3 0x000010BC /* RW-4R */
|
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#define NV_PBUS_DEBUG_CTRIM_3_INIT 0x00001300 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_3_OPTIMAL 0x00001300 /* RW--V */
|
|
#define NV_PBUS_DEBUG_CTRIM_3_C0_DELAY 3:0 /* RWIUF */
|
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#define NV_PBUS_DEBUG_CTRIM_3_C0_DELAY_8 0x00000003 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_3_C1_DELAY 7:4 /* RWIUF */
|
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#define NV_PBUS_DEBUG_CTRIM_3_C1_DELAY_8 0x00000000 /* RWI-V */
|
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#define NV_PBUS_DEBUG_CTRIM_3_C2_DELAY 11:8 /* RWIUF */
|
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#define NV_PBUS_DEBUG_CTRIM_3_C2_DELAY_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_C3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_C3_DELAY_8 0x00000003 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_C4_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_C4_DELAY_8 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_C5_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_C5_DELAY_8 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_C6_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_C6_DELAY_F 0x0000000f /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_C7_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_C7_DELAY_F 0x0000000f /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_CCIR_CLK_OUT_TRIM 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_CCIR_CLK_OUT_TRIM_8 0x00000003 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_CCIR_CLK_OUT_TRIM_INIT 0x00000003 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_PCLK1_TRIM 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_PCLK1_TRIM_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_PCLK1_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_VCLK1_TRIM 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_VCLK1_TRIM_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_VCLK1_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_VSCLK_TRIM 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_VSCLK_TRIM_8 0x00000003 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_VSCLK_TRIM_INIT 0x00000003 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_PCLK2_TRIM 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_PCLK2_TRIM_8 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_PCLK2_TRIM_INIT 0x00000002 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_VCLK2_TRIM 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_VCLK2_TRIM_8 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_VCLK2_TRIM_INIT 0x00000002 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_NVCLK 24:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_NVCLK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_NVCLK_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_MCLK 25:25 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_MCLK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_MCLK_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CLK4X 26:26 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CLK4X_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CLK4X_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CCIR_O 27:27 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CCIR_O_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CCIR_O_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_VIP_HCLK 28:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_VIP_HCLK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_VIP_HCLK_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_VCLK2 29:29 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_VCLK2_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_VCLK2_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_PCLK 30:30 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_PCLK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_PCLK_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CCIR2 31:31 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CCIR2_ENABLE 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_3_BYPASS_CCIR2_EN_INIT 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4 0x000010C4 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_4_INIT 0x46AB5081 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_OPTIMAL 0x00432465 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_C0_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C0_DELAY_8 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C1_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C1_DELAY_8 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C2_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C2_DELAY_8 0x00000003 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C3_DELAY_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C4_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C4_DELAY_8 0x0000000C /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C5_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C5_DELAY_8 0x0000000B /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C6_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C6_DELAY_8 0x0000000D /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_C7_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_C7_DELAY_8 0x0000000A /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_0_TRIM 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_0_TRIM_8 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_0_TRIM_INIT 0x00000005 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_1_TRIM 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_1_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_1_TRIM_INIT 0x00000006 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_2_TRIM 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_2_TRIM_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_2_TRIM_INIT 0x00000004 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_3_TRIM 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_3_TRIM_8 0x00000005 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2I_3_TRIM_INIT 0x00000002 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_0_TRIM 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_0_TRIM_8 0x0000000B /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_0_TRIM_INIT 0x00000003 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_1_TRIM 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_1_TRIM_8 0x0000000A /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_1_TRIM_INIT 0x00000004 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_2_TRIM 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_2_TRIM_8 0x00000006 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_2_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_3_TRIM 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_3_TRIM_8 0x00000004 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_4_M2O_3_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5 0x000010C8 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_5_INIT 0x00401300 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_OPTIMAL 0x000000FF /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_C0_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C0_DELAY_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C1_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C1_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C2_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C2_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C3_DELAY_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C4_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C4_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C5_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C5_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C6_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C6_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_C7_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_C7_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPIOCLK_TRIM 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_FPIOCLK_TRIM_8 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPIOCLK_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPIONCLK_TRIM 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_FPIONCLK_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPIONCLK_TRIM_INIT 0x00000008 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPDPCLK_TRIM 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_FPDPCLK_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPDPCLK_TRIM_INIT 0x00000008 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPCLK1_TRIM 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_FPCLK1_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPCLK1_TRIM_INIT 0x00000008 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPCLK2_TRIM 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_FPCLK2_TRIM_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_FPCLK2_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_IFPCLK1_TRIM 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_IFPCLK1_TRIM_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_IFPCLK1_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_IFPCLK2_TRIM 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_IFPCLK2_TRIM_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_IFPCLK2_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_5_M_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_5_M_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_5_M_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6 0x000010CC /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_6_INIT 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_OPTIMAL 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_C0_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C0_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C1_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C1_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C2_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C2_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C3_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C4_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C4_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C5_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C5_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C6_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C6_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_C7_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_C7_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_0_DELAY 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_0_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_0_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_1_DELAY 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_1_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_1_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_2_DELAY 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_2_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_2_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_3_DELAY 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_3_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2I_3_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_0_DELAY 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_0_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_0_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_1_DELAY 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_1_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_1_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_2_DELAY 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_2_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_2_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_3_DELAY 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_3_DELAY_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_6_FBIO_M2O_3_DELAY_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_AGPPLL 0x000010C0 /* RW-4R */
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#define NV_PBUS_DEBUG_AGPPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PBUS_DEBUG_AGPPLL_COEFF_MDIV_1 0x00000001 /* RWI-V */
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#define NV_PBUS_DEBUG_AGPPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PBUS_DEBUG_AGPPLL_COEFF_NDIV_4 0x00000004 /* RWI-V */
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#define NV_PBUS_DEBUG_AGPPLL_SETUP 24:16 /* RWIUF */
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#define NV_PBUS_DEBUG_AGPPLL_SETUP_DEFAULT 0x0000011C /* RWI-V */
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#define NV_PBUS_DEBUG_AGPPLL_PWRDWN 28:28 /* RWIVF */
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#define NV_PBUS_DEBUG_AGPPLL_PWRDWN_ON 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_AGPPLL_PWRDWN_OFF 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_AGPPLL_STATUS 31:31 /* R--VF */
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#define NV_PBUS_DEBUG_AGPPLL_STATUS_NOTLOCKED 0x00000000 /* R---V */
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#define NV_PBUS_DEBUG_AGPPLL_STATUS_LOCKED 0x00000001 /* R---V */
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#define NV_PBUS_DEBUG_PORT 0x000010D0 /* RW-4R */
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#define NV_PBUS_DEBUG_PORT_MODE 0:0 /* RWIVF */
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#define NV_PBUS_DEBUG_PORT_MODE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PORT_MODE_AGP4X 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7 0x000010D4 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_7_INIT 0x00000002 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_OPTIMAL 0x09000002 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_CCDP_TRIM 3:0 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_CCDP_TRIM_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_CCDP_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_CCDP_SHAPE 7:4 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_CCDP_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_CCDP_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_CCIO_SHAPE 11:8 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_CCIO_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_CCIO_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_FP2_SHAPE 15:12 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_FP2_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_FP2_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_IFP1_SHAPE 19:16 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_IFP1_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_IFP1_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_IFP2_SHAPE 23:20 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_IFP2_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_IFP2_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_PCLK1_DP_TRIM 27:24 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_PCLK1_DP_TRIM_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_PCLK1_DP_TRIM_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_7_PCLK1_DP_SHAPE 31:28 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_7_PCLK1_DP_SHAPE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_7_PCLK1_DP_SHAPE_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8 0x000010D8 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_0 3:0 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_0_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_0_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_1 7:4 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_1_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_1_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_2 11:8 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_2_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_2_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_3 15:12 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_3_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_3_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_4 19:16 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_4_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_4_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_5 23:20 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_5_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_5_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_6 27:24 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_6_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_6_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_7 31:28 /* RWISF */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_7_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_8_DQSOB_7_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_9 0x000010DC /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_9_INIT 0x00003211 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_OPTIMAL 0x00004301 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA0_TRIM 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA0_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA1_TRIM 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA1_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA2_TRIM 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA2_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA3_TRIM 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_PA3_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_CM_TRIM 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_CM_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_TM_TRIM 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_TM_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_XF_TRIM 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_XF_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_NB_TRIM 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_9_NV_NB_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC 0x000010E0 /* RW-4R */
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#define NV_PBUS_DEBUG_PRIV_ASRC_0__ALIAS_1 NV_PBUS_DEBUG_PRIV_ASRC /* */
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#define NV_PBUS_DEBUG_PRIV_ASRC_EAST_SEL 31:31 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_EAST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_EAST_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_EAST_VALUE 30:24 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_EAST_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_SOUTH_SEL 23:23 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_SOUTH_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_SOUTH_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_SOUTH_VALUE 22:16 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_SOUTH_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_WEST_SEL 15:15 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_WEST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_WEST_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_WEST_VALUE 14:8 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_WEST_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_NORTH_SEL 7:7 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_NORTH_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_NORTH_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_NORTH_VALUE 6:0 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_NORTH_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1 0x000010E4 /* RW-4R */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_0_SEL 31:31 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_0_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_0_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_0_VALUE 30:24 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_0_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_1_SEL 23:23 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_1_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_1_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_1_VALUE 22:16 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_1_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_2_SEL 15:15 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_2_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_2_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_2_VALUE 14:8 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_2_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_3_SEL 7:7 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_3_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_3_OVERIDE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_3_VALUE 6:0 /* RWIVF */
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#define NV_PBUS_DEBUG_PRIV_ASRC_1_BK_3_VALUE_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10 0x000010E8 /* RW-4R */
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#define NV_PBUS_DEBUG_CTRIM_10_INIT 0x00021193 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_OPTIMAL 0x00031163 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_NW_TRIM 3:0 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_NW_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_FB_TRIM 7:4 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_FB_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA0_TRIM 11:8 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA0_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA1_TRIM 15:12 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA1_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA2_TRIM 19:16 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA2_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA3_TRIM 23:20 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_PA3_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_M_NB_TRIM 27:24 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_M_NB_TRIM_8 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_SPARE_1 31:28 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_SPARE_1_INIT 0x00000008 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_BYPASS_MCLK2 31:31 /* RWIUF */
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#define NV_PBUS_DEBUG_CTRIM_10_BYPASS_MCLK2_DISABLE 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_CTRIM_10_BYPASS_MCLK2_ENABLE 0x00000001 /* RW--V */
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#define NV_PBUS_DEBUG_CTRIM_10_BYPASS_MCLK2_EN_INIT 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010F0 /* RW-4R */
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#define NV_PBUS_DEBUG_DUALHEAD_CTL_BLAH 31:0 /* RWIUF */
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#define NV_PBUS_DEBUG_DUALHEAD_CTL_BLAH_0 0x00000000 /* RWI-V */
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#define NV_PBUS_DEBUG_RDIBIST_CTL 0x000010F4 /* RW-4R */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_RAM_FIRST 10:0 /* RWXVF */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_RAM_FIRST_0 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_TEST 15:15 /* RWIVF */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_TEST_GO 0x00000001 /* -W--V */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_TEST_RUNNING 0x00000001 /* R---V */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_TEST_DONE 0x00000000 /* R-I-V */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_RAM_LAST 26:16 /* RWXVF */
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#define NV_PBUS_DEBUG_RDIBIST_CTL_RAM_LAST_7FF 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX 0x000010F8 /* RW-4R */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_ADDR 4:0 /* RWXVF */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_ADDR_0 0x00000000 /* RW--V */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_31_0 0x00000000 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_63_32 0x00000001 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_95_64 0x00000002 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_127_96 0x00000003 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_159_128 0x00000004 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_191_160 0x00000005 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_223_192 0x00000006 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_255_224 0x00000007 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_287_256 0x00000008 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_319_288 0x00000009 /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_PASS_351_320 0x0000000A /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_FAIL_RAM 0x0000000B /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_FAIL_DWORD 0x0000000C /* */
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#define NV_PBUS_DEBUG_RDIBIST_INDEX_BIST_FAIL 0x0000000D /* */
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#define NV_PBUS_DEBUG_RDIBIST_DATA 0x000010FC /* RW-4R */
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#define NV_PBUS_DEBUG_RDIBIST_DATA_VALUE 31:0 /* RWXVF */
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#define NV_PBUS_INTR_0 0x00001100 /* RW-4R */
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#define NV_PBUS_INTR_0_PCI_BUS_ERROR 0:0 /* RWXVF */
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#define NV_PBUS_INTR_0_PCI_BUS_ERROR_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PBUS_INTR_0_PCI_BUS_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PBUS_INTR_0_PCI_BUS_ERROR_RESET 0x00000001 /* -W--V */
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#define NV_PBUS_INTR_0_HOTPLUG 4:4 /* RWXVF */
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#define NV_PBUS_INTR_0_HOTPLUG_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PBUS_INTR_0_HOTPLUG_PENDING 0x00000001 /* R---V */
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#define NV_PBUS_INTR_0_HOTPLUG_RESET 0x00000001 /* -W--V */
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#define NV_PBUS_INTR_EN_0 0x00001140 /* RWI4R */
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#define NV_PBUS_INTR_EN_0_PCI_BUS_ERROR 0:0 /* RWIVF */
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#define NV_PBUS_INTR_EN_0_PCI_BUS_ERROR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_INTR_EN_0_PCI_BUS_ERROR_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_INTR_EN_0_HOTPLUG 4:4 /* RWIVF */
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#define NV_PBUS_INTR_EN_0_HOTPLUG_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_INTR_EN_0_HOTPLUG_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_ROM_CONFIG 0x00001200 /* RWI4R */
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#define NV_PBUS_ROM_CONFIG_TW1 5:0 /* RWIVF */
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#define NV_PBUS_ROM_CONFIG_TW1_DEFAULT 0x0000003F /* RWI-V */
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#define NV_PBUS_ROM_CONFIG_TW0 7:6 /* RWIVF */
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#define NV_PBUS_ROM_CONFIG_TW0_DEFAULT 0x00000003 /* RWI-V */
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#define NV_PBUS_FBIO_CFG 0x00001210 /* RW-4R */
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#define NV_PBUS_FBIO_CFG_ADR_EDGE 0:0 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_ADR_EDGE_QUARTER 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_CFG_ADR_EDGE_HALF 0x00000001 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_CLK_EDGE 4:4 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_CLK_EDGE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_CLK_EDGE_EARLY 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DQS_EDGE 8:8 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_DQS_EDGE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_DQS_EDGE_EARLY 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CFG_WRITE_DATA 12:12 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_WRITE_DATA_STROBED 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_WRITE_DATA_CLOCKED 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CFG_QUSE 17:16 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_QUSE_NORMAL 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_CFG_QUSE_ALWAYS 0x00000001 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_QUSE_HOLD 0x00000002 /* RW--V */
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#define NV_PBUS_FBIO_CFG_QUSE_RESERVED 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_CFG_RESERVED0 20:20 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_RESERVED0_0 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_RESERVED0_1 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DQSEN 25:24 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_DQSEN_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_DQSEN_HOLD 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DQSEN_PULL 0x00000002 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DQSEN_EXTENDED 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DEN 27:26 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_DEN_NORMAL 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_DEN_HOLD 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DEN_EARLY 0x00000002 /* RW--V */
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#define NV_PBUS_FBIO_CFG_DEN_EXTENDED 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_CFG_RESERVED1 28:28 /* RWIVF */
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#define NV_PBUS_FBIO_CFG_RESERVED1_0 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CFG_RESERVED1_1 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_DLY 0x00001214 /* RW-4R */
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#define NV_PBUS_FBIO_DLY_DATAIB_A 2:0 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DATAIB_A_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DATAIB_A_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_CLKIC_A 4:3 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_CLKIC_A_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_CLKIC_A_FULL 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_A 7:5 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DQSIB_A_NONE 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_A_INIT 0x00000006 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DQSIB_A_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DATAIB_B 10:8 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DATAIB_B_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DATAIB_B_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_CLKIC_B 12:11 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_CLKIC_B_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_CLKIC_B_FULL 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_B 15:13 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DQSIB_B_NONE 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_B_INIT 0x00000006 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DQSIB_B_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DATAIB_C 18:16 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DATAIB_C_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DATAIB_C_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_CLKIC_C 20:19 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_CLKIC_C_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_CLKIC_C_FULL 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_C 23:21 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DQSIB_C_NONE 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_C_INIT 0x00000006 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DQSIB_C_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DATAIB_D 26:24 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DATAIB_D_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DATAIB_D_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_DLY_CLKIC_D 28:27 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_CLKIC_D_NONE 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_CLKIC_D_FULL 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_D 31:29 /* RWIUF */
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#define NV_PBUS_FBIO_DLY_DQSIB_D_NONE 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_DLY_DQSIB_D_INIT 0x00000006 /* RWI-V */
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#define NV_PBUS_FBIO_DLY_DQSIB_D_FULL 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_RAM 0x00001218 /* RW-4R */
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#define NV_PBUS_FBIO_RAM_DQS_SIZE 0:0 /* RWIVF */
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#define NV_PBUS_FBIO_RAM_DQS_SIZE_32 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_RAM_DQS_SIZE_8 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_RAM_TYPE 8:8 /* RWIUF */
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#define NV_PBUS_FBIO_RAM_TYPE_DDR 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_RAM_TYPE_SDR 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_RAM_VREF 16:16 /* RWIUF */
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#define NV_PBUS_FBIO_RAM_VREF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_RAM_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_RAM_RESERVED0 24:24 /* RWIUF */
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#define NV_PBUS_FBIO_RAM_RESERVED0_0 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_RAM_RESERVED0_1 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALCNT 0x0000121C /* RW-4R */
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#define NV_PBUS_FBIO_CALCNT_COUNT 31:0 /* RW-SF */
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#define NV_PBUS_FBIO_CALCNT_OVERFLOW 31:31 /* RW-VF */
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#define NV_PBUS_FBIO_CALEN 0x00001220 /* RW-4R */
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#define NV_PBUS_FBIO_CALEN_VCC_A 0:0 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCC_A_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCC_A_ON 0x00000001 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCC_B 1:1 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCC_B_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCC_B_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_VCC_C 2:2 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCC_C_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCC_C_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_VCC_D 3:3 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCC_D_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCC_D_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_A 8:8 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCCQ_A_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_A_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_B 9:9 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCCQ_B_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_B_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_C 10:10 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCCQ_C_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_C_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_D 11:11 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_VCCQ_D_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_VCCQ_D_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_PN_A 16:16 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_PN_A_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_PN_A_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_PN_B 17:17 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_PN_B_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_PN_B_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_PN_C 18:18 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_PN_C_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_PN_C_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALEN_PN_D 19:19 /* RWIVF */
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#define NV_PBUS_FBIO_CALEN_PN_D_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALEN_PN_D_ON 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALPN 0x00001224 /* R--4R */
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#define NV_PBUS_FBIO_CALPN_A 4:0 /* R--VF */
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#define NV_PBUS_FBIO_CALPN_B 12:8 /* R--VF */
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#define NV_PBUS_FBIO_CALPN_C 20:16 /* R--VF */
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#define NV_PBUS_FBIO_CALPN_D 28:24 /* R--VF */
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#define NV_PBUS_FBIO_CALSEL 0x00001228 /* RW-4R */
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#define NV_PBUS_FBIO_CALSEL_SOURCE 3:0 /* RW-VF */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCC_A 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCC_B 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCC_C 0x00000002 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCC_D 0x00000003 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCCQ_A 0x00000004 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCCQ_B 0x00000005 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCCQ_C 0x00000006 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_VCCQ_D 0x00000007 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_PCI 0x00000008 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_CORE 0x00000009 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_RESERVED0 0x0000000A /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_RESERVED1 0x0000000B /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_RESERVED2 0x0000000C /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_RESERVED3 0x0000000D /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_RESERVED4 0x0000000E /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_SOURCE_RESERVED5 0x0000000F /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_REF_SEL 8:8 /* RWIVF */
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#define NV_PBUS_FBIO_CALSEL_REF_SEL_XTAL 0x00000000 /* RWI-V */
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#define NV_PBUS_FBIO_CALSEL_REF_SEL_PCICLK 0x00000001 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_REF_DIV 19:16 /* RW-UF */
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#define NV_PBUS_FBIO_CALSEL_REF_DIV_0 0x00000000 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_REF_DIV_4 0x00000004 /* RW--V */
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#define NV_PBUS_FBIO_CALSEL_REF_DIV_16 0x0000000F /* RW--V */
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#define NV_PBUS_FBIO_ADRDRV 0x0000122C /* RW-4R */
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#define NV_PBUS_FBIO_ADRDRV_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_A_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_A_RISE 7:4 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_A_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_B_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_B_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_C_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_C_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_D_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRDRV_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_ADRDRV_D_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV 0x00001230 /* RW-4R */
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#define NV_PBUS_FBIO_CLKDRV_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_A_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_A_RISE 7:4 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_A_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_B_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_B_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_C_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_C_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_D_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKDRV_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_CLKDRV_D_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV 0x00001234 /* RW-4R */
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#define NV_PBUS_FBIO_DATDRV_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_A_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_A_RISE 7:4 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_A_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_B_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_B_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_C_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_C_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_D_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DATDRV_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_DATDRV_D_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV 0x00001238 /* RW-4R */
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#define NV_PBUS_FBIO_DQSDRV_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_A_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_A_RISE 7:4 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_A_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_B_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_B_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_C_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_C_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_D_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DQSDRV_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_DQSDRV_D_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW 0x0000123C /* RW-4R */
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#define NV_PBUS_FBIO_ADRSLW_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_A_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_A_RISE 7:4 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_A_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_B_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_B_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_C_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_C_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_D_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_ADRSLW_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_ADRSLW_D_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW 0x00001240 /* RW-4R */
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#define NV_PBUS_FBIO_CLKSLW_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_A_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_A_RISE 7:4 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_A_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_B_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_B_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_C_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_C_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_D_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_CLKSLW_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_CLKSLW_D_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DATSLW 0x00001244 /* RW-4R */
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#define NV_PBUS_FBIO_DATSLW_A_FALL 3:0 /* RWIUF */
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#define NV_PBUS_FBIO_DATSLW_A_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_DATSLW_A_RISE 7:4 /* RWIUF */
|
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#define NV_PBUS_FBIO_DATSLW_A_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_FBIO_DATSLW_B_FALL 11:8 /* RWIUF */
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#define NV_PBUS_FBIO_DATSLW_B_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_DATSLW_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_DATSLW_B_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_FBIO_DATSLW_C_FALL 19:16 /* RWIUF */
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|
#define NV_PBUS_FBIO_DATSLW_C_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_DATSLW_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_DATSLW_C_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_FBIO_DATSLW_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_DATSLW_D_FALL_INIT 0x0000000B /* RWIUV */
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|
#define NV_PBUS_FBIO_DATSLW_D_RISE 31:28 /* RWIUF */
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|
#define NV_PBUS_FBIO_DATSLW_D_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_FBIO_DQSSLW 0x00001248 /* RW-4R */
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#define NV_PBUS_FBIO_DQSSLW_A_FALL 3:0 /* RWIUF */
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|
#define NV_PBUS_FBIO_DQSSLW_A_FALL_INIT 0x0000000B /* RWIUV */
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|
#define NV_PBUS_FBIO_DQSSLW_A_RISE 7:4 /* RWIUF */
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|
#define NV_PBUS_FBIO_DQSSLW_A_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_FBIO_DQSSLW_B_FALL 11:8 /* RWIUF */
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|
#define NV_PBUS_FBIO_DQSSLW_B_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_DQSSLW_B_RISE 15:12 /* RWIUF */
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#define NV_PBUS_FBIO_DQSSLW_B_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_FBIO_DQSSLW_C_FALL 19:16 /* RWIUF */
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#define NV_PBUS_FBIO_DQSSLW_C_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_DQSSLW_C_RISE 23:20 /* RWIUF */
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#define NV_PBUS_FBIO_DQSSLW_C_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_FBIO_DQSSLW_D_FALL 27:24 /* RWIUF */
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#define NV_PBUS_FBIO_DQSSLW_D_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_FBIO_DQSSLW_D_RISE 31:28 /* RWIUF */
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#define NV_PBUS_FBIO_DQSSLW_D_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_DISPIO_PADCTL 0x0000124C /* RW-4R */
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#define NV_PBUS_DISPIO_PADCTL_DATSLW_FALL 3:0 /* RWIUF */
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#define NV_PBUS_DISPIO_PADCTL_DATSLW_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_DISPIO_PADCTL_DATSLW_RISE 7:4 /* RWIUF */
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#define NV_PBUS_DISPIO_PADCTL_DATSLW_RISE_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_DISPIO_PADCTL_DATDRV_FALL 11:8 /* RWIUF */
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|
#define NV_PBUS_DISPIO_PADCTL_DATDRV_FALL_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_DISPIO_PADCTL_DATDRV_RISE 15:12 /* RWIUF */
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#define NV_PBUS_DISPIO_PADCTL_DATDRV_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_DISPIO_PADCTL_STBSLW_FALL 19:16 /* RWIUF */
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#define NV_PBUS_DISPIO_PADCTL_STBSLW_FALL_INIT 0x0000000B /* RWIUV */
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#define NV_PBUS_DISPIO_PADCTL_STBSLW_RISE 23:20 /* RWIUF */
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|
#define NV_PBUS_DISPIO_PADCTL_STBSLW_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_DISPIO_PADCTL_STBDRV_FALL 27:24 /* RWIUF */
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|
#define NV_PBUS_DISPIO_PADCTL_STBDRV_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_DISPIO_PADCTL_STBDRV_RISE 31:28 /* RWIUF */
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|
#define NV_PBUS_DISPIO_PADCTL_STBDRV_RISE_INIT 0x00000007 /* RWIUV */
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#define NV_PBUS_TVDIO_PADCTL 0x00001250 /* RW-4R */
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#define NV_PBUS_TVDIO_PADCTL_DATSLW_FALL 3:0 /* RWIUF */
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#define NV_PBUS_TVDIO_PADCTL_DATSLW_FALL_INIT 0x0000000B /* RWIUV */
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|
#define NV_PBUS_TVDIO_PADCTL_DATSLW_RISE 7:4 /* RWIUF */
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|
#define NV_PBUS_TVDIO_PADCTL_DATSLW_RISE_INIT 0x00000008 /* RWIUV */
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|
#define NV_PBUS_TVDIO_PADCTL_DATDRV_FALL 11:8 /* RWIUF */
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|
#define NV_PBUS_TVDIO_PADCTL_DATDRV_FALL_INIT 0x00000008 /* RWIUV */
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#define NV_PBUS_TVDIO_PADCTL_DATDRV_RISE 15:12 /* RWIUF */
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#define NV_PBUS_TVDIO_PADCTL_DATDRV_RISE_INIT 0x00000007 /* RWIUV */
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|
#define NV_PBUS_TVDIO_PADCTL_VREF 31:31 /* RWIUF */
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|
#define NV_PBUS_TVDIO_PADCTL_VREF_DISABLED 0x00000000 /* RWIUV */
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|
#define NV_PBUS_TVDIO_PADCTL_VREF_ENABLED 0x00000001 /* RW-UV */
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|
#define NV_PBUS_PRIV_ASRC_2 0x00001254 /* RW-4R */
|
|
#define NV_PBUS_PRIV_ASRC_V33_OB 7:0 /* RWIUF */
|
|
#define NV_PBUS_PRIV_ASRC_V33_OB_INIT 0x00000000 /* RWIUV */
|
|
#define NV_PBUS_PRIV_ASRC_V25_OB 15:8 /* RWIUF */
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|
#define NV_PBUS_PRIV_ASRC_V25_OB_INIT 0x00000000 /* RWIUV */
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|
#define NV_PBUS_PRIV_ASRC_V33_IB 22:16 /* R-XUF */
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|
#define NV_PBUS_PRIV_ASRC_V25_IB 30:24 /* R-XUF */
|
|
#define NV_PBUS_TVDIO_CALCNT 0x00001260 /* RW-4R */
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|
#define NV_PBUS_TVDIO_CALCNT_COUNT 31:0 /* RW-SF */
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|
#define NV_PBUS_TVDIO_CALCNT_OVERFLOW 31:31 /* RW-VF */
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|
#define NV_PBUS_TVDIO_CALEN 0x00001264 /* RW-4R */
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|
#define NV_PBUS_TVDIO_CALEN_VCC_A 0:0 /* RWIVF */
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|
#define NV_PBUS_TVDIO_CALEN_VCC_A_OFF 0x00000000 /* RWI-V */
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|
#define NV_PBUS_TVDIO_CALEN_VCC_A_ON 0x00000001 /* RWI-V */
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|
#define NV_PBUS_TVDIO_CALEN_VCCQ_A 8:8 /* RWIVF */
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|
#define NV_PBUS_TVDIO_CALEN_VCCQ_A_OFF 0x00000000 /* RWI-V */
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|
#define NV_PBUS_TVDIO_CALEN_VCCQ_A_ON 0x00000001 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALEN_PN_A 16:16 /* RWIVF */
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|
#define NV_PBUS_TVDIO_CALEN_PN_A_OFF 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_TVDIO_CALEN_PN_A_ON 0x00000001 /* RW--V */
|
|
#define NV_PBUS_TVDIO_CALPN 0x00001268 /* R--4R */
|
|
#define NV_PBUS_TVDIO_CALPN_A 4:0 /* R--VF */
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|
#define NV_PBUS_TVDIO_CALSEL 0x0000126C /* RW-4R */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE 3:0 /* RW-VF */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED0 0x00000000 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED1 0x00000001 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED2 0x00000002 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED3 0x00000003 /* RW--V */
|
|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_VCCQ_A 0x00000004 /* RW--V */
|
|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED4 0x00000005 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED5 0x00000006 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED6 0x00000007 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_PCI 0x00000008 /* RW--V */
|
|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_CORE 0x00000009 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED7 0x0000000A /* RW--V */
|
|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED8 0x0000000B /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVED9 0x0000000C /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVEDA 0x0000000D /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVEDB 0x0000000E /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_SOURCE_RESERVEDC 0x0000000F /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_REF_SEL 8:8 /* RWIVF */
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#define NV_PBUS_TVDIO_CALSEL_REF_SEL_XTAL 0x00000000 /* RWI-V */
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|
#define NV_PBUS_TVDIO_CALSEL_REF_SEL_PCICLK 0x00000001 /* RW--V */
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|
#define NV_PBUS_TVDIO_CALSEL_REF_DIV 19:16 /* RW-UF */
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#define NV_PBUS_TVDIO_CALSEL_REF_DIV_0 0x00000000 /* RW--V */
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#define NV_PBUS_TVDIO_CALSEL_REF_DIV_4 0x00000004 /* RW--V */
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#define NV_PBUS_TVDIO_CALSEL_REF_DIV_16 0x0000000F /* RW--V */
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#define NV_PBUS_PCI_NV_0 0x00001800 /* R--4R */
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#define NV_PBUS_PCI_NV_0__ALIAS_1 NV_CONFIG_PCI_NV_0 /* */
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#define NV_PBUS_PCI_NV_0_VENDOR_ID 15:0 /* C--UF */
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#define NV_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA_SGS 0x000012D2 /* ----V */
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#define NV_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA 0x000010DE /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC 18:16 /* C--UF */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_VGA 0x00000000 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_ALT1 0x00000001 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_ALT2 0x00000002 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_ALT3 0x00000003 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_LC0 0x00000004 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_LC1 0x00000005 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_LC2 0x00000006 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_FUNC_LC3 0x00000007 /* C---V */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP 31:19 /* C--UF */
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#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV0 0x00000000 /* ----V */
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|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV1 0x00000001 /* ----V */
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|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV2 0x00000002 /* ----V */
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|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV3 0x00000003 /* ----V */
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|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV4 0x00000004 /* ----V */
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|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV5 0x00000005 /* ----V */
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|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV10 0x00000010 /* ----V */
|
|
#define NV_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV20 0x00000020 /* C---V */
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|
#define NV_PBUS_PCI_NV_1 0x00001804 /* RW-4R */
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|
#define NV_PBUS_PCI_NV_1__ALIAS_1 NV_CONFIG_PCI_NV_1 /* */
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|
#define NV_PBUS_PCI_NV_1_IO_SPACE 0:0 /* RWIVF */
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|
#define NV_PBUS_PCI_NV_1_IO_SPACE_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PBUS_PCI_NV_1_IO_SPACE_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PBUS_PCI_NV_1_MEMORY_SPACE 1:1 /* RWIVF */
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|
#define NV_PBUS_PCI_NV_1_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PBUS_PCI_NV_1_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_PCI_NV_1_BUS_MASTER 2:2 /* RWIVF */
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|
#define NV_PBUS_PCI_NV_1_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_PCI_NV_1_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_PCI_NV_1_WRITE_AND_INVAL 4:4 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_1_WRITE_AND_INVAL_DISABLED 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_1_WRITE_AND_INVAL_ENABLED 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_1_PALETTE_SNOOP 5:5 /* RWIVF */
|
|
#define NV_PBUS_PCI_NV_1_PALETTE_SNOOP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_PCI_NV_1_PALETTE_SNOOP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_PCI_NV_1_CAPLIST 20:20 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_1_CAPLIST_NOT_PRESENT 0x00000000 /* ----V */
|
|
#define NV_PBUS_PCI_NV_1_CAPLIST_PRESENT 0x00000001 /* C---V */
|
|
#define NV_PBUS_PCI_NV_1_66MHZ 21:21 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_1_66MHZ_INCAPABLE 0x00000000 /* ----V */
|
|
#define NV_PBUS_PCI_NV_1_66MHZ_CAPABLE 0x00000001 /* C---V */
|
|
#define NV_PBUS_PCI_NV_1_FAST_BACK2BACK 23:23 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_1_FAST_BACK2BACK_INCAPABLE 0x00000000 /* ----V */
|
|
#define NV_PBUS_PCI_NV_1_FAST_BACK2BACK_CAPABLE 0x00000001 /* C---V */
|
|
#define NV_PBUS_PCI_NV_1_DEVSEL_TIMING 26:25 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_1_DEVSEL_TIMING_FAST 0x00000000 /* ----V */
|
|
#define NV_PBUS_PCI_NV_1_DEVSEL_TIMING_MEDIUM 0x00000001 /* C---V */
|
|
#define NV_PBUS_PCI_NV_1_DEVSEL_TIMING_SLOW 0x00000002 /* ----V */
|
|
#define NV_PBUS_PCI_NV_1_SIGNALED_TARGET 27:27 /* RWIVF */
|
|
#define NV_PBUS_PCI_NV_1_SIGNALED_TARGET_NO_ABORT 0x00000000 /* R-I-V */
|
|
#define NV_PBUS_PCI_NV_1_SIGNALED_TARGET_ABORT 0x00000001 /* R---V */
|
|
#define NV_PBUS_PCI_NV_1_SIGNALED_TARGET_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_TARGET 28:28 /* RWIVF */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_TARGET_NO_ABORT 0x00000000 /* R-I-V */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_TARGET_ABORT 0x00000001 /* R---V */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_TARGET_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_MASTER 29:29 /* RWIVF */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_MASTER_NO_ABORT 0x00000000 /* R-I-V */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_MASTER_ABORT 0x00000001 /* R---V */
|
|
#define NV_PBUS_PCI_NV_1_RECEIVED_MASTER_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_PBUS_PCI_NV_1_CFG2RMA_MAPPING 30:30 /* RWIVF */
|
|
#define NV_PBUS_PCI_NV_1_CFG2RMA_MAPPING_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_PCI_NV_1_CFG2RMA_MAPPING_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PBUS_PCI_NV_2 0x00001808 /* R--4R */
|
|
#define NV_PBUS_PCI_NV_2__ALIAS_1 NV_CONFIG_PCI_NV_2 /* */
|
|
#define NV_PBUS_PCI_NV_2_REVISION_ID 7:0 /* C--UF */
|
|
#define NV_PBUS_PCI_NV_2_REVISION_ID_A01 0x000000A1 /* C---V */
|
|
#define NV_PBUS_PCI_NV_2_REVISION_ID_B01 0x000000B1 /* ----V */
|
|
#define NV_PBUS_PCI_NV_2_CLASS_CODE 31:8 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_2_CLASS_CODE_VGA 0x00030000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_2_CLASS_CODE_MULTIMEDIA 0x00048000 /* ----V */
|
|
#define NV_PBUS_PCI_NV_3 0x0000180C /* RW-4R */
|
|
#define NV_PBUS_PCI_NV_3__ALIAS_1 NV_CONFIG_PCI_NV_3 /* */
|
|
#define NV_PBUS_PCI_NV_3_LATENCY_TIMER 15:11 /* RWIUF */
|
|
#define NV_PBUS_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x00000000 /* RWI-V */
|
|
#define NV_PBUS_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x00000001 /* RW--V */
|
|
#define NV_PBUS_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x0000001E /* RW--V */
|
|
#define NV_PBUS_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x0000001F /* RW--V */
|
|
#define NV_PBUS_PCI_NV_3_HEADER_TYPE 23:16 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_3_HEADER_TYPE_SINGLEFUNC 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_3_HEADER_TYPE_MULTIFUNC 0x00000080 /* ----V */
|
|
#define NV_PBUS_PCI_NV_4 0x00001810 /* RW-4R */
|
|
#define NV_PBUS_PCI_NV_4__ALIAS_1 NV_CONFIG_PCI_NV_4 /* */
|
|
#define NV_PBUS_PCI_NV_4_SPACE_TYPE 0:0 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_4_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_4_SPACE_TYPE_IO 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_4_ADDRESS_TYPE 2:1 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_4_ADDRESS_TYPE_32_BIT 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_4_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_4_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
|
|
#define NV_PBUS_PCI_NV_4_PREFETCHABLE 3:3 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_4_PREFETCHABLE_NOT 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_4_PREFETCHABLE_MERGABLE 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_4_BASE_ADDRESS 31:24 /* RWXUF */
|
|
#define NV_PBUS_PCI_NV_5 0x00001814 /* RW-4R */
|
|
#define NV_PBUS_PCI_NV_5__ALIAS_1 NV_CONFIG_PCI_NV_5 /* */
|
|
#define NV_PBUS_PCI_NV_5_SPACE_TYPE 0:0 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_5_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_5_SPACE_TYPE_IO 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_5_ADDRESS_TYPE 2:1 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_5_ADDRESS_TYPE_32_BIT 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_5_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
|
|
#define NV_PBUS_PCI_NV_5_PREFETCHABLE 3:3 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_5_PREFETCHABLE_NOT 0x00000000 /* ----V */
|
|
#define NV_PBUS_PCI_NV_5_PREFETCHABLE_MERGABLE 0x00000001 /* C---V */
|
|
#define NV_PBUS_PCI_NV_5_BASE_ADDRESS 31:24 /* RWXUF */
|
|
#define NV_PBUS_PCI_NV_6 0x00001818 /* RW-4R */
|
|
#define NV_PBUS_PCI_NV_6__ALIAS_1 NV_CONFIG_PCI_NV_6 /* */
|
|
#define NV_PBUS_PCI_NV_6_SPACE_TYPE 0:0 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_6_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
|
|
#define NV_PBUS_PCI_NV_6_SPACE_TYPE_IO 0x00000001 /* ----V */
|
|
#define NV_PBUS_PCI_NV_6_ADDRESS_TYPE 2:1 /* C--VF */
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#define NV_PBUS_PCI_NV_6_ADDRESS_TYPE_32_BIT 0x00000000 /* C---V */
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#define NV_PBUS_PCI_NV_6_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */
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#define NV_PBUS_PCI_NV_6_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
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#define NV_PBUS_PCI_NV_6_PREFETCHABLE 3:3 /* C--VF */
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#define NV_PBUS_PCI_NV_6_PREFETCHABLE_NOT 0x00000000 /* ----V */
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|
#define NV_PBUS_PCI_NV_6_PREFETCHABLE_MERGABLE 0x00000001 /* C---V */
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#define NV_PBUS_PCI_NV_6_BASE_ADDRESS 31:19 /* RWXUF */
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#define NV_PBUS_PCI_NV_7(i) (0x0000181C+(i)*4) /* R--4A */
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#define NV_PBUS_PCI_NV_7__SIZE_1 4 /* */
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#define NV_PBUS_PCI_NV_7__ALIAS_1 NV_CONFIG_PCI_NV_7 /* */
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#define NV_PBUS_PCI_NV_7_RESERVED 31:0 /* C--VF */
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#define NV_PBUS_PCI_NV_7_RESERVED_0 0x00000000 /* C---V */
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#define NV_PBUS_PCI_NV_11 0x0000182C /* R--4R */
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#define NV_PBUS_PCI_NV_11__ALIAS_1 NV_CONFIG_PCI_NV_11 /* */
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#define NV_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID 15:0 /* R--UF */
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#define NV_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R---V */
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#define NV_PBUS_PCI_NV_11_SUBSYSTEM_ID 31:16 /* R--UF */
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#define NV_PBUS_PCI_NV_11_SUBSYSTEM_ID_NONE 0x00000000 /* R---V */
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#define NV_PBUS_PCI_NV_12 0x00001830 /* RW-4R */
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#define NV_PBUS_PCI_NV_12__ALIAS_1 NV_CONFIG_PCI_NV_12 /* */
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#define NV_PBUS_PCI_NV_12_ROM_DECODE 0:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_12_ROM_DECODE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_12_ROM_DECODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_PCI_NV_12_ROM_BASE 31:16 /* RWXUF */
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#define NV_PBUS_PCI_NV_13 0x00001834 /* RW-4R */
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#define NV_PBUS_PCI_NV_13__ALIAS_1 NV_CONFIG_PCI_NV_13 /* */
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#define NV_PBUS_PCI_NV_13_CAP_PTR 7:0 /* C--VF */
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#define NV_PBUS_PCI_NV_13_CAP_PTR_AGP 0x00000044 /* ----V */
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#define NV_PBUS_PCI_NV_13_CAP_PTR_POWER_MGMT 0x00000060 /* C---V */
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#define NV_PBUS_PCI_NV_14 0x00001838 /* R--4R */
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#define NV_PBUS_PCI_NV_14__ALIAS_1 NV_CONFIG_PCI_NV_14 /* */
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#define NV_PBUS_PCI_NV_14_RESERVED 31:0 /* C--VF */
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#define NV_PBUS_PCI_NV_14_RESERVED_0 0x00000000 /* C---V */
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#define NV_PBUS_PCI_NV_15 0x0000183C /* RW-4R */
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#define NV_PBUS_PCI_NV_15__ALIAS_1 NV_CONFIG_PCI_NV_15 /* */
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#define NV_PBUS_PCI_NV_15_INTR_LINE 7:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_15_INTR_LINE_IRQ0 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_15_INTR_LINE_IRQ1 0x00000001 /* RW--V */
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#define NV_PBUS_PCI_NV_15_INTR_LINE_IRQ15 0x0000000F /* RW--V */
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#define NV_PBUS_PCI_NV_15_INTR_LINE_UNKNOWN 0x000000FF /* RW--V */
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#define NV_PBUS_PCI_NV_15_INTR_PIN 15:8 /* C--VF */
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#define NV_PBUS_PCI_NV_15_INTR_PIN_INTA 0x00000001 /* C---V */
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#define NV_PBUS_PCI_NV_15_MIN_GNT 23:16 /* C--VF */
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#define NV_PBUS_PCI_NV_15_MIN_GNT_NO_REQUIREMENTS 0x00000000 /* ----V */
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#define NV_PBUS_PCI_NV_15_MIN_GNT_750NS 0x00000003 /* ----V */
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#define NV_PBUS_PCI_NV_15_MIN_GNT_1250NS 0x00000005 /* C---V */
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#define NV_PBUS_PCI_NV_15_MAX_LAT 31:24 /* C--VF */
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#define NV_PBUS_PCI_NV_15_MAX_LAT_NO_REQUIREMENTS 0x00000000 /* ----V */
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#define NV_PBUS_PCI_NV_15_MAX_LAT_250NS 0x00000001 /* C---V */
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#define NV_PBUS_PCI_NV_16 0x00001840 /* RW-4R */
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#define NV_PBUS_PCI_NV_16__ALIAS_1 NV_CONFIG_PCI_NV_16 /* */
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#define NV_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID 15:0 /* RW-VF */
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#define NV_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R---V */
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#define NV_PBUS_PCI_NV_16_SUBSYSTEM_ID 31:16 /* RW-VF */
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#define NV_PBUS_PCI_NV_16_SUBSYSTEM_ID_NONE 0x00000000 /* R---V */
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#define NV_PBUS_PCI_NV_17 0x00001844 /* RW-4R */
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#define NV_PBUS_PCI_NV_17__ALIAS_1 NV_CONFIG_PCI_NV_17 /* */
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#define NV_PBUS_PCI_NV_17_AGP_REV_MAJOR 23:20 /* C--VF */
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#define NV_PBUS_PCI_NV_17_AGP_REV_MAJOR_1 0x00000002 /* C---V */
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|
#define NV_PBUS_PCI_NV_17_AGP_REV_MINOR 19:16 /* C--VF */
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|
#define NV_PBUS_PCI_NV_17_AGP_REV_MINOR_0 0x00000000 /* C---V */
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#define NV_PBUS_PCI_NV_17_NEXT_PTR 15:8 /* C--VF */
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#define NV_PBUS_PCI_NV_17_NEXT_PTR_NULL 0x00000000 /* C---V */
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#define NV_PBUS_PCI_NV_17_CAP_ID 7:0 /* C--VF */
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#define NV_PBUS_PCI_NV_17_CAP_ID_AGP 0x00000002 /* C---V */
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#define NV_PBUS_PCI_NV_18 0x00001848 /* RW-4R */
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|
#define NV_PBUS_PCI_NV_18__ALIAS_1 NV_CONFIG_PCI_NV_18 /* */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RQ 31:24 /* C--VF */
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#define NV_PBUS_PCI_NV_18_AGP_STATUS_RQ_32 0x0000001F /* C---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_SBA 9:9 /* R--VF */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_SBA_NONE 0x00000000 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_SBA_CAPABLE 0x00000001 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_FW 4:4 /* R--VF */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_FW_NONE 0x00000000 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_FW_CAPABLE 0x00000001 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RATE 2:0 /* R--VF */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X 0x00000001 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RATE_2X 0x00000002 /* ----V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X_AND_2X 0x00000003 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RATE_4X 0x00000004 /* R---V */
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|
#define NV_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X_2X_4X 0x00000007 /* R---V */
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#define NV_PBUS_PCI_NV_19 0x0000184C /* RW-4R */
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|
#define NV_PBUS_PCI_NV_19__ALIAS_1 NV_CONFIG_PCI_NV_19 /* */
|
|
#define NV_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH 28:24 /* RWIVF */
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|
#define NV_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH_0 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE 9:9 /* RWIVF */
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|
#define NV_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_ON 0x00000001 /* RW--V */
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|
#define NV_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE 8:8 /* RWIVF */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_ON 0x00000001 /* RW--V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_FW_ENABLE 4:4 /* RWIVF */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_FW_ENABLE_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_FW_ENABLE_ON 0x00000001 /* RW--V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE 2:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_OFF 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_1X 0x00000001 /* RW--V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_2X 0x00000002 /* RW--V */
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#define NV_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_4X 0x00000004 /* RW--V */
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#define NV_PBUS_PCI_NV_20 0x00001850 /* RW-4R */
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#define NV_PBUS_PCI_NV_20__ALIAS_1 NV_CONFIG_PCI_NV_20 /* */
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#define NV_PBUS_PCI_NV_20_ROM_SHADOW 0:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED 0x00000000 /* RWI-V */
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#define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x00000001 /* RW--V */
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#define NV_PBUS_PCI_NV_21 0x00001854 /* RW-4R */
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#define NV_PBUS_PCI_NV_21__ALIAS_1 NV_CONFIG_PCI_NV_21 /* */
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#define NV_PBUS_PCI_NV_21_VGA 0:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_21_VGA_DISABLED 0x00000000 /* RW--V */
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#define NV_PBUS_PCI_NV_21_VGA_ENABLED 0x00000001 /* RWI-V */
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#define NV_PBUS_PCI_NV_22 0x00001858 /* RW-4R */
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#define NV_PBUS_PCI_NV_22__ALIAS_1 NV_CONFIG_PCI_NV_22 /* */
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#define NV_PBUS_PCI_NV_22_SCRATCH 23:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_22_SCRATCH_DEFAULT 0x0023D6CE /* RWI-V */
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#define NV_PBUS_PCI_NV_23 0x0000185C /* RW-4R */
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#define NV_PBUS_PCI_NV_23__ALIAS_1 NV_CONFIG_PCI_NV_23 /* */
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#define NV_PBUS_PCI_NV_23_DT_TIMEOUT 3:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_23_DT_TIMEOUT_16 0x0000000F /* RWI-V */
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#define NV_PBUS_PCI_NV_24 0x00001860 /* RW-4R */
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#define NV_PBUS_PCI_NV_24__ALIAS_1 NV_CONFIG_PCI_NV_24 /* */
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#define NV_PBUS_PCI_NV_24_PME_D3_COLD 31:31 /* C--VF */
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#define NV_PBUS_PCI_NV_24_PME_D3_COLD_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_PME_D3_COLD_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_PME_D3_HOT 30:30 /* C--VF */
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#define NV_PBUS_PCI_NV_24_PME_D3_HOT_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_PME_D3_HOT_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_PME_D2 29:29 /* C--VF */
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#define NV_PBUS_PCI_NV_24_PME_D2_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_PME_D2_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_PME_D1 28:28 /* C--VF */
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#define NV_PBUS_PCI_NV_24_PME_D1_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_PME_D1_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_PME_D0 27:27 /* C--VF */
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#define NV_PBUS_PCI_NV_24_PME_D0_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_PME_D0_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_D2 26:26 /* C--VF */
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#define NV_PBUS_PCI_NV_24_D2_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_D2_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_D1 25:25 /* C--VF */
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#define NV_PBUS_PCI_NV_24_D1_SUPPORTED 0x00000001 /* ---VV */
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#define NV_PBUS_PCI_NV_24_D1_NOT_SUPPORTED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_DSI 21:21 /* C--VF */
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#define NV_PBUS_PCI_NV_24_DSI_NOT_REQUIRED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_PME_CLOCK 19:19 /* C--VF */
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#define NV_PBUS_PCI_NV_24_PME_CLOCK_NOT_REQUIRED 0x00000000 /* C--VV */
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#define NV_PBUS_PCI_NV_24_VERSION 18:16 /* C--VF */
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|
#define NV_PBUS_PCI_NV_24_VERSION_1 0x00000001 /* ---VV */
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|
#define NV_PBUS_PCI_NV_24_VERSION_2 0x00000002 /* C--VV */
|
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#define NV_PBUS_PCI_NV_24_NEXT_PTR 15:8 /* R--VF */
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#define NV_PBUS_PCI_NV_24_NEXT_PTR_NULL 0x00000000 /* ----V */
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#define NV_PBUS_PCI_NV_24_NEXT_PTR_AGP 0x00000044 /* ----V */
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#define NV_PBUS_PCI_NV_24_CAP_ID 7:0 /* C--VF */
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#define NV_PBUS_PCI_NV_24_CAP_ID_POWER_MGMT 0x00000001 /* C---V */
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#define NV_PBUS_PCI_NV_25 0x00001864 /* RW-4R */
|
|
#define NV_PBUS_PCI_NV_25__ALIAS_1 NV_CONFIG_PCI_NV_25 /* */
|
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#define NV_PBUS_PCI_NV_25_POWER_STATE 1:0 /* RWIVF */
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#define NV_PBUS_PCI_NV_25_POWER_STATE_D3_HOT 0x00000003 /* RW-VV */
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#define NV_PBUS_PCI_NV_25_POWER_STATE_D0 0x00000000 /* RWIVV */
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#define NV_PBUS_PCI_NV_26(i) (0x00001868+(i)*4) /* R--4A */
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#define NV_PBUS_PCI_NV_26__SIZE_1 38 /* */
|
|
#define NV_PBUS_PCI_NV_26__ALIAS_1 NV_CONFIG_PCI_NV_25 /* */
|
|
#define NV_PBUS_PCI_NV_26_RESERVED 31:0 /* C--VF */
|
|
#define NV_PBUS_PCI_NV_26_RESERVED_0 0x00000000 /* C---V */
|
|
/* dev_fifo.ref */
|
|
#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */
|
|
#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */
|
|
#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */
|
|
#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */
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|
#define NV_PFIFO_DELAY_1 0x00002054 /* RW-4R */
|
|
#define NV_PFIFO_DELAY_1_ACQUIRE_WAIT 9:0 /* RWIUF */
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|
#define NV_PFIFO_DELAY_1_ACQUIRE_WAIT_2 0x00000002 /* RWI-V */
|
|
#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */
|
|
#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */
|
|
#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */
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|
#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */
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|
#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */
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|
#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */
|
|
#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */
|
|
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */
|
|
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */
|
|
#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */
|
|
#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */
|
|
#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */
|
|
#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */
|
|
#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */
|
|
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */
|
|
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */
|
|
#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */
|
|
#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */
|
|
#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */
|
|
#define NV_PFIFO_NEXT_CHANNEL_CHID 4:0 /* RWXUF */
|
|
#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */
|
|
#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */
|
|
#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */
|
|
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */
|
|
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */
|
|
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */
|
|
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */
|
|
#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */
|
|
#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */
|
|
#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */
|
|
#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */
|
|
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */
|
|
#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */
|
|
#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */
|
|
#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */
|
|
#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */
|
|
#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */
|
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#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */
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#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */
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#define NV_PFIFO_INTR_0_SEMAPHORE 20:20 /* RWXVF */
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#define NV_PFIFO_INTR_0_SEMAPHORE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PFIFO_INTR_0_SEMAPHORE_PENDING 0x00000001 /* R---V */
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#define NV_PFIFO_INTR_0_SEMAPHORE_RESET 0x00000001 /* -W--V */
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#define NV_PFIFO_INTR_0_ACQUIRE_TIMEOUT 24:24 /* RWXVF */
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#define NV_PFIFO_INTR_0_ACQUIRE_TIMEOUT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PFIFO_INTR_0_ACQUIRE_TIMEOUT_PENDING 0x00000001 /* R---V */
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#define NV_PFIFO_INTR_0_ACQUIRE_TIMEOUT_RESET 0x00000001 /* -W--V */
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#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */
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#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_INTR_EN_0_SEMAPHORE 20:20 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_SEMAPHORE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_SEMAPHORE_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_INTR_EN_0_ACQUIRE_TIMEOUT 24:24 /* RWIVF */
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#define NV_PFIFO_INTR_EN_0_ACQUIRE_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_INTR_EN_0_ACQUIRE_TIMEOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */
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#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */
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#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */
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#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */
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#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */
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#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */
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#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */
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#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */
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#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */
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#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */
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#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */
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#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */
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#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */
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#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */
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#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:2 /* RWIUF */
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#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000044 /* RWI-V */
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#define NV_PFIFO_RAMFC_SIZE 16:16 /* RWIVF */
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#define NV_PFIFO_RAMFC_SIZE_1K 0x00000000 /* RWI-V */
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#define NV_PFIFO_RAMFC_SIZE_2K 0x00000001 /* RW--V */
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#define NV_PFIFO_RAMFC_BASE_ADDRESS2 23:17 /* RWIUF */
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#define NV_PFIFO_RAMFC_BASE_ADDRESS_11400 0x00000045 /* RWI-V */
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#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */
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#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */
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#define NV_PFIFO_RAMRO_BASE_ADDRESS_11500 0x0000008B /* RWI-V */
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#define NV_PFIFO_RAMRO_BASE_ADDRESS_11400 0x0000008A /* RW--V */
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#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RW--V */
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#define NV_PFIFO_RAMRO_BASE_ADDRESS_11800 0x0000008C /* RW--V */
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#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */
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#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */
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#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */
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#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */
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#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */
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#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */
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#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */
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#define NV_PFIFO_MODE 0x00002504 /* RW-4R */
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#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_16 16:16 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_16_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_16_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_17 17:17 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_17_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_17_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_18 18:18 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_18_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_18_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_19 19:19 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_19_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_19_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_20 20:20 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_20_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_20_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_21 21:21 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_21_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_21_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_22 22:22 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_22_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_22_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_23 23:23 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_23_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_23_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_24 24:24 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_24_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_24_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_25 25:25 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_25_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_25_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_26 26:26 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_26_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_26_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_27 27:27 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_27_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_27_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_28 28:28 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_28_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_28_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_29 29:29 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_29_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_29_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_30 30:30 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_30_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_30_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_MODE_CHANNEL_31 31:31 /* RWIVF */
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#define NV_PFIFO_MODE_CHANNEL_31_PIO 0x00000000 /* RWI-V */
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#define NV_PFIFO_MODE_CHANNEL_31_DMA 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA 0x00002508 /* RW-4R */
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#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_16 16:16 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_16_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_16_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_17 17:17 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_17_NOT_PENDING 0x00000000 /* RWI-V */
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#define NV_PFIFO_DMA_CHANNEL_17_PENDING 0x00000001 /* RW--V */
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#define NV_PFIFO_DMA_CHANNEL_18 18:18 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_18_NOT_PENDING 0x00000000 /* RWI-V */
|
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#define NV_PFIFO_DMA_CHANNEL_18_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_19 19:19 /* RWIVF */
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#define NV_PFIFO_DMA_CHANNEL_19_NOT_PENDING 0x00000000 /* RWI-V */
|
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#define NV_PFIFO_DMA_CHANNEL_19_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_20 20:20 /* RWIVF */
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|
#define NV_PFIFO_DMA_CHANNEL_20_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_20_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_21 21:21 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_21_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_21_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_22 22:22 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_22_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_22_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_23 23:23 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_23_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_23_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_24 24:24 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_24_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_24_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_25 25:25 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_25_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_25_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_26 26:26 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_26_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_26_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_27 27:27 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_27_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_27_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_28 28:28 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_28_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_28_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_29 29:29 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_29_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_29_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_30 30:30 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_30_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_30_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_DMA_CHANNEL_31 31:31 /* RWIVF */
|
|
#define NV_PFIFO_DMA_CHANNEL_31_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_DMA_CHANNEL_31_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */
|
|
#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_16 16:16 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_16_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_16_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_17 17:17 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_17_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_17_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_18 18:18 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_18_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_18_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_19 19:19 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_19_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_19_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_20 20:20 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_20_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_20_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_21 21:21 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_21_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_21_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_22 22:22 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_22_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_22_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_23 23:23 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_23_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_23_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_24 24:24 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_24_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_24_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_25 25:25 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_25_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_25_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_26 26:26 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_26_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_26_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_27 27:27 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_27_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_27_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_28 28:28 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_28_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_28_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_29 29:29 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_29_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_29_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_30 30:30 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_30_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_30_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_31 31:31 /* RWIVF */
|
|
#define NV_PFIFO_SIZE_CHANNEL_31_124_BYTES 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_SIZE_CHANNEL_31_512_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */
|
|
#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */
|
|
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */
|
|
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */
|
|
#define NV_PFIFO_CACHE0_PUSH1_CHID 4:0 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_PUSH1_CHID 4:0 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */
|
|
#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_ACQUIRE 16:16 /* RWIVF */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_ACQUIRE_NOT_PENDING 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUSH_ACQUIRE_PENDING 0x00000001 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 20:16 /* RWIUF */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_ENDIAN 31:31 /* RWIUF */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_LITTLE_ENDIAN 0x00000000 /* RWI-V */
|
|
#define NV_PFIFO_CACHE1_DMA_FETCH_BIG_ENDIAN 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 31:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 31:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_REF 0x00003248 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_REF_CNT 31:0 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_SUBROUTINE_RETURN_OFFSET 31:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE 0:0 /* RWXVF */
|
|
#define NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE_INACTIVE 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_SUBROUTINE_STATE_ACTIVE 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_DCOUNT_VALUE 12:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW 0x000032A4 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_GET_JMP_SHADOW_OFFSET 31:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_DMA_RSVD_SHADOW 0x000032A8 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_DMA_RSVD_SHADOW_CMD 31:0 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_DMA_DATA_SHADOW 0x000032AC /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_DATA_SHADOW_VALUE 31:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_01_INST 0x000032B0 /* RW-4R */
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#define NV_PFIFO_CACHE1_SUBCH_0_INST_VALUE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_1_INST_VALUE 31:16 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_23_INST 0x000032B4 /* RW-4R */
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#define NV_PFIFO_CACHE1_SUBCH_2_INST_VALUE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_3_INST_VALUE 31:16 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_45_INST 0x000032B8 /* RW-4R */
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#define NV_PFIFO_CACHE1_SUBCH_4_INST_VALUE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_5_INST_VALUE 31:16 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_67_INST 0x000032BC /* RW-4R */
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#define NV_PFIFO_CACHE1_SUBCH_6_INST_VALUE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_SUBCH_7_INST_VALUE 31:16 /* RWXUF */
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#define NV_PFIFO_CACHE0_SUBCH_INST 0x000032C0 /* RW-4R */
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#define NV_PFIFO_CACHE0_SUBCH_INST_VALUE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE 0:0 /* RWXUV */
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#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_INC 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_TYPE_NON_INC 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */
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#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:29 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_CALL 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RETURN 0x00000003 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000004 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000006 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_NVM 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */
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#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */
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#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 31:2 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 31:12 /* RWXUF */
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#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */
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#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */
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#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */
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#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
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#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */
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#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */
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#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */
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#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */
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#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */
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#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */
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#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */
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#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */
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#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */
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#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */
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#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_ACQUIRE_STATE 16:16 /* R-XVF */
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#define NV_PFIFO_CACHE1_PULL0_ACQUIRE_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_ACQUIRE_STATE_BUSY 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_SEMAPHORE 21:20 /* R-XVF */
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#define NV_PFIFO_CACHE1_PULL0_SEMAPHORE_NO_ERROR 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_SEMAPHORE_BAD_ARG 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_PULL0_SEMAPHORE_INV_STATE 0x00000002 /* R---V */
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#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */
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#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */
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#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */
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#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_ACQUIRE 4:4 /* RWXVF */
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#define NV_PFIFO_CACHE1_PULL1_ACQUIRE_INACTIVE 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_ACQUIRE_ACTIVE 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_SEM_TARGET_NODE 17:16 /* RWXUF */
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#define NV_PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_NVM 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_PCI 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE1_PULL1_SEM_TARGET_NODE_AGP 0x00000003 /* RW--V */
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#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */
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#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */
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#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */
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#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */
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#define NV_PFIFO_CACHE1_ACQUIRE_0 0x00003260 /* RW-4R */
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#define NV_PFIFO_CACHE1_ACQUIRE_0_TIMEOUT 30:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_ACQUIRE_1 0x00003264 /* RW-4R */
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#define NV_PFIFO_CACHE1_ACQUIRE_1_TIMESTAMP 31:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_ACQUIRE_2 0x00003268 /* RW-4R */
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#define NV_PFIFO_CACHE1_ACQUIRE_2_VALUE 31:0 /* RWXUF */
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#define NV_PFIFO_CACHE1_SEMAPHORE 0x0000326C /* RW-4R */
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#define NV_PFIFO_CACHE1_SEMAPHORE_CTXDMA 0:0 /* RWXVF */
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#define NV_PFIFO_CACHE1_SEMAPHORE_CTXDMA_INVALID 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE1_SEMAPHORE_CTXDMA_VALID 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE1_SEMAPHORE_OFFSET 11:2 /* RWXUF */
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#define NV_PFIFO_CACHE1_SEMAPHORE_PAGE_ADDRESS 31:12 /* RWXUF */
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#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */
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#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */
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#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */
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#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */
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#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */
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#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */
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#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */
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#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */
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#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */
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#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */
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#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */
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#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */
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#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */
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#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */
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#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */
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#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */
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#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */
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#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */
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#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */
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#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */
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#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */
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#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */
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#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */
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#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */
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#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */
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#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */
|
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#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */
|
|
#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */
|
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#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */
|
|
#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */
|
|
#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */
|
|
#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */
|
|
#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */
|
|
#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */
|
|
#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */
|
|
#define NV_PFIFO_CACHE1_METHOD_TYPE 0:0 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */
|
|
#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */
|
|
#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */
|
|
#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */
|
|
#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */
|
|
#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */
|
|
#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */
|
|
#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */
|
|
#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */
|
|
#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */
|
|
#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */
|
|
#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */
|
|
#define NV_PFIFO_DEVICE__SIZE_1 128 /* */
|
|
#define NV_PFIFO_DEVICE_CHID 4:0 /* R--UF */
|
|
#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */
|
|
#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */
|
|
#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */
|
|
#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */
|
|
#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */
|
|
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */
|
|
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */
|
|
#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */
|
|
#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */
|
|
#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */
|
|
#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */
|
|
#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */
|
|
#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */
|
|
/* dev_tremapper.ref */
|
|
#define NV_UREMAP 0x00FFFFFF:0x00C00000 /* RW--D */
|
|
#define NV_UREMAP_FORMAT(i) ((i)*0x10000 + 0x00C00000) /* RW-4R */
|
|
#define NV_UREMAP_FORMAT__SIZE 2 /* */
|
|
#define NV_UREMAP_FORMAT_BPP 3:0 /* RWIVF */
|
|
#define NV_UREMAP_FORMAT_BPP_8 0x00000000 /* RWI-V */
|
|
#define NV_UREMAP_FORMAT_BPP_16 0x00000001 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_BPP_32 0x00000002 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_BPP_64 0x00000003 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_BPP_128 0x00000004 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH 7:4 /* RWIVF */
|
|
#define NV_UREMAP_FORMAT_WIDTH_1 0x00000000 /* RWI-V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_2 0x00000001 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_4 0x00000002 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_8 0x00000003 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_16 0x00000004 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_32 0x00000005 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_64 0x00000006 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_128 0x00000007 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_WIDTH_256 0x00000008 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT 11:8 /* RWIVF */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_1 0x00000000 /* RWI-V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_2 0x00000001 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_4 0x00000002 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_8 0x00000003 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_16 0x00000004 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_32 0x00000005 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_64 0x00000006 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_128 0x00000007 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_HEIGHT_256 0x00000008 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH 15:12 /* RWIVF */
|
|
#define NV_UREMAP_FORMAT_DEPTH_1 0x00000000 /* RWI-V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_2 0x00000001 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_4 0x00000002 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_8 0x00000003 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_16 0x00000004 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_32 0x00000005 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_64 0x00000006 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_128 0x00000007 /* RW--V */
|
|
#define NV_UREMAP_FORMAT_DEPTH_256 0x00000008 /* RW--V */
|
|
#define NV_UREMAP_OFFSET(i) ((i)*0x10000 + 0x00C00004) /* RW-4R */
|
|
#define NV_UREMAP_OFFSET__SIZE 2 /* */
|
|
#define NV_UREMAP_OFFSET_ADR 32:0 /* RWIVF */
|
|
#define NV_UREMAP_OFFSET_ADR_0 0x00000000 /* RWI-V */
|
|
/* dev_tremapper.ref */
|
|
#define NV_PREMAP 0x006E1FFF:0x006E0000 /* RW--D */
|
|
#define NV_PREMAP_BASE(i) ((i)*0x10 + 0x006e0000) /* RW-4R */
|
|
#define NV_PREMAP_BASE__SIZE 2 /* */
|
|
#define NV_PREMAP_ENDIAN 0:0 /* RWIVF */
|
|
#define NV_PREMAP_ENDIAN_LE 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_ENDIAN_BE 0x00000001 /* RWI-V */
|
|
#define NV_PREMAP_BASE_ADR 28:6 /* RWIVF */
|
|
#define NV_PREMAP_BASE_ADR_0 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_LIMIT(i) ((i)*0x10 + 0x006e0004) /* RW-4R */
|
|
#define NV_PREMAP_LIMIT__SIZE 2 /* */
|
|
#define NV_PREMAP_LIMIT_ADR 28:6 /* RWIVF */
|
|
#define NV_PREMAP_LIMIT_ADR_0 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_CONTROL 0x006e0100 /* RW-4R */
|
|
#define NV_PREMAP_CONTROL_ALLOC_STATUS 1:0 /* RW-VF */
|
|
#define NV_PREMAP_CONTROL_NOT_ALLOCATED 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_CONTROL_ALLOCATE_CTX0 0x00000001 /* RW--V */
|
|
#define NV_PREMAP_CONTROL_ALLOCATE_CTX1 0x00000002 /* RW--V */
|
|
#define NV_PREMAP_CONTROL_DIRTY 31:31 /* -W-VF */
|
|
#define NV_PREMAP_CONTROL_DIRTY_RESET 0x00000000 /* -W--V */
|
|
#define NV_PREMAP_CONTROL_DIRTY_SET 0x00000001 /* -W--V */
|
|
#define NV_PREMAP_INTR 0x006e0300 /* RW-4R */
|
|
#define NV_PREMAP_INTR_FORMAT_ERROR 0:0 /* RWXVF */
|
|
#define NV_PREMAP_INTR_FORMAT_ERROR_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PREMAP_INTR_FORMAT_ERROR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PREMAP_INTR_FORMAT_ERROR_RESET 0x00000001 /* -W--V */
|
|
#define NV_PREMAP_INTR_EN_0 0x006e0304 /* RW-4R */
|
|
#define NV_PREMAP_INTR_EN_0_FORMAT_ERROR 0:0 /* RWIVF */
|
|
#define NV_PREMAP_INTR_EN_0_FORMAT_ERROR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_INTR_EN_0_FORMAT_ERROR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PREMAP_BUFFER(i) ((i)*4 + 0x00000800)) /* RW-4R */
|
|
#define NV_PREMAP_BUFFER__SIZE 512 /* */
|
|
#define NV_PREMAP_BUFFER_BYTE0 8:0 /* RW--V */
|
|
#define NV_PREMAP_BUFFER_BYTE1 24:16 /* RW--V */
|
|
#define NV_PREMAP_PFORMAT(i) ((i)*0x10 + 0x006e0200)) /* RW-4R */
|
|
#define NV_PREMAP_PFORMAT__SIZE 2 /* */
|
|
#define NV_PREMAP_PFORMAT_ADR 15:0 /* RWIVF */
|
|
#define NV_PREMAP_PFORMAT_ADR_0 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_POFFSET(i) ((i)*0x10 + 0x006e0204)) /* RW-4R */
|
|
#define NV_PREMAP_POFFSET__SIZE 2 /* */
|
|
#define NV_PREMAP_POFFSET_ADR 31:0 /* RWIVF */
|
|
#define NV_PREMAP_POFFSET_ADR_0 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_DBG_CONTROL 0x006e0400 /* RW-4R */
|
|
#define NV_PREMAP_DBG_CONTROL_FLUSH 0:0 /* -W-VF */
|
|
#define NV_PREMAP_DBG_CONTROL_FLUSH_REMAP 0x00000001 /* -W--V */
|
|
#define NV_PREMAP_DBG_RAM_DIAG 4:4 /* RW-VF */
|
|
#define NV_PREMAP_DBG_RAM_DIAG_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PREMAP_DBG_RAM_DIAG_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PREMAP_DBG_CONTEXT 8:8 /* R---F */
|
|
#define NV_PREMAP_DBG_CONTEXT_0 0x00000000 /* R-I-V */
|
|
#define NV_PREMAP_DBG_CONTEXT_1 0x00000001 /* R---V */
|
|
#define NV_PREMAP_DBG_DIRTY_STATE 12:12 /* R---F */
|
|
#define NV_PREMAP_DBG_NOT_DIRTY 0x00000000 /* R-I-V */
|
|
#define NV_PREMAP_DBG_DIRTY 0x00000001 /* R---V */
|
|
/* dev_tremapper.ref */
|
|
#define NV_BREMAP_BUFFER32(i,j) (i*0x10000) + (j*4) /* RW-4A */
|
|
#define NV_BREMAP_BUFFER32__SIZE_1 2 /* */
|
|
#define NV_BREMAP_BUFFER32__SIZE_2 128 /* */
|
|
#define NV_BREMAP_BUFFER32_VALUE 31:0 /* RW--V */
|
|
#define NV_BREMAP_BUFFER16(i,j) ((i*0x10000)+(j/2)+(j%2)) /* RW-2A */
|
|
#define NV_BREMAP_BUFFER16__SIZE_1 2 /* */
|
|
#define NV_BREMAP_BUFFER16__SIZE_2 256 /* */
|
|
#define NV_BREMAP_BUFFER16_VALUE 15:0 /* RW--V */
|
|
#define NV_BREMAP_BUFFER8(i,j) ((i*0x10000) + j + 0x00000000) /* RW-1A */
|
|
#define NV_BREMAP_BUFFER8__SIZE_1 2 /* */
|
|
#define NV_BREMAP_BUFFER8_SIZE_2 512 /* */
|
|
#define NV_BREMAP_BUFFER8_VALUE 7:0 /* RW--V */
|
|
/* dev_host_diag.ref */
|
|
#define NV_HOST_DIAG 0x00005FFF:0x00005000 /* RW--D */
|
|
#define NV_HOST_DIAG_C1SYNCM_DATA(i) (0x00005000 +(i)* 8) /* RW-4R */
|
|
#define NV_HOST_DIAG_C1SYNCM_DATA__SIZE_1 4 /* */
|
|
#define NV_HOST_DIAG_C1SYNCM_DATA_VALUE 13:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_C1SYNCD_DATA(i) (0x00005004 +(i)* 8) /* RW-4R */
|
|
#define NV_HOST_DIAG_C1SYNCD_DATA__SIZE_1 4 /* */
|
|
#define NV_HOST_DIAG_C1SYNCD_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQA_DATA(i) (0x00005400 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQA_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQA_DATA_VALUE 28:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD0L_DATA(i) (0x00005408 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD0L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD0L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD1L_DATA(i) (0x00005410 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD1L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD1L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD2L_DATA(i) (0x00005418 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD2L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD2L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD3L_DATA(i) (0x00005420 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD3L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD3L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD0H_DATA(i) (0x0000540c +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD0H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD0H_DATA_VALUE 3:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD1H_DATA(i) (0x00005414 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD1H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD1H_DATA_VALUE 3:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD2H_DATA(i) (0x0000541c +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD2H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD2H_DATA_VALUE 3:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CPUQD3H_DATA(i) (0x00005424 +(i)* 64) /* RW-4R */
|
|
#define NV_HOST_DIAG_CPUQD3H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_CPUQD3H_DATA_VALUE 3:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_AQL_DATA(i) (0x00005100 +(i)* 8) /* RW-4R */
|
|
#define NV_HOST_DIAG_AQL_DATA__SIZE_1 4 /* */
|
|
#define NV_HOST_DIAG_AQL_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_AQH_DATA(i) (0x00005104 +(i)* 8) /* RW-4R */
|
|
#define NV_HOST_DIAG_AQH_DATA__SIZE_1 4 /* */
|
|
#define NV_HOST_DIAG_AQH_DATA_VALUE 19:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_WDQL_DATA(i) (0x00005200 +(i)* 8) /* RW-4R */
|
|
#define NV_HOST_DIAG_WDQL_DATA__SIZE_1 8 /* */
|
|
#define NV_HOST_DIAG_WDQL_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_WDQH_DATA(i) (0x00005204 +(i)* 8) /* RW-4R */
|
|
#define NV_HOST_DIAG_WDQH_DATA__SIZE_1 8 /* */
|
|
#define NV_HOST_DIAG_WDQH_DATA_VALUE 3:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_DSPQ_DATA(i) (0x00005300 +(i)* 4) /* RW-4R */
|
|
#define NV_HOST_DIAG_DSPQ_DATA__SIZE_1 32 /* */
|
|
#define NV_HOST_DIAG_DSPQ_DATA_VALUE 18:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_RDQ0_DATA(i) (0x00005800 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_RDQ0_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_RDQ0_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_RDQ1L_DATA(i) (0x00005804 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_RDQ1L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_RDQ1L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_RDQ1H_DATA(i) (0x00005808 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_RDQ1H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_RDQ1H_DATA_VALUE 15:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_RDQ2_DATA(i) (0x00005810 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_RDQ2_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_RDQ2_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_RDQ3L_DATA(i) (0x00005814 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_RDQ3L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_RDQ3L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_RDQ3H_DATA(i) (0x00005818 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_RDQ3H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_RDQ3H_DATA_VALUE 15:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_CTL 0x00005F00 /* RW-4R */
|
|
#define NV_HOST_DIAG_RAM_RDWR 0:0 /* RWIUF */
|
|
#define NV_HOST_DIAG_RAM_RDWR_OFF 0x0 /* RWI-V */
|
|
#define NV_HOST_DIAG_RAM_RDWR_ON 0x1 /* RW--V */
|
|
#define NV_HOST_DIAG_RP1_SEL 1:1 /* RWIUF */
|
|
#define NV_HOST_DIAG_RP1_OFF 0x0 /* RWI-V */
|
|
#define NV_HOST_DIAG_RP1_ON 0x1 /* RW--V */
|
|
#define NV_HOST_DIAG_FWB0L_DATA(i) (0x00005A00 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB0L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB0L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB1L_DATA(i) (0x00005A08 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB1L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB1L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB2L_DATA(i) (0x00005A10 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB2L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB2L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB3L_DATA(i) (0x00005A18 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB3L_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB3L_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB0H_DATA(i) (0x00005A04 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB0H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB0H_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB1H_DATA(i) (0x00005A0c +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB1H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB1H_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB2H_DATA(i) (0x00005A14 +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB2H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB2H_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWB3H_DATA(i) (0x00005A1c +(i)* 32) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWB3H_DATA__SIZE_1 16 /* */
|
|
#define NV_HOST_DIAG_FWB3H_DATA_VALUE 31:0 /* RWXUF */
|
|
#define NV_HOST_DIAG_FWAQ_DATA(i) (0x00005c00 +(i)* 4) /* RW-4R */
|
|
#define NV_HOST_DIAG_FWAQ_DATA__SIZE_1 4 /* */
|
|
#define NV_HOST_DIAG_FWAQ_DATA_VALUE 28:0 /* RWXUF */
|
|
/* dev_graphics_generated.ref */
|
|
#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */
|
|
#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */
|
|
#define NV_PGRAPH_DEBUG_0_STATE 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_0_STATE_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_0_STATE_RESET 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_0_FE_2D_STATE 1:1 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_0_FE_2D_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_FE_2D_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_FE_3D_STATE 2:2 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_FE_3D_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_FE_3D_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_CACHE_STATE 3:3 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_CACHE_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_CACHE_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_PREROP_STATE 4:4 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_PREROP_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_PREROP_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_ROP_STATE 5:5 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_ROP_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_ROP_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_FINE_RSTR_STATE 6:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_FINE_RSTR_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_FINE_RSTR_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_COARSE_RSTR_STATE 7:7 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_COARSE_RSTR_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_COARSE_RSTR_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_DMA_STATE 8:8 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_DMA_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_DMA_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_RSTR_2D_STATE 9:9 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_RSTR_2D_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_RSTR_2D_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_SETUP_STATE 10:10 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_SETUP_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_SETUP_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_ZCULL_STATE 11:11 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_ZCULL_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_ZCULL_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_SHD_STATE 13:13 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_SHD_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_SHD_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_SHDBE_STATE 14:14 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_SHDBE_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_SHDBE_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_XF_STATE 15:15 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_XF_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_XF_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_IDX_STATE 16:16 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_IDX_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_IDX_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_VTX_STATE 17:17 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_VTX_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_VTX_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_CAS_STATE 18:18 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_CAS_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_CAS_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_FD_STATE 19:19 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_FD_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_FD_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_CMB_STATE 20:20 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_CMB_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_CMB_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_CBUF_STATE 21:21 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_CBUF_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_CBUF_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_ZRD_STATE 22:22 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_ZRD_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_ZRD_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_ZWR_STATE 23:23 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_ZWR_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_ZWR_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_XBAR_STATE 24:24 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_XBAR_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_XBAR_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_0_CROP_STATE 25:25 /* RWIVF */
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#define NV_PGRAPH_DEBUG_0_CROP_STATE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_0_CROP_STATE_RESET 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */
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#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET 0:0 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_NOT_LAST 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VOLATILE_RESET_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_DMA_ACTIVITY 4:4 /* CWIVF */
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#define NV_PGRAPH_DEBUG_1_DMA_ACTIVITY_IGNORE 0x00000000 /* CWI-V */
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#define NV_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 0x00000001 /* -W--T */
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#define NV_PGRAPH_DEBUG_1_PM 5:5 /* CWIVF */
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#define NV_PGRAPH_DEBUG_1_PM_IGNORE 0x00000000 /* CWI-V */
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#define NV_PGRAPH_DEBUG_1_PM_TRIGGER 0x00000001 /* -W--T */
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#define NV_PGRAPH_DEBUG_1_MS_ENUMS 6:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_MS_ENUMS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_MS_ENUMS_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_MS_ENUMS_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_GL_ENUMS 7:7 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_GL_ENUMS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_GL_ENUMS_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_GL_ENUMS_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VTX_PTE 8:8 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_VTX_PTE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_VTX_PTE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VTX_PTE_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VTX_CACHE 9:9 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_VTX_CACHE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_VTX_CACHE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VTX_CACHE_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VTX_FILE 10:10 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_VTX_FILE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_VTX_FILE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_VTX_FILE_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_XF_ASYNC 12:12 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_XF_ASYNC_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_XF_ASYNC_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_LT_ASYNC 13:13 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_LT_ASYNC_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_LT_ASYNC_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_AUTO 14:14 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_AUTO_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_AUTO_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_AUTO_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_Y 15:15 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_Y_DECR 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_Y_INCR 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_DRAWDIR_Y_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_INSTANCE 16:16 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_INSTANCE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_INSTANCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_INSTANCE_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_CTX 20:20 /* RWIVF */
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#define NV_PGRAPH_DEBUG_1_CTX_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_1_CTX_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_CTX_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_1_CACHE 24:24 /* CWIVF */
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#define NV_PGRAPH_DEBUG_1_CACHE_IGNORE 0x00000000 /* CWI-V */
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#define NV_PGRAPH_DEBUG_1_CACHE_INVALIDATE 0x00000001 /* -W--T */
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#define NV_PGRAPH_DEBUG_2 0x00400880 /* RW-4R */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_2D 0:0 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_2D_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_2D_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_2D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_BLT 1:1 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_BLT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_BLT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_BLT_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_CELS 2:2 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_CELS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_CELS_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_CELS_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_3D 3:3 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_3D_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_3D_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCH_CHECK_3D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_CHECK 4:4 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_CHECK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_CHECK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_CHECK_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_CHECK 5:5 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_CHECK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_CHECK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_CHECK_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_MEMSIZE_CHECK 6:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_MEMSIZE_CHECK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_MEMSIZE_CHECK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_MEMSIZE_CHECK_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_SWIZZLE_CHECK 7:7 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_SWIZZLE_CHECK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_SWIZZLE_CHECK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_SWIZZLE_CHECK_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_TILEVIOL 8:8 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_TILEVIOL_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_TILEVIOL_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_TILEVIOL_INIT 0x00000001 /* RW0-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_ENDIAN_CHECK 9:9 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_ENDIAN_CHECK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_ENDIAN_CHECK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_ENDIAN_CHECK_INIT 0x00000001 /* RW0-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_INT 10:10 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_INT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_INT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_LIMIT_INT_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_INT 11:11 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_INT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_INT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_OVRFLW_INT_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PASS_VIOL 12:12 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_PASS_VIOL_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_2_PREROP_PASS_VIOL_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PASS_VIOL_INIT 0x00000000 /* RW0-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCHWRAP 13:13 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCHWRAP_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCHWRAP_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_PITCHWRAP_INIT 0x00000000 /* RW0-V */
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#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_3D 14:14 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_3D_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_3D_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_3D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_2D 15:15 /* RWIVF */
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#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_2D_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_2D_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_DITHER_2D_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SWALLOW_REQS 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SWALLOW_REQS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SWALLOW_REQS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SWALLOW_REQS_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SBFILTER 17:17 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SBFILTER_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SBFILTER_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SBFILTER_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FASTCLEAR 18:18 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FASTCLEAR_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FASTCLEAR_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FASTCLEAR_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FLUSH_HOLDOFF 19:19 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FLUSH_HOLDOFF_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FLUSH_HOLDOFF_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_FLUSH_HOLDOFF_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_TILEBIT_UPDATE 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_TILEBIT_UPDATE_AUTO 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_TILEBIT_UPDATE_MANUAL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_TILEBIT_UPDATE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_BLEND_OPT 21:21 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_BLEND_OPT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_BLEND_OPT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_BLEND_OPT_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SPARE 31:22 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_2_PREROP_SPARE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */
|
|
#define NV_PGRAPH_DEBUG_3_FLUSHING 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_FLUSHING_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_FLUSHING_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FLUSHING_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_ZCULLFLUSH 1:1 /* CWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_ZCULLFLUSH_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_ZCULLFLUSH_ACTIVATE 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_DEBUG_3_HW_CONTEXT_SWITCH 2:2 /* RWIVF */
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|
#define NV_PGRAPH_DEBUG_3_HW_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_HW_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_HW_CONTEXT_SWITCH_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CHECK 3:3 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_FD_CHECK_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CHECK_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CHECK_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FAST_DATA_STRTCH 4:4 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_FAST_DATA_STRTCH_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_FAST_DATA_STRTCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_FAST_DATA_STRTCH_INIT 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_DEBUG_3_FAST_3D_SHADOW_DATA 5:5 /* RWIVF */
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|
#define NV_PGRAPH_DEBUG_3_FAST_3D_SHADOW_DATA_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_FAST_3D_SHADOW_DATA_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_FAST_3D_SHADOW_DATA_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_CHECK_64BYTE_ALIGN 6:6 /* RWIVF */
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|
#define NV_PGRAPH_DEBUG_3_CHECK_64BYTE_ALIGN_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_CHECK_64BYTE_ALIGN_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_CHECK_64BYTE_ALIGN_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_ZFLUSH 7:7 /* CWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_ZFLUSH_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_ZFLUSH_ACTIVATE 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_STEP 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_STEP_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_SINGLE_STEP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_STEP_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_RDI_IDLE_WAIT 9:9 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_RDI_IDLE_WAIT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_RDI_IDLE_WAIT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_RDI_IDLE_WAIT_INIT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_IDLE_FILTER 10:10 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_IDLE_FILTER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_IDLE_FILTER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_IDLE_FILTER_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CLEAR 11:11 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CLEAR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CLEAR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FD_CLEAR_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_SYNCHRONIZE 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_SYNCHRONIZE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_SYNCHRONIZE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_SYNCHRONIZE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_OBJECT_RELOAD 14:14 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_OBJECT_RELOAD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_OBJECT_RELOAD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_OBJECT_RELOAD_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_PM_TRIGGER 15:15 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_PM_TRIGGER_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_PM_TRIGGER_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_PM_TRIGGER_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_ALTARCH 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_ALTARCH_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_ALTARCH_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_ALTARCH_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_CYCLE_LOAD 17:17 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_CYCLE_LOAD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_CYCLE_LOAD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_SINGLE_CYCLE_LOAD_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_BILINEAR_3D 18:18 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_BILINEAR_3D_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_BILINEAR_3D_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_BILINEAR_3D_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_VOLATILE_RESET 19:19 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_VOLATILE_RESET_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_VOLATILE_RESET_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_VOLATILE_RESET_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21:21 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_FAIL_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_FAIL_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_DATA_CHECK_FAIL_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FORMAT_CHECK 22:22 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_FORMAT_CHECK_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_FORMAT_CHECK_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_FORMAT_CHECK_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_DMA_CHECK 23:23 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_DMA_CHECK_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_DMA_CHECK_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_DMA_CHECK_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_STATE_CHECK 24:24 /* RWIVF */
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|
#define NV_PGRAPH_DEBUG_3_STATE_CHECK_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_3_STATE_CHECK_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_STATE_CHECK_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_KELVIN_HWFLIP 25:25 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_KELVIN_HWFLIP_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_KELVIN_HWFLIP_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_KELVIN_HWFLIP_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_FAST_3D_RESTORE 26:26 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_FAST_3D_RESTORE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_3_FAST_3D_RESTORE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_FAST_3D_RESTORE_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_STATE3D_CHECK 27:27 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_STATE3D_CHECK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_3_STATE3D_CHECK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_STATE3D_CHECK_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_XFMODE_COALESCE 28:28 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_XFMODE_COALESCE_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_XFMODE_COALESCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_XFMODE_COALESCE_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_3_CTX_METHODS 29:29 /* RWIVF */
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#define NV_PGRAPH_DEBUG_3_CTX_METHODS_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_CTX_METHODS_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_CTX_METHODS_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_OP_METHODS 30:30 /* RWIVF */
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|
#define NV_PGRAPH_DEBUG_3_OP_METHODS_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_OP_METHODS_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_OP_METHODS_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_3_IGNORE_PATCHVALID 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_3_IGNORE_PATCHVALID_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_3_IGNORE_PATCHVALID_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_3_IGNORE_PATCHVALID_INIT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_4 0x00400090 /* RW-4R */
|
|
#define NV_PGRAPH_DEBUG_4_FD_SPARE1 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_FD_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_FD_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_FD_SPARE2 1:1 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_FD_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_FD_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_COARSE_RSTR_SPARE1 2:2 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_COARSE_RSTR_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_COARSE_RSTR_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_COARSE_RSTR_SPARE2 3:3 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_COARSE_RSTR_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_COARSE_RSTR_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_RSTR2D_SPARE1 4:4 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_RSTR2D_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_RSTR2D_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_RSTR2D_SPARE2 5:5 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_RSTR2D_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_RSTR2D_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_FINE_RSTR_SPARE1 6:6 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_FINE_RSTR_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_FINE_RSTR_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_FRSTR_HALF_PIPE 6:6 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_FRSTR_HALF_PIPE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_FRSTR_HALF_PIPE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_FINE_RSTR_SPARE2 7:7 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_FINE_RSTR_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_FINE_RSTR_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_TEX_SPARE1 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_TEX_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_TEX_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_TEX_SPARE2 9:9 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_TEX_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_TEX_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_COMB_SPARE1 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_COMB_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_COMB_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_COMB_SPARE2 13:13 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_COMB_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_COMB_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE1 14:14 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE2 15:15 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_XF_SPARE1 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_XF_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_XF_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_XF_SPARE2 17:17 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_XF_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_XF_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE3 18:18 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE4 19:19 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE4_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SETUP_SPARE4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_IDX_SPARE1 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_IDX_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_IDX_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_IDX_SPARE2 21:21 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_IDX_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_IDX_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_VTX_SPARE1 22:22 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_VTX_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_VTX_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_VTX_SPARE2 23:23 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_VTX_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_VTX_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_CAS_SPARE1 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_CAS_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_CAS_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_CAS_SPARE2 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_CAS_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_CAS_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SHD_SPARE1 26:26 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SHD_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SHD_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SHD_SPARE2 27:27 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SHD_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SHD_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SHDBE_SPARE1 28:28 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SHDBE_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SHDBE_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_SHDBE_SPARE2 29:29 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_SHDBE_SPARE2_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_SHDBE_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_DISABLE_H0 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_DISABLE_H0_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_DISABLE_H0_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_4_DISABLE_H1 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_4_DISABLE_H1_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_4_DISABLE_H1_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5 0x00400094 /* RW-4R */
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#define NV_PGRAPH_DEBUG_5_ZCULL_REQ_FULL_CVG 0:0 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_REQ_FULL_CVG_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_REQ_FULL_CVG_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_REQ_FULL_CVG_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_FB_BUSY 1:1 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_FB_BUSY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_FB_BUSY_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_FB_BUSY_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_S_ON_Z 2:2 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_S_ON_Z_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_S_ON_Z_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_PUNT_S_ON_Z_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_RETURN_COMP 3:3 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_RETURN_COMP_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_RETURN_COMP_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_RETURN_COMP_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE4 4:4 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE4_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE5 5:5 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE5_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE6 6:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE6_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE7 7:7 /* RWIVF */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_5_ZCULL_SPARE7_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6 0x00400b80 /* RW-4R */
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#define NV_PGRAPH_DEBUG_6_ROP_SEP_ZC_READS 0:0 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_SEP_ZC_READS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_SEP_ZC_READS_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_SEP_ZC_READS_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_3D 1:1 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_3D_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_3D_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_3D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_2D 2:2 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_2D_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_2D_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_DITHER_2D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_EARLY_ZABORT 3:3 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_EARLY_ZABORT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_EARLY_ZABORT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_EARLY_ZABORT_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_PASS_ROPFLUSH 4:4 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_PASS_ROPFLUSH_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_PASS_ROPFLUSH_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_PASS_ROPFLUSH_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_DRAIN 5:5 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_DRAIN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_DRAIN_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_DRAIN_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER 9:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER_INIT 0x00000004 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER_FULL 0x00000008 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER2 13:10 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER2_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER2_INIT 0x00000004 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CBUF_HIGHWATER2_FULL 0x00000008 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_3D 14:14 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_3D_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_3D_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_3D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_2D 15:15 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_2D_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_2D_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_COALESCE_2D_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_FIXED_ADRS 16:16 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_FIXED_ADRS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_FIXED_ADRS_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_FIXED_ADRS_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_FAST_KEEP_DST 17:17 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_FAST_KEEP_DST_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_FAST_KEEP_DST_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_FAST_KEEP_DST_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_FORCE_CREAD 18:18 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_FORCE_CREAD_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_FORCE_CREAD_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_FORCE_CREAD_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ALLOW_3D_SKIP_READ 19:19 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_ALLOW_3D_SKIP_READ_ENABLED 0x00000001 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_ALLOW_3D_SKIP_READ_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ALLOW_3D_SKIP_READ_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCMP_ALWAYS_READ 20:20 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCMP_ALWAYS_READ_ENABLED 0x00000001 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCMP_ALWAYS_READ_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCMP_ALWAYS_READ_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCOMPRESS_EN 21:21 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCOMPRESS_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCOMPRESS_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCOMPRESS_EN_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CREADS 22:22 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CREADS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CREADS_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CREADS_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CWRITES 23:23 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CWRITES_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CWRITES_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_BURST_CWRITES_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_AUTO_INIT 24:24 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_AUTO_INIT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_AUTO_INIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_AUTO_INIT_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_HASH_TEST1 25:25 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_HASH_TEST1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_HASH_TEST1_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_HASH_TEST1_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_INTERLOCK 26:26 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_INTERLOCK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_INTERLOCK_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_INTERLOCK_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZREAD 28:27 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_ZREAD_NORMAL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZREAD_FORCE_ZREAD 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZREAD_FORCE_NO_ZREAD 0x00000002 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZREAD_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCULL_DATA 29:29 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCULL_DATA_USE 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCULL_DATA_DISCARD 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_ZCULL_DATA_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CROP_SWALLOW 30:30 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_ROP_CROP_SWALLOW_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_ROP_CROP_SWALLOW_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_ROP_CROP_SWALLOW_INIT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_SPARE_BIT31 31:31 /* RWIVF */
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#define NV_PGRAPH_DEBUG_6_SPARE_BIT31_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_6_SPARE_BIT31_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_SPARE_BIT31_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_6_BITS 31:0 /* RWIUF */
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#define NV_PGRAPH_DEBUG_6_BITS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7 0x00400b84 /* RW-4R */
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#define NV_PGRAPH_DEBUG_7_ROP_INIT_ZRD_TMSTAMP 0:0 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_INIT_ZRD_TMSTAMP_DEFAULT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_INIT_ZRD_TMSTAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZCULL_NO_STALE 1:1 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZCULL_NO_STALE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZCULL_NO_STALE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZCULL_NO_STALE_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZROP_INTERLOCK 2:2 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZROP_INTERLOCK_ENA 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZROP_INTERLOCK_DIS 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZROP_INTERLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_VISIBLE 3:3 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_VISIBLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_VISIBLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_VISIBLE_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_PURGE_PER_PKT 4:4 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_PURGE_PER_PKT_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_PURGE_PER_PKT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_PURGE_PER_PKT_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_16BYTE_WR 5:5 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_16BYTE_WR_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_16BYTE_WR_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_16BYTE_WR_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_FSTCLR_EXPAND 6:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_FSTCLR_EXPAND_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_FSTCLR_EXPAND_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_FSTCLR_EXPAND_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_RMW_DISABLE 7:7 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_RMW_DISABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_RMW_DISABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_FORCE_NO_RMW_DISABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_COMPRESS 8:8 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_COMPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_COMPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_COMPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_CMPR_FULL_BE_ONLY 9:9 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_CMPR_FULL_BE_ONLY_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_CMPR_FULL_BE_ONLY_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_CMPR_FULL_BE_ONLY_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_ALWAYS_WR_STENCIL 10:10 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_ALWAYS_WR_STENCIL_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_ALWAYS_WR_STENCIL_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_ALWAYS_WR_STENCIL_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_SKIP_WR_EQ 11:11 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_SKIP_WR_EQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_SKIP_WR_EQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_INHIBIT_SKIP_WR_EQ_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_SELECTPM 13:12 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_SELECTPM_NORMAL 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_SELECTPM_PKTRF_STALL 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_SELECTPM_CMPR_STALL 0x00000002 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_SELECTPM_TAGREL_STALL 0x00000003 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_SELECTPM_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA1 14:14 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA1_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA1_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA2 15:15 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA2_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA2_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA2_INIT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA3 16:16 /* RWIVF */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA3_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA3_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_SELECTPM 18:17 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_SELECTPM_GRP3 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_SELECTPM_GRP2 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_SELECTPM_GRP1 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_SELECTPM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA4 19:19 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA4_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA4_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZWR_EXTRA4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_HASH_TAGS 24:20 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_HASH_TAGS_01 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_HASH_TAGS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_BLIT_HASH 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_BLIT_HASH_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_BLIT_HASH_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_BLIT_HASH_INIT 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_DEBUG_7_ROP_ZROP_RAISE_PRI 26:26 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZROP_RAISE_PRI_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZROP_RAISE_PRI_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZROP_RAISE_PRI_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA0 27:27 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA0_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA0_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA1 28:28 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA1_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA1_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_ZRD_EXTRA1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_RAISE_PRI 29:29 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_RAISE_PRI_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_RAISE_PRI_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_CROP_RAISE_PRI_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_TC_SELECT_REQ 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_TC_SELECT_REQ_PIPEID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_TC_SELECT_REQ_BANK 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_7_ROP_TC_SELECT_REQ_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_7_SPARE 31:31 /* RWIUF */
|
|
#define NV_PGRAPH_DEBUG_7_BITS 31:0 /* RWIUF */
|
|
#define NV_PGRAPH_DEBUG_7_BITS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8 0x00400098 /* RW-4R */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_WATERMARK 9:0 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_WATERMARK_64 0x00000040 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_WATERMARK_PERF 0x00000094 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_WATERMARK_INIT 0x00000078 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_WATERMARK 19:10 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_WATERMARK_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_WATERMARK_PERF 0x00000094 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_WATERMARK_INIT 0x00000078 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_DEBUG 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_DEBUG_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_DEBUG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFO_DEBUG_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_DEBUG 21:21 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_DEBUG_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_DEBUG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FIFOP1_DEBUG_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_ONE_TEXTURE 29:29 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_ONE_TEXTURE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_ONE_TEXTURE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_ONE_TEXTURE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FOG_LINE_CLAMP 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FOG_LINE_CLAMP_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FOG_LINE_CLAMP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_FOG_LINE_CLAMP_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_COMBINER_NEG_TEXTURE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_COMBINER_NEG_TEXTURE_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_8_COMBINER_NEG_TEXTURE_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_COMBINER_NEG_TEXTURE_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_SPARE 31:10 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_8_SHADER_SPARE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9 0x0040009C /* RW-4R */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH0_CHECK 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH0_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH0_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH0_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH1_CHECK 1:1 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH1_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH1_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH1_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH2_CHECK 2:2 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH2_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH2_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH2_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH3_CHECK 3:3 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH3_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH3_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_PATCH3_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_END_PATCH_CHECK 4:4 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_END_PATCH_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_END_PATCH_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_END_PATCH_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_END_SWATCH_CHECK 5:5 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_END_SWATCH_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_END_SWATCH_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_END_SWATCH_CHECK_INIT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_9_BEGIN_END_CURVE_CHECK 6:6 /* RWIVF */
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#define NV_PGRAPH_DEBUG_9_BEGIN_END_CURVE_CHECK_ENABLE 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_9_BEGIN_END_CURVE_CHECK_DISABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_9_BEGIN_END_CURVE_CHECK_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_9_CURVE_COEFF_CHECK 7:7 /* RWIVF */
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#define NV_PGRAPH_DEBUG_9_CURVE_COEFF_CHECK_ENABLE 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_9_CURVE_COEFF_CHECK_DISABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_9_CURVE_COEFF_CHECK_INIT 0x00000000 /* RW--V */
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#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS0_CHECK 8:8 /* RWIVF */
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#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS0_CHECK_ENABLE 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS0_CHECK_DISABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS0_CHECK_INIT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS1_CHECK 9:9 /* RWIVF */
|
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#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS1_CHECK_ENABLE 0x00000000 /* RWI-V */
|
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#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS1_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS1_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS2_CHECK 10:10 /* RWIVF */
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|
#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS2_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS2_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_BEGIN_TRANS2_CHECK_INIT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_END_TRANSITION_CHECK 11:11 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_9_END_TRANSITION_CHECK_ENABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_9_END_TRANSITION_CHECK_DISABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_9_END_TRANSITION_CHECK_INIT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_DEBUG_10 0x00400b88 /* RW-4R */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_CRD 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_CRD_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_CRD_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_CRD_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_KILL 1:1 /* RWIVF */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_KILL_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_KILL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_10_ROP_BLEND_OPT_KILL_INIT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DEBUG_10_SPARE 31:2 /* RWIUF */
|
|
#define NV_PGRAPH_DEBUG_10_BITS 31:0 /* RWIUF */
|
|
#define NV_PGRAPH_DEBUG_10_BITS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */
|
|
#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_R 6:6 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_R_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_R_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_R_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_W 7:7 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_W_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_W_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_DMA_W_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_A 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_A_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_A_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_A_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_B 9:9 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_B_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_B_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_TEX_B_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_VTX 10:10 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_VTX_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_VTX_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_TLB_PRESENT_VTX_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_STATE3D 13:13 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_STATE3D_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_STATE3D_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_STATE3D_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_INTR_ERROR 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_ERROR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_ERROR_RESET 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_INTR_SINGLE_STEP 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_SINGLE_STEP_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_INTR_SINGLE_STEP_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_SINGLE_STEP_RESET 0x00000001 /* -W--C */
|
|
#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */
|
|
#define NV_PGRAPH_NSTATUS_STATE_IN_USE 23:23 /* RWIVF */
|
|
#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NSTATUS_INVALID_STATE 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 26:26 /* RWIVF */
|
|
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */
|
|
#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA 5:5 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_DMA_VTX_PROTECTION 16:16 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_DMA_VTX_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_DMA_VTX_PROTECTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_IDX_INLINE_REUSE 17:17 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_IDX_INLINE_REUSE_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_IDX_INLINE_REUSE_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_INVALID_OPERATION 18:18 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_INVALID_OPERATION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_INVALID_OPERATION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_FD_INVALID_OP 19:19 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_FD_INVALID_OP_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_FD_INVALID_OP_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_FD_ERROR_CODE 21:20 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_FD_ERROR_CODE_0 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_FD_ERROR_CODE_1 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_FD_ERROR_CODE_2 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_FD_ERROR_CODE_3 0x00000003 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_TEX_A_PROTECTION 22:22 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_TEX_A_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_TEX_A_PROTECTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_NSOURCE_TEX_B_PROTECTION 23:23 /* R-IVF */
|
|
#define NV_PGRAPH_NSOURCE_TEX_B_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_NSOURCE_TEX_B_PROTECTION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */
|
|
#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_R 6:6 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_R_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_R_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_W 7:7 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_W_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_DMA_W_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_A 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_A_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_A_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_B 9:9 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_B_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_TEX_B_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_VTX 10:10 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_VTX_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_VTX_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_STATE3D 13:13 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_STATE3D_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_STATE3D_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_ERROR 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_ERROR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_ERROR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_INTR_EN_SINGLE_STEP 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_INTR_EN_SINGLE_STEP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_INTR_EN_SINGLE_STEP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CONTROL 0x00400144 /* RW-4R */
|
|
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */
|
|
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */
|
|
#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */
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#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CTX_USER 0x00400148 /* RW-4R */
|
|
#define NV_PGRAPH_CTX_USER_CHANNEL_3D 0:0 /* RWIVF */
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|
#define NV_PGRAPH_CTX_USER_CHANNEL_3D_FALSE 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_CTX_USER_CHANNEL_3D_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_USER_CHANNEL_3D_VALID 4:4 /* RWIVF */
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#define NV_PGRAPH_CTX_USER_CHANNEL_3D_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PGRAPH_CTX_USER_CHANNEL_3D_VALID_TRUE 0x00000001 /* RWI-V */
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|
#define NV_PGRAPH_CTX_USER_CHANNEL_3D_ID 12:8 /* RWIVF */
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#define NV_PGRAPH_CTX_USER_CHANNEL_3D_ID_0 0x00000000 /* RWI-V */
|
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#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */
|
|
#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_USER_CHID 28:24 /* RWIVF */
|
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#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_USER_SINGLE_STEP 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_CTX_USER_SINGLE_STEP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CTX_USER_SINGLE_STEP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1 0x0040014C /* RW-4R */
|
|
#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SYNCHRONIZE 18:18 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SYNCHRONIZE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SYNCHRONIZE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_ENDIAN_MODE 19:19 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_ENDIAN_MODE_LITTLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_ENDIAN_MODE_BIG 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_DITHER_MODE 21:20 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_DITHER_MODE_COMPATIBILITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_DITHER_MODE_DITHER 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_DITHER_MODE_TRUNCATE 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_DITHER_MODE_MS 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CLASS_TYPE 22:22 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CLASS_TYPE_COMPATIBILITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CLASS_TYPE_PERFORMANCE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SINGLE_STEP 23:23 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SINGLE_STEP_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_SINGLE_STEP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE0 25:25 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE0_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE0_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE1 26:26 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE1_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE1_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_PATTERN 27:27 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_PATTERN_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_PATTERN_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_ROP 28:28 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_ROP_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_ROP_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA1 29:29 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA1_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA1_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA4 30:30 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA4_INVALID 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_BETA4_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */
|
|
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_CTX_SWITCH2 0x00400150 /* RW-4R */
|
|
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_AY8 0x15 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_EYB8ECR8EYA8ECB8 0x16 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_ECR8EYB8ECB8EYA8 0x17 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH3 0x00400154 /* RW-4R */
|
|
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */
|
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#define NV_PGRAPH_CTX_SWITCH4 0x00400158 /* RW-4R */
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#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */
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#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */
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#define NV_PGRAPH_CTX_SWITCH5 0x0040015C /* RW-4R */
|
|
#define NV_PGRAPH_CTX_SWITCH5_TRAP_BITS 31:0 /* RWXUF */
|
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#define NV_PGRAPH_CTX_SWITCH5_TRAP_BITS_DISABLED 0x0000 /* RW--V */
|
|
#define NV_PGRAPH_CTX_CACHE1(i) (0x00400160+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */
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|
#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */
|
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#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 17:15 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE1_SYNCHRONIZE 18:18 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_CACHE1_ENDIAN_MODE 19:19 /* RWXUF */
|
|
#define NV_PGRAPH_CTX_CACHE1_DITHER_MODE 21:20 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE1_CLASS_TYPE 22:22 /* RWXVF */
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#define NV_PGRAPH_CTX_CACHE1_SINGLE_STEP 23:23 /* RWXVF */
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|
#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */
|
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#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE0 25:25 /* RWXVF */
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|
#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE1 26:26 /* RWXVF */
|
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#define NV_PGRAPH_CTX_CACHE1_CONTEXT_PATTERN 27:27 /* RWXVF */
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#define NV_PGRAPH_CTX_CACHE1_CONTEXT_ROP 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE1_CONTEXT_BETA1 29:29 /* RWXVF */
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#define NV_PGRAPH_CTX_CACHE1_CONTEXT_BETA4 30:30 /* RWXVF */
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|
#define NV_PGRAPH_CTX_CACHE2(i) (0x00400180+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE3(i) (0x004001a0+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE4(i) (0x004001c0+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */
|
|
#define NV_PGRAPH_CTX_CACHE5(i) (0x004001e0+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_CTX_CACHE5__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_CTX_CACHE5_TRAP_BITS 31:0 /* RWXVF */
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|
#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */
|
|
#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */
|
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#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x004007a0+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 12:2 /* RWXVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 18:16 /* RWXVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_CODE 21:20 /* RWXVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_CODE_DOUBLE_NONINCR 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_CODE_DOUBLE_INCR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_CODE_SINGLE 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_0_CODE_CHSW 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x004007c0+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_2(i) (0x004007e0+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_2__SIZE_1 8 /* */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_2_ARGUMENT 31:0 /* RWXVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400760 /* RW-4R */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 3:0 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 7:4 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2 0x00400764 /* RW-4R */
|
|
#define NV_PGRAPH_FFINTFC_ST2_MTHD 12:2 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH 18:16 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID 24:20 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_16 0x00000010 /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_17 0x00000011 /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_18 0x00000012 /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_19 0x00000013 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_20 0x00000014 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_21 0x00000015 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_22 0x00000016 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_23 0x00000017 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_24 0x00000018 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_25 0x00000019 /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_26 0x0000001A /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_27 0x0000001B /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_28 0x0000001C /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_29 0x0000001D /* RW--V */
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#define NV_PGRAPH_FFINTFC_ST2_CHID_30 0x0000001E /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_CHID_31 0x0000001F /* RW--V */
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|
#define NV_PGRAPH_FFINTFC_ST2_DATAHIGH 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DATAHIGH_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DATAHIGH_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_STATUS 26:26 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 27:27 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHSWITCH 28:28 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHSWITCH_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_CHSWITCH_SET 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_FIFOHOLD 29:29 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_FIFOHOLD_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_FIFOHOLD_SET 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_MODE 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_MODE_NONINCREMENTING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_MODE_INCREMENTING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DL 0x00400768 /* RW-4R */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DL_ARGUMENT 31:0 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DL_ARGUMENT_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DH 0x0040076c /* RW-4R */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DH_ARGUMENT 31:0 /* RWIVF */
|
|
#define NV_PGRAPH_FFINTFC_ST2_DH_ARGUMENT_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */
|
|
#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_FINE_RASTERIZER 1:1 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_FINE_RASTERIZER_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_FINE_RASTERIZER_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_COARSE_RASTERIZER 2:2 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_COARSE_RASTERIZER_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_COARSE_RASTERIZER_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_FE_3D 3:3 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_FE_3D_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_FE_3D_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_FE_2D 4:4 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_FE_2D_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_FE_2D_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_XY_LOGIC 5:5 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_WAITCRTC 6:6 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_WAITCRTC_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_WAITCRTC_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_RASTERIZER_2D 7:7 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_RASTERIZER_2D_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_RASTERIZER_2D_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_IDX 8:8 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_IDX_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_IDX_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_XF 9:9 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_XF_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_XF_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_VTX 10:10 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_VTX_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_VTX_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_CAS 11:11 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_CAS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_CAS_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_PORT_NOTIFY 12:12 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_SHADER 13:13 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_SHADER_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_SHADER_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_SHADER_BE 14:14 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_SHADER_BE_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_SHADER_BE_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_DMA_WARNING_NOTIFY 22:22 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_DMA_WARNING_NOTIFY_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_DMA_WARNING_NOTIFY_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_ZCULL 23:23 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_ZCULL_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_ZCULL_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_FDIFF 24:24 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_FDIFF_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_FDIFF_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_SETUP 25:25 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_SETUP_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_SETUP_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_CACHE 26:26 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_COMBINER 27:27 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_COMBINER_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_COMBINER_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_PREROP 28:28 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_ROP 29:29 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_PORT_USER 30:30 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_STATUS_PORT_FB 31:31 /* R-IVF */
|
|
#define NV_PGRAPH_STATUS_PORT_FB_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PGRAPH_STATUS_PORT_FB_BUSY 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */
|
|
#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */
|
|
#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 /* R-XUF */
|
|
#define NV_PGRAPH_TRAPPED_ADDR_CHID 24:20 /* R-XUF */
|
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#define NV_PGRAPH_TRAPPED_ADDR_DHV 28:28 /* R-XUF */
|
|
#define NV_PGRAPH_TRAPPED_DATA_LOW 0x00400708 /* R--4R */
|
|
#define NV_PGRAPH_TRAPPED_DATA_LOW_VALUE 31:0 /* R-XVF */
|
|
#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C /* R--4R */
|
|
#define NV_PGRAPH_TRAPPED_DATA_HIGH_VALUE 31:0 /* R-XVF */
|
|
#define NV_PGRAPH_SURFACE 0x00400710 /* RW-4R */
|
|
#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */
|
|
#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_SURFACE_TYPE_056 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_TYPE_096 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_TYPE_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_ANTIALIASING 5:4 /* RWIVF */
|
|
#define NV_PGRAPH_SURFACE_ANTIALIASING_CENTER_1 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_ANTIALIASING_CENTER_CORNER_2 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SURFACE_ANTIALIASING_SQUARE_OFFSET_4 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_SURFACE_ANTIALIASING_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_WRITE_BLIT 10:8 /* RWIVF */
|
|
#define NV_PGRAPH_SURFACE_WRITE_BLIT_0 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_SURFACE_WRITE_BLIT_09F 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_SURFACE_READ_BLIT 14:12 /* RWIVF */
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|
#define NV_PGRAPH_SURFACE_READ_BLIT_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_READ_BLIT_09F 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_SURFACE_MODULO_BLIT 18:16 /* RWIVF */
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#define NV_PGRAPH_SURFACE_MODULO_BLIT_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_MODULO_BLIT_09F 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_WRITE_3D 22:20 /* RWIVF */
|
|
#define NV_PGRAPH_SURFACE_WRITE_3D_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_WRITE_3D_056 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_WRITE_3D_096 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_WRITE_3D_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_READ_3D 26:24 /* RWIVF */
|
|
#define NV_PGRAPH_SURFACE_READ_3D_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_READ_3D_056 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_READ_3D_096 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_READ_3D_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_MODULO_3D 30:28 /* RWIVF */
|
|
#define NV_PGRAPH_SURFACE_MODULO_3D_0 0x00000002 /* RWI-V */
|
|
#define NV_PGRAPH_SURFACE_MODULO_3D_056 0x00000002 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_MODULO_3D_096 0x00000002 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACE_MODULO_3D_097 0x00000002 /* RWC-V */
|
|
#define NV_PGRAPH_INCREMENT 0x0040071C /* RW-4R */
|
|
#define NV_PGRAPH_INCREMENT_READ_BLIT 0:0 /* CWIVF */
|
|
#define NV_PGRAPH_INCREMENT_READ_BLIT_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_INCREMENT_READ_BLIT_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_INCREMENT_READ_3D 1:1 /* CWIVF */
|
|
#define NV_PGRAPH_INCREMENT_READ_3D_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_INCREMENT_READ_3D_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_NOTIFY 0x00400718 /* RW-4R */
|
|
#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_REQ 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_REQ_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_REQ_PENDING 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STYLE 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STATUS 30:28 /* RWIVF */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STATUS_NO_WARNING 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STATUS_INVALID_ENUM 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STATUS_INVALID_VALUE 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_NOTIFY_WARNING_STATUS_INVALID_OP 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_BOFFSET(i) (0x00400820+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */
|
|
#define NV_PGRAPH_BOFFSET_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BOFFSET0 0x00400820 /* RW-4R */
|
|
#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */
|
|
#define NV_PGRAPH_BOFFSET0_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BOFFSET0_LINADRS_042 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET0_LINADRS_058 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET0_LINADRS_062 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET1 0x00400824 /* RW-4R */
|
|
#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */
|
|
#define NV_PGRAPH_BOFFSET1_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BOFFSET1_LINADRS_042 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET1_LINADRS_059 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET1_LINADRS_062 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET2 0x00400828 /* RW-4R */
|
|
#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */
|
|
#define NV_PGRAPH_BOFFSET2_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BOFFSET2_LINADRS_056 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET2_LINADRS_05A 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET2_LINADRS_096 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET2_LINADRS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET3 0x0040082C /* RW-4R */
|
|
#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */
|
|
#define NV_PGRAPH_BOFFSET3_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BOFFSET3_LINADRS_056 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET3_LINADRS_05B 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BOFFSET3_LINADRS_096 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BOFFSET3_LINADRS_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BOFFSET4 0x00400830 /* RW-4R */
|
|
#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */
|
|
#define NV_PGRAPH_BOFFSET4_LINADRS 29:0 /* RWIUF */
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|
#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BOFFSET5 0x00400834 /* RW-4R */
|
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#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */
|
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#define NV_PGRAPH_BOFFSET5_LINADRS 29:0 /* RWIUF */
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|
#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_BOFFSET5_LINADRS_052 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BOFFSET5_LINADRS_09E 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BBASE(i) (0x00400838+(i)*4) /* RW-4A */
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|
#define NV_PGRAPH_BBASE__SIZE_1 6 /* */
|
|
#define NV_PGRAPH_BBASE_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_BBASE0 0x00400838 /* RW-4R */
|
|
#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */
|
|
#define NV_PGRAPH_BBASE0_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BBASE1 0x0040083c /* RW-4R */
|
|
#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */
|
|
#define NV_PGRAPH_BBASE1_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_BBASE2 0x00400840 /* RW-4R */
|
|
#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */
|
|
#define NV_PGRAPH_BBASE2_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BBASE3 0x00400844 /* RW-4R */
|
|
#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */
|
|
#define NV_PGRAPH_BBASE3_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BBASE4 0x00400848 /* RW-4R */
|
|
#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */
|
|
#define NV_PGRAPH_BBASE4_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BBASE5 0x0040084C /* RW-4R */
|
|
#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */
|
|
#define NV_PGRAPH_BBASE5_LINADRS 29:0 /* RWIUF */
|
|
#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BPITCH(i) (0x00400850+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */
|
|
#define NV_PGRAPH_BPITCH_VALUE 15:0 /* RWIUF */
|
|
#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BPITCH0 0x00400850 /* RW-4R */
|
|
#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */
|
|
#define NV_PGRAPH_BPITCH0_VALUE 15:0 /* RWIUF */
|
|
#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BPITCH0_VALUE_042 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH0_VALUE_058 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH0_VALUE_062 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH1 0x00400854 /* RW-4R */
|
|
#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */
|
|
#define NV_PGRAPH_BPITCH1_VALUE 15:0 /* RWIUF */
|
|
#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BPITCH1_VALUE_042 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH1_VALUE_059 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH1_VALUE_062 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH2 0x00400858 /* RW-4R */
|
|
#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */
|
|
#define NV_PGRAPH_BPITCH2_VALUE 15:0 /* RWIUF */
|
|
#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BPITCH2_VALUE_056 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH2_VALUE_05A 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH2_VALUE_096 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH2_VALUE_097 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH3 0x0040085C /* RW-4R */
|
|
#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */
|
|
#define NV_PGRAPH_BPITCH3_VALUE 15:0 /* RWIUF */
|
|
#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BPITCH3_VALUE_056 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH3_VALUE_05B 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH3_VALUE_096 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH3_VALUE_097 0x00000040 /* RWC-V */
|
|
#define NV_PGRAPH_BPITCH4 0x00400860 /* RW-4R */
|
|
#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */
|
|
#define NV_PGRAPH_BPITCH4_VALUE 15:0 /* RWIUF */
|
|
#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT(i) (0x00400864+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */
|
|
#define NV_PGRAPH_BLIMIT_VALUE 29:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLIMIT_ADDRESSING 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT_ADDRESSING_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT0 0x00400864 /* RW-4R */
|
|
#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */
|
|
#define NV_PGRAPH_BLIMIT0_VALUE 29:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLIMIT0_ADDRESSING 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT0_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT0_ADDRESSING_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT1 0x00400868 /* RW-4R */
|
|
#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */
|
|
#define NV_PGRAPH_BLIMIT1_VALUE 29:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLIMIT1_ADDRESSING 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT1_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT1_ADDRESSING_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT2 0x0040086c /* RW-4R */
|
|
#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */
|
|
#define NV_PGRAPH_BLIMIT2_VALUE 29:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLIMIT2_ADDRESSING 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT2_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT2_ADDRESSING_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT3 0x00400870 /* RW-4R */
|
|
#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */
|
|
#define NV_PGRAPH_BLIMIT3_VALUE 29:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLIMIT3_ADDRESSING 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT3_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT3_ADDRESSING_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT4 0x00400874 /* RW-4R */
|
|
#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */
|
|
#define NV_PGRAPH_BLIMIT4_VALUE 29:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLIMIT4_ADDRESSING 30:30 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT4_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT4_ADDRESSING_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */
|
|
#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */
|
|
#define NV_PGRAPH_BLIMIT5 0x00400878 /* RW-4R */
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#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */
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#define NV_PGRAPH_BLIMIT5_VALUE 29:0 /* RWXUF */
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#define NV_PGRAPH_BLIMIT5_ADDRESSING 30:30 /* RWIVF */
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#define NV_PGRAPH_BLIMIT5_ADDRESSING_LINEAR 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BLIMIT5_ADDRESSING_TILED 0x00000001 /* RW--V */
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#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */
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#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */
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#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */
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#define NV_PGRAPH_BSWIZZLE2 0x00400818 /* RW-4R */
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#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */
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#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BSWIZZLE2_WIDTH_MAX 0x0000000c /* RW--V */
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#define NV_PGRAPH_BSWIZZLE2_WIDTH_056 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE2_WIDTH_096 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE2_WIDTH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */
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#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BSWIZZLE2_HEIGHT_MAX 0x0000000c /* RW--V */
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#define NV_PGRAPH_BSWIZZLE2_HEIGHT_056 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE2_HEIGHT_096 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE2_HEIGHT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE5 0x0040081c /* RW-4R */
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#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */
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#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BSWIZZLE5_WIDTH_052 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE5_WIDTH_09E 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */
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#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BSWIZZLE5_HEIGHT_052 0x00000000 /* RWC-V */
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#define NV_PGRAPH_BSWIZZLE5_HEIGHT_09E 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TILE(i) (0x00400900+(i)*16) /* RW-4A */
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#define NV_PGRAPH_TILE__SIZE_1 8 /* */
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#define NV_PGRAPH_TILE_REGION 0:0 /* RWIVF */
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#define NV_PGRAPH_TILE_REGION_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_TILE_REGION_VALID 0x00000001 /* RW--V */
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#define NV_PGRAPH_TILE_BANK0_SENSE 1:1 /* RWIVF */
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#define NV_PGRAPH_TILE_BANK0_SENSE_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_TILE_BANK0_SENSE_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_TILE_ADR 31:14 /* RW-UF */
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#define NV_PGRAPH_TLIMIT(i) (0x00400904+(i)*16) /* RW-4A */
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#define NV_PGRAPH_TLIMIT__SIZE_1 8 /* */
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#define NV_PGRAPH_TLIMIT_ADR 31:14 /* RW-UF */
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#define NV_PGRAPH_TSIZE(i) (0x00400908+(i)*16) /* RW-4A */
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#define NV_PGRAPH_TSIZE__SIZE_1 8 /* */
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#define NV_PGRAPH_TSIZE_PITCH 15:8 /* RW-UF */
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#define NV_PGRAPH_TSTATUS(i) (0x0040090c+(i)*16) /* R--4A */
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#define NV_PGRAPH_TSTATUS__SIZE_1 8 /* */
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#define NV_PGRAPH_TSTATUS_PRIME 1:0 /* R--VF */
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#define NV_PGRAPH_TSTATUS_FACTOR 6:4 /* R--VF */
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#define NV_PGRAPH_TSTATUS_REGION 31:31 /* R-I-F */
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#define NV_PGRAPH_ZCOMP(i) (0x00400980+(i)*4) /* RW-4A */
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#define NV_PGRAPH_ZCOMP__SIZE_1 8 /* */
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#define NV_PGRAPH_ZCOMP_OFFSET 0x004009a0 /* RW-4R */
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#define NV_PGRAPH_FBCFG0 0x004009a4 /* RW-4R */
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#define NV_PGRAPH_FBCFG1 0x004009a8 /* RW-4R */
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#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */
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#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */
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#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_042 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_058 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH0_062 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */
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#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_042 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_059 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH1_062 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */
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#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_056 0x00000002 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_05A 0x00000002 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_096 0x00000002 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH2_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */
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#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BPIXEL_DEPTH3_Z16 0x00000001 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH3_Z24S8 0x00000002 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH3_05B 0x00000002 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH3_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */
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#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */
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#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_052 0x00000001 /* RWC-V */
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#define NV_PGRAPH_BPIXEL_DEPTH5_09E 0x00000001 /* RWC-V */
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#define NV_PGRAPH_LIMIT_VIOL_PIX 0x0040080c /* RW-4R */
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#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 31:0 /* RWIVF */
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#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400810 /* RW-4R */
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#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 31:0 /* RWIVF */
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#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_LIMIT_VIOL_MODE 0x00400800 /* RW-4R */
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTBPITCH 0:0 /* RWIVF */
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTBPITCH_NO_VIOL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTBPITCH_VIOL 0x00000001 /* RW--V */
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTBLIMIT 1:1 /* RWIVF */
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTBLIMIT_NO_VIOL 0x00000000 /* RWI-V */
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTBLIMIT_VIOL 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTOVRFLW 2:2 /* RWIVF */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTOVRFLW_NO_VIOL 0x00000000 /* RWI-V */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTOVRFLW_VIOL 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTMEMSIZE 3:3 /* RWIVF */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTMEMSIZE_NO_VIOL 0x00000000 /* RWI-V */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTMEMSIZE_VIOL 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTTILED 4:4 /* RWIVF */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTTILED_NO_VIOL 0x00000000 /* RWI-V */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_DSTTILED_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCBPITCH 8:8 /* RWIVF */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCBPITCH_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCBPITCH_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCBLIMIT 9:9 /* RWIVF */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCBLIMIT_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCBLIMIT_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCOVRFLW 10:10 /* RWIVF */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCOVRFLW_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCOVRFLW_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCMEMSIZE 11:11 /* RWIVF */
|
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#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCMEMSIZE_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCMEMSIZE_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCTILED 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCTILED_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SRCTILED_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SWIZZLEX 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SWIZZLEX_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SWIZZLEX_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SWIZZLEY 17:17 /* RWIVF */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SWIZZLEY_NO_VIOL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_SWIZZLEY_VIOL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_ZTILEMODE 21:20 /* RWIVF */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_CTILEMODE 23:22 /* RWIVF */
|
|
#define NV_PGRAPH_LIMIT_VIOL_MODE_ROPMODE 31:24 /* RWIVF */
|
|
#define NV_PGRAPH_STATE 0x00400714 /* RW-4R */
|
|
#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_BUFFER_0_042 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_0_058 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_0_062 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_BUFFER_1_042 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_1_059 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_1_062 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_BUFFER_2_056 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_2_05A 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_2_096 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_2_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_BUFFER_3_056 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_3_05B 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_3_096 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_3_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */
|
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#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_BUFFER_4_038 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_4_088 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */
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#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_BUFFER_5_052 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_BUFFER_5_09E 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */
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#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PITCH_0_042 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_0_058 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_0_062 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PITCH_1_042 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_1_059 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_1_062 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PITCH_2_056 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_2_05A 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_2_096 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_2_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PITCH_3_056 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_3_05B 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_3_096 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_3_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLOR_057 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_017 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */
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|
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_044 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_044 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_CPATTERN_SELECT_044 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR0_018 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PATTERN_COLOR1_018 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT0_018 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE_PATTERN_PATT1_018 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_DMA_PITCH 0x00400770 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */
|
|
#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */
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|
#define NV_PGRAPH_DVD_COLORFMT 0x00400774 /* RW-4R */
|
|
#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */
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|
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */
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|
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
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|
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
|
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#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */
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|
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */
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|
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8CR8CB8Y8 0x01 /* RW--V */
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|
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4CR6YB6A4CB6YA6 0x02 /* RW--V */
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#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */
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#define NV_PGRAPH_SCALED_FORMAT 0x00400778 /* RW-4R */
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#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */
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#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */
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#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */
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|
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */
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#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */
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#define NV_PGRAPH_STATE3D 0x0040077C /* RW-4R */
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#define NV_PGRAPH_STATE3D_CELSIUS_TAG_ID 15:0 /* RWIVF */
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#define NV_PGRAPH_STATE3D_CELSIUS_TAG_ID_0 0x00000000 /* RWI-V */
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#define NV_PGRAPH_STATE3D_CHANNEL_ID 20:16 /* RWIVF */
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|
#define NV_PGRAPH_STATE3D_CHANNEL_ID_0 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_STATE3D_CELSIUS_TAG_VALID 24:24 /* RWIVF */
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#define NV_PGRAPH_STATE3D_CELSIUS_TAG_VALID_FALSE 0x00000000 /* RWI-V */
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|
#define NV_PGRAPH_STATE3D_CELSIUS_TAG_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_STATE3D_CHANNEL_VALID 25:25 /* RWIVF */
|
|
#define NV_PGRAPH_STATE3D_CHANNEL_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_STATE3D_CHANNEL_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 /* RW-4R */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TABLE_INST 15:0 /* RWIVF */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TABLE_INST_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 /* RW-4R */
|
|
#define NV_PGRAPH_CHANNEL_CTX_POINTER_INST 15:0 /* RWIVF */
|
|
#define NV_PGRAPH_CHANNEL_CTX_POINTER_INST_0 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER 0x00400788 /* RW-4R */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN 0:0 /* CWIVF */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER_READ_IN_ACTIVATE 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT 1:1 /* CWIVF */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT_IGNORE 0x00000000 /* CWI-V */
|
|
#define NV_PGRAPH_CHANNEL_CTX_TRIGGER_WRITE_OUT_ACTIVATE 0x00000001 /* -W--T */
|
|
#define NV_PGRAPH_RDI_INDEX 0x00400750 /* RW-4R */
|
|
#define NV_PGRAPH_RDI_INDEX_ADDRESS 12:2 /* RWXVF */
|
|
#define NV_PGRAPH_RDI_INDEX_ADDRESS_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_RDI_INDEX_SELECT 24:16 /* RWXVF */
|
|
#define NV_PGRAPH_RDI_INDEX_SELECT_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_RDI_DATA 0x00400754 /* RW-4R */
|
|
#define NV_PGRAPH_RDI_DATA_VALUE 31:0 /* RWXVF */
|
|
#define NV_PGRAPH_RDI_DEBUG_DATA 0x00400758 /* RW-4R */
|
|
#define NV_PGRAPH_RDI_DEBUG_DATA_VALUE 31:0 /* RWXVF */
|
|
#define NV_PGRAPH_OGL_PERF 0x00400730 /* R--4R */
|
|
#define NV_PGRAPH_OGL_PERF_SMOOTHLINE 1:0 /* R-XVF */
|
|
#define NV_PGRAPH_OGL_PERF_SMOOTHLINE_1X 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_SMOOTHLINE_2X 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_SMOOTHLINE_4X 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_SMOOTHLINE_8X 0x00000003 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_POLYMODE 3:2 /* R-XVF */
|
|
#define NV_PGRAPH_OGL_PERF_POLYMODE_1X 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_POLYMODE_2X 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_POLYMODE_4X 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_POLYMODE_8X 0x00000003 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_TWOSIDEDLIGHT 5:4 /* R-XVF */
|
|
#define NV_PGRAPH_OGL_PERF_TWOSIDEDLIGHT_1X 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_TWOSIDEDLIGHT_2X 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_TWOSIDEDLIGHT_4X 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_OGL_PERF_TWOSIDEDLIGHT_8X 0x00000003 /* R---V */
|
|
#define NV_PGRAPH_PATT_COLOR0 0x00400b10 /* RW-4R */
|
|
#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_PATT_COLOR0_VALUE_018 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATT_COLOR0_VALUE_044 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATT_COLOR1 0x00400b14 /* RW-4R */
|
|
#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_PATT_COLOR1_VALUE_018 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATT_COLOR1_VALUE_044 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400a00+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */
|
|
#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* RWXUF */
|
|
#define NV_PGRAPH_PATT_COLORRAM_VALUE_044 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATTERN(i) (0x00400b18+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */
|
|
#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */
|
|
#define NV_PGRAPH_PATTERN_BITMAP_018 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATTERN_BITMAP_044 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE 0x00400b20 /* RW-4R */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_018 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_044 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_044 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_MONO_COLOR0 0x00400814 /* RW-4R */
|
|
#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_ROP3 0x00400b00 /* RW-4R */
|
|
#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */
|
|
#define NV_PGRAPH_ROP3_VALUE_043 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CHROMA 0x0040087c /* RW-4R */
|
|
#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_CHROMA_VALUE_017 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CHROMA_VALUE_057 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BETA_AND 0x00400b04 /* RW-4R */
|
|
#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */
|
|
#define NV_PGRAPH_BETA_AND_VALUE_FRACTION_012 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BETA_PREMULT 0x00400b08 /* RW-4R */
|
|
#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_BETA_PREMULT_VALUE_072 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STORED_FMT 0x00400b0c /* RW-4R */
|
|
#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */
|
|
#define NV_PGRAPH_STORED_FMT_MONO0_04A 0x0000000C /* RWC-V */
|
|
#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */
|
|
#define NV_PGRAPH_STORED_FMT_PATT0_044 0x0000000B /* RWC-V */
|
|
#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */
|
|
#define NV_PGRAPH_STORED_FMT_PATT1_044 0x0000000B /* RWC-V */
|
|
#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */
|
|
#define NV_PGRAPH_STORED_FMT_CHROMA_057 0x0000000B /* RWC-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT 0x00400888 /* RW-4R */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF0 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF0_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF0_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF1 1:1 /* RWXVF */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF1_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF1_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF2 2:2 /* RWXVF */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF2_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF2_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF3 3:3 /* RWXVF */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF3_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF3_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF4 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF4_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF4_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF5 5:5 /* RWXVF */
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|
#define NV_PGRAPH_PREROP_TILEBIT_BUF5_LINEAR 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_PREROP_TILEBIT_BUF5_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_FORMATS 0x00400804 /* R--4R */
|
|
#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */
|
|
#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* R---V */
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|
#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* R---V */
|
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#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */
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|
#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* R---V */
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|
#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* R---V */
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|
#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* R---V */
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|
#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* R---V */
|
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#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_AY8 0x00000015 /* R---V */
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|
#define NV_PGRAPH_FORMATS_SRC_LE_EYB8ECR8EYA8ECB8 0x00000016 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_SRC_LE_ECR8EYB8ECB8EYA8 0x00000017 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */
|
|
#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* R---V */
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|
#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* R---V */
|
|
#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* R---V */
|
|
#define NV_PGRAPH_FORMATS_ZB 19:18 /* R-XVF */
|
|
#define NV_PGRAPH_FORMATS_ZB_INVALID 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_ZB_Z16 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_FORMATS_ZB_Z24S8 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE 0x00400808 /* R--4R */
|
|
#define NV_PGRAPH_ROPMODE_CBYTES 1:0 /* R-XVF */
|
|
#define NV_PGRAPH_ROPMODE_CBYTES_1 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_CBYTES_2 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_CBYTES_4 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_ZBYTES 3:2 /* R-XVF */
|
|
#define NV_PGRAPH_ROPMODE_ZBYTES_1 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_ZBYTES_2 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_ZBYTES_4 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_SWIZZLE 4:4 /* R-XVF */
|
|
#define NV_PGRAPH_ROPMODE_SWIZZLE_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_SWIZZLE_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_PSEUDO 5:5 /* R-XVF */
|
|
#define NV_PGRAPH_ROPMODE_PSEUDO_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_PSEUDO_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_TYPE 7:6 /* R-XVF */
|
|
#define NV_PGRAPH_ROPMODE_TYPE_3D 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_TYPE_CLEAR 0x00000001 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_TYPE_2D 0x00000002 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_TYPE_BLT 0x00000003 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS 7:0 /* R-XVF */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z32_C32 0x0000000A /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z32_CPSEUDO32 0x0000002A /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z32_C16 0x00000009 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z32_C32_SWIZZLE 0x0000001A /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z16_C32 0x00000006 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z16_CPSEUDO32 0x00000026 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z16_C16 0x00000005 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z16_CPSEUDO32_SWIZZLE 0x00000036 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_Z16_C16_SWIZZLE 0x00000015 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_ZNULL_C8 0x00000000 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_ZNULL_C8_SWIZZLE 0x00000010 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2D32 0x0000008A /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2DPSEUDO32 0x000000A6 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2D16 0x00000085 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2D8 0x00000080 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2D32_SWIZZLE 0x0000009A /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2DPSEUDO32_SWIZZLE 0x000000B6 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2D16_SWIZZLE 0x00000095 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_2D8_SWIZZLE 0x00000090 /* R---V */
|
|
#define NV_PGRAPH_ROPMODE_BUS_CLEAR32 0x0000004A /* R---V */
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|
#define NV_PGRAPH_ROPMODE_BUS_CLEAR16 0x00000045 /* R---V */
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#define NV_PGRAPH_ROPMODE_BUS_BLT32 0x000000CA /* R---V */
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#define NV_PGRAPH_ROPMODE_BUS_BLT16 0x000000C5 /* R---V */
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|
#define NV_PGRAPH_ROPMODE_BUS_BLT8 0x000000C0 /* R---V */
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|
#define NV_PGRAPH_ROPMODE_ZTILEMODE 9:8 /* R-XVF */
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#define NV_PGRAPH_ROPMODE_ZTILEMODE_NULL 0x00000000 /* R---V */
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#define NV_PGRAPH_ROPMODE_ZTILEMODE_LINEAR 0x00000001 /* R---V */
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#define NV_PGRAPH_ROPMODE_ZTILEMODE_TILED 0x00000002 /* R---V */
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#define NV_PGRAPH_ROPMODE_CTILEMODE 11:10 /* R-XVF */
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#define NV_PGRAPH_ROPMODE_CTILEMODE_NULL 0x00000000 /* R---V */
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|
#define NV_PGRAPH_ROPMODE_CTILEMODE_LINEAR 0x00000001 /* R---V */
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#define NV_PGRAPH_ROPMODE_CTILEMODE_TILED 0x00000002 /* R---V */
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#define NV_PGRAPH_PROPSTATE 0x00400884 /* R--4R */
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#define NV_PGRAPH_PROPSTATE_VALUE 31:0 /* R-XVF */
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#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */
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#define NV_PGRAPH_ABS_X_RAM__SIZE_1 10 /* */
|
|
#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */
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#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 10 /* */
|
|
#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */
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#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */
|
|
#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 10 /* */
|
|
#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */
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|
#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 10 /* */
|
|
#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */
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#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */
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|
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_IMAGE_DATA_64 24:24 /* RWVVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_IMAGE_DATA_64_FALSE 0x00000000 /* RWV-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_IMAGE_DATA_64_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */
|
|
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */
|
|
#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */
|
|
#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */
|
|
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */
|
|
#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */
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#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */
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#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */
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#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */
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#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */
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#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */
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#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */
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#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE_019 0x00000000 /* RWC-V */
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#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE_019 0x00000000 /* RWC-V */
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#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE_019 0x00000000 /* RWC-V */
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#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE_019 0x00000000 /* RWC-V */
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#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE_MIN 0x00000000 /* RWN-V */
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#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE_MAX 0x0000ffff /* RWN-V */
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#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE_MIN 0x00000000 /* RWN-V */
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#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */
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#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */
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#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE_MAX 0x0000ffff /* RWN-V */
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#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */
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#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */
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#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */
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#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */
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#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */
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#define NV_PGRAPH_VALID1_VLD_NOCLIP (0x1<<19) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_SRCCOLOR (0x1<<16) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTMOVE (0x1<<21) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTX01 (0x3<<0) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTX02 (0x7<<0) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTX03 (0xf<<0) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTXCHAIN01 (0x3<<4) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTXCHAIN02 (0x7<<4) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTXCHAIN03 (0xf<<4) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTY01 (0x3<<8) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTY02 (0x7<<8) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTY03 (0xf<<8) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTYCHAIN01 (0x3<<12) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTYCHAIN02 (0x7<<12) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTYCHAIN03 (0xf<<12) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_X_OFFSET (0x1<<0) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_XCHAIN_OFFSET (0x1<<4) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_Y_OFFSET (0x1<<8) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_YCHAIN_OFFSET (0x1<<12) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTCOLOR0 (0x1<<17) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTCOLOR1 (0x1<<18) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTCLIP (0x1<<20) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTFONT (0x1<<22) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTOFFSET (0x1<<22) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTBPITCH (0x1<<2) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTBOFFSET (0x1<<3) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTDUDX (0x1<<4) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTDVDY (0x1<<5) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTPOINT (0x1<<8) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTSIZE (0x1<<9) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTPITCH (0x1<<10) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTSTART (0x1<<11) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTDUDX2 (0x1<<12) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTDVDY2 (0x1<<13) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTPOINT2 (0x1<<14) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTSIZE2 (0x1<<15) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTPITCH2 (0x1<<16) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTSTART2 (0x1<<17) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTOFFSIN (0x1<<0) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTOFFSOUT (0x1<<1) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTPITCHIN (0x1<<2) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTPITCHOUT (0x1<<3) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTLENGTH (0x1<<4) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTCOUNT (0x1<<5) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTFORMAT (0x1<<6) /* RW--V */
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#define NV_PGRAPH_VALID1_VLD_GOTNOTIFY (0x1<<7) /* RW--V */
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#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */
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#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */
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#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */
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#define NV_PGRAPH_VALID1_CLIP_MIN_019 0x00000000 /* RWC-V */
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#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */
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#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */
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#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */
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#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */
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#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */
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#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */
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#define NV_PGRAPH_VALID1_CLIP_MAX_019 0x00000000 /* RWC-V */
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#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */
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#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */
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#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */
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#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */
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#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */
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#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */
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#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */
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#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */
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#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */
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#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */
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#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */
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#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */
|
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#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */
|
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#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */
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|
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */
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|
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */
|
|
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */
|
|
#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */
|
|
#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */
|
|
#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */
|
|
#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */
|
|
#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */
|
|
#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */
|
|
#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */
|
|
#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */
|
|
#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DIMX_TEXTURE 0x00400588 /* RW-4R */
|
|
#define NV_PGRAPH_DIMX_TEXTURE_VALUE 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_WDIMX_TEXTURE 0x0040058c /* RW-4R */
|
|
#define NV_PGRAPH_WDIMX_TEXTURE_VALUE 16:0 /* RWXSF */
|
|
#define NV_PGRAPH_CLEAR 0x00000000 /* ---4P */
|
|
#define NV_PGRAPH_CLEAR_BUNDLE 0x000001FF /* ----B */
|
|
#define NV_PGRAPH_CLEAR_Z 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_CLEAR_Z_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_Z_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_STENCIL 1:1 /* RWXVF */
|
|
#define NV_PGRAPH_CLEAR_STENCIL_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_STENCIL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_R 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_CLEAR_R_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_R_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_G 5:5 /* RWXVF */
|
|
#define NV_PGRAPH_CLEAR_G_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_G_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_B 6:6 /* RWXVF */
|
|
#define NV_PGRAPH_CLEAR_B_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_B_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_A 7:7 /* RWXVF */
|
|
#define NV_PGRAPH_CLEAR_A_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CLEAR_A_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_PERFMONCLR 0x00000000 /* ---4P */
|
|
#define NV_PGRAPH_PERFMONCLR_BUNDLE 0x000001FD /* ----B */
|
|
#define NV_PGRAPH_PERFMONCLR_TYPE 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_PERFMONCLR_TYPE_ZPASS_PIXEL_CNT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_REPORT 0x00000000 /* ---4P */
|
|
#define NV_PGRAPH_REPORT_BUNDLE 0x000001FC /* ----B */
|
|
#define NV_PGRAPH_REPORT_OFFSET 23:0 /* RWXUF */
|
|
#define NV_PGRAPH_REPORT_TYPE 24:24 /* RWXVF */
|
|
#define NV_PGRAPH_REPORT_TYPE_ZPASS_PIXEL_CNT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TSEMAPHORERELEASE 0x00000000 /* ---4P */
|
|
#define NV_PGRAPH_TSEMAPHORERELEASE_BUNDLE 0x000001FB /* ----B */
|
|
#define NV_PGRAPH_TSEMAPHORERELEASE_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_TLPROGLAUNCH 0x00000000 /* ---4P */
|
|
#define NV_PGRAPH_TLPROGLAUNCH_BUNDLE 0x000001FA /* ----B */
|
|
#define NV_PGRAPH_TLPROGLAUNCH_V 6:0 /* RWXUF */
|
|
#define NV_PGRAPH_ANTIALIASING 0x00401800 /* RW-4R */
|
|
#define NV_PGRAPH_ANTIALIASING_BUNDLE 0x00000000 /* ----B */
|
|
#define NV_PGRAPH_ANTIALIASING_ENABLE 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_ANTIALIASING_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ANTIALIASING_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ANTIALIASING_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_COVERAGE 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_COVERAGE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_COVERAGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_COVERAGE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_ONE 8:8 /* RWXVF */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_ONE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_ONE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ANTIALIASING_ALPHA_TO_ONE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ANTIALIASING_SAMPLE_MASK 31:16 /* RWXUF */
|
|
#define NV_PGRAPH_ANTIALIASING_SAMPLE_MASK_097 0x0000FFFF /* RWC-V */
|
|
#define NV_PGRAPH_BLEND 0x00401804 /* RW-4R */
|
|
#define NV_PGRAPH_BLEND_BUNDLE 0x00000001 /* ----B */
|
|
#define NV_PGRAPH_BLEND_EN 3:3 /* RWXVF */
|
|
#define NV_PGRAPH_BLEND_EN_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EN_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BLEND_SFACTOR 7:4 /* RWXVF */
|
|
#define NV_PGRAPH_BLEND_SFACTOR_ZERO 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_SFACTOR_ONE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_SFACTOR_SRC_COLOR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_SRC_COLOR 0x00000003 /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_SRC_ALPHA 0x00000004 /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_SRC_ALPHA 0x00000005 /* RW--V */
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#define NV_PGRAPH_BLEND_SFACTOR_DST_ALPHA 0x00000006 /* RW--V */
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#define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_DST_ALPHA 0x00000007 /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_DST_COLOR 0x00000008 /* RW--V */
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#define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_DST_COLOR 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_SRC_ALPHA_SATURATE 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_CONSTANT_COLOR 0x0000000C /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_CONSTANT_COLOR 0x0000000D /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_CONSTANT_ALPHA 0x0000000E /* RW--V */
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#define NV_PGRAPH_BLEND_SFACTOR_ONE_MINUS_CONSTANT_ALPHA 0x0000000F /* RW--V */
|
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#define NV_PGRAPH_BLEND_SFACTOR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BLEND_DFACTOR 11:8 /* RWXVF */
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|
#define NV_PGRAPH_BLEND_DFACTOR_ZERO 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_DFACTOR_ONE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_SRC_COLOR 0x00000002 /* RW--V */
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#define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_SRC_COLOR 0x00000003 /* RW--V */
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#define NV_PGRAPH_BLEND_DFACTOR_SRC_ALPHA 0x00000004 /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_SRC_ALPHA 0x00000005 /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_DST_ALPHA 0x00000006 /* RW--V */
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#define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_DST_ALPHA 0x00000007 /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_DST_COLOR 0x00000008 /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_DST_COLOR 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_SRC_ALPHA_SATURATE 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_CONSTANT_COLOR 0x0000000C /* RW--V */
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#define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_CONSTANT_COLOR 0x0000000D /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_CONSTANT_ALPHA 0x0000000E /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_ONE_MINUS_CONSTANT_ALPHA 0x0000000F /* RW--V */
|
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#define NV_PGRAPH_BLEND_DFACTOR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BLEND_EQN 2:0 /* RWXVF */
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|
#define NV_PGRAPH_BLEND_EQN_FUNC_SUBTRACT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EQN_FUNC_REVERSE_SUBTRACT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EQN_FUNC_ADD 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_BLEND_EQN_MIN 0x00000003 /* RW--V */
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#define NV_PGRAPH_BLEND_EQN_MAX 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EQN_FUNC_REVERSE_SUBTRACT_SIGNED 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EQN_FUNC_ADD_SIGNED 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_EQN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_ENABLE 16:16 /* RWXVF */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP 15:12 /* RWXVF */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_AND 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_AND_REVERSE 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_COPY 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_AND_INVERTED 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_NOOP 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_XOR 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_OR 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_NOR 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_EQUIV 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_INVERT 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_OR_REVERSE 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_COPY_INVERTED 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_OR_INVERTED 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_NAND 0x0000000E /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_SET 0x0000000F /* RW--V */
|
|
#define NV_PGRAPH_BLEND_LOGICOP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BLENDCOLOR 0x00401808 /* RW-4R */
|
|
#define NV_PGRAPH_BLENDCOLOR_BUNDLE 0x00000002 /* ----B */
|
|
#define NV_PGRAPH_BLENDCOLOR_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_BLENDCOLOR_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BORDERCOLOR0 0x0040180C /* RW-4R */
|
|
#define NV_PGRAPH_BORDERCOLOR0_BUNDLE 0x00000003 /* ----B */
|
|
#define NV_PGRAPH_BORDERCOLOR0_BORDER_COLOR 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_BORDERCOLOR0_BORDER_COLOR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BORDERCOLOR1 0x00401810 /* RW-4R */
|
|
#define NV_PGRAPH_BORDERCOLOR1_BUNDLE 0x00000004 /* ----B */
|
|
#define NV_PGRAPH_BORDERCOLOR1_BORDER_COLOR 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_BORDERCOLOR1_BORDER_COLOR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BORDERCOLOR2 0x00401814 /* RW-4R */
|
|
#define NV_PGRAPH_BORDERCOLOR2_BUNDLE 0x00000005 /* ----B */
|
|
#define NV_PGRAPH_BORDERCOLOR2_BORDER_COLOR 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_BORDERCOLOR2_BORDER_COLOR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BORDERCOLOR3 0x00401818 /* RW-4R */
|
|
#define NV_PGRAPH_BORDERCOLOR3_BUNDLE 0x00000006 /* ----B */
|
|
#define NV_PGRAPH_BORDERCOLOR3_BORDER_COLOR 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_BORDERCOLOR3_BORDER_COLOR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPMAT00_1 0x0040181C /* RW-4R */
|
|
#define NV_PGRAPH_BUMPMAT00_1_BUNDLE 0x00000007 /* ----B */
|
|
#define NV_PGRAPH_BUMPMAT00_1_BUMPMAT00 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPMAT00_1_BUMPMAT00_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPMAT00_2 0x00401820 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPMAT00_2_BUNDLE 0x00000008 /* ----B */
|
|
#define NV_PGRAPH_BUMPMAT00_2_BUMPMAT00 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPMAT00_2_BUMPMAT00_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPMAT00_3 0x00401824 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPMAT00_3_BUNDLE 0x00000009 /* ----B */
|
|
#define NV_PGRAPH_BUMPMAT00_3_BUMPMAT00 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPMAT00_3_BUMPMAT00_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPMAT01_1 0x00401828 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPMAT01_1_BUNDLE 0x0000000A /* ----B */
|
|
#define NV_PGRAPH_BUMPMAT01_1_BUMPMAT01 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPMAT01_1_BUMPMAT01_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPMAT01_2 0x0040182C /* RW-4R */
|
|
#define NV_PGRAPH_BUMPMAT01_2_BUNDLE 0x0000000B /* ----B */
|
|
#define NV_PGRAPH_BUMPMAT01_2_BUMPMAT01 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT01_2_BUMPMAT01_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPMAT01_3 0x00401830 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPMAT01_3_BUNDLE 0x0000000C /* ----B */
|
|
#define NV_PGRAPH_BUMPMAT01_3_BUMPMAT01 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT01_3_BUMPMAT01_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPMAT10_1 0x00401834 /* RW-4R */
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|
#define NV_PGRAPH_BUMPMAT10_1_BUNDLE 0x0000000D /* ----B */
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|
#define NV_PGRAPH_BUMPMAT10_1_BUMPMAT10 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT10_1_BUMPMAT10_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPMAT10_2 0x00401838 /* RW-4R */
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|
#define NV_PGRAPH_BUMPMAT10_2_BUNDLE 0x0000000E /* ----B */
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|
#define NV_PGRAPH_BUMPMAT10_2_BUMPMAT10 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT10_2_BUMPMAT10_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPMAT10_3 0x0040183C /* RW-4R */
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#define NV_PGRAPH_BUMPMAT10_3_BUNDLE 0x0000000F /* ----B */
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|
#define NV_PGRAPH_BUMPMAT10_3_BUMPMAT10 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT10_3_BUMPMAT10_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPMAT11_1 0x00401840 /* RW-4R */
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|
#define NV_PGRAPH_BUMPMAT11_1_BUNDLE 0x00000010 /* ----B */
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|
#define NV_PGRAPH_BUMPMAT11_1_BUMPMAT11 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT11_1_BUMPMAT11_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPMAT11_2 0x00401844 /* RW-4R */
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|
#define NV_PGRAPH_BUMPMAT11_2_BUNDLE 0x00000011 /* ----B */
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|
#define NV_PGRAPH_BUMPMAT11_2_BUMPMAT11 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT11_2_BUMPMAT11_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPMAT11_3 0x00401848 /* RW-4R */
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|
#define NV_PGRAPH_BUMPMAT11_3_BUNDLE 0x00000012 /* ----B */
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|
#define NV_PGRAPH_BUMPMAT11_3_BUMPMAT11 31:0 /* RWXFF */
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|
#define NV_PGRAPH_BUMPMAT11_3_BUMPMAT11_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_BUMPOFFSET1 0x0040184C /* RW-4R */
|
|
#define NV_PGRAPH_BUMPOFFSET1_BUNDLE 0x00000013 /* ----B */
|
|
#define NV_PGRAPH_BUMPOFFSET1_BUMPOFFSET 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPOFFSET1_BUMPOFFSET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPOFFSET2 0x00401850 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPOFFSET2_BUNDLE 0x00000014 /* ----B */
|
|
#define NV_PGRAPH_BUMPOFFSET2_BUMPOFFSET 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPOFFSET2_BUMPOFFSET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPOFFSET3 0x00401854 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPOFFSET3_BUNDLE 0x00000015 /* ----B */
|
|
#define NV_PGRAPH_BUMPOFFSET3_BUMPOFFSET 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPOFFSET3_BUMPOFFSET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPSCALE1 0x00401858 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPSCALE1_BUNDLE 0x00000016 /* ----B */
|
|
#define NV_PGRAPH_BUMPSCALE1_BUMPSCALE 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPSCALE1_BUMPSCALE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPSCALE2 0x0040185C /* RW-4R */
|
|
#define NV_PGRAPH_BUMPSCALE2_BUNDLE 0x00000017 /* ----B */
|
|
#define NV_PGRAPH_BUMPSCALE2_BUMPSCALE 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPSCALE2_BUMPSCALE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BUMPSCALE3 0x00401860 /* RW-4R */
|
|
#define NV_PGRAPH_BUMPSCALE3_BUNDLE 0x00000018 /* ----B */
|
|
#define NV_PGRAPH_BUMPSCALE3_BUMPSCALE 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_BUMPSCALE3_BUMPSCALE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CLEARRECTX 0x00401864 /* RW-4R */
|
|
#define NV_PGRAPH_CLEARRECTX_BUNDLE 0x00000019 /* ----B */
|
|
#define NV_PGRAPH_CLEARRECTX_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_CLEARRECTX_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CLEARRECTX_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_CLEARRECTX_XMAX_097 0x00000FFF /* RWC-V */
|
|
#define NV_PGRAPH_CLEARRECTY 0x00401868 /* RW-4R */
|
|
#define NV_PGRAPH_CLEARRECTY_BUNDLE 0x0000001A /* ----B */
|
|
#define NV_PGRAPH_CLEARRECTY_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_CLEARRECTY_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CLEARRECTY_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_CLEARRECTY_YMAX_097 0x00000FFF /* RWC-V */
|
|
#define NV_PGRAPH_COLORCLEARVALUE 0x0040186C /* RW-4R */
|
|
#define NV_PGRAPH_COLORCLEARVALUE_BUNDLE 0x0000001B /* ----B */
|
|
#define NV_PGRAPH_COLORCLEARVALUE_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_COLORCLEARVALUE_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COLORKEYCOLOR0 0x00401870 /* RW-4R */
|
|
#define NV_PGRAPH_COLORKEYCOLOR0_BUNDLE 0x0000001C /* ----B */
|
|
#define NV_PGRAPH_COLORKEYCOLOR0_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_COLORKEYCOLOR0_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COLORKEYCOLOR1 0x00401874 /* RW-4R */
|
|
#define NV_PGRAPH_COLORKEYCOLOR1_BUNDLE 0x0000001D /* ----B */
|
|
#define NV_PGRAPH_COLORKEYCOLOR1_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_COLORKEYCOLOR1_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COLORKEYCOLOR2 0x00401878 /* RW-4R */
|
|
#define NV_PGRAPH_COLORKEYCOLOR2_BUNDLE 0x0000001E /* ----B */
|
|
#define NV_PGRAPH_COLORKEYCOLOR2_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_COLORKEYCOLOR2_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COLORKEYCOLOR3 0x0040187C /* RW-4R */
|
|
#define NV_PGRAPH_COLORKEYCOLOR3_BUNDLE 0x0000001F /* ----B */
|
|
#define NV_PGRAPH_COLORKEYCOLOR3_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_COLORKEYCOLOR3_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0 0x00401880 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_BUNDLE 0x00000020 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_0_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1 0x00401884 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_BUNDLE 0x00000021 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_1_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2 0x00401888 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_BUNDLE 0x00000022 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_2_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3 0x0040188C /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_BUNDLE 0x00000023 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_3_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4 0x00401890 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_BUNDLE 0x00000024 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_4_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5 0x00401894 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_BUNDLE 0x00000025 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_5_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6 0x00401898 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_BUNDLE 0x00000026 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_6_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7 0x0040189C /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_BUNDLE 0x00000027 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR0_7_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0 0x004018A0 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_BUNDLE 0x00000028 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_0_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1 0x004018A4 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_BUNDLE 0x00000029 /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_1_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2 0x004018A8 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_BUNDLE 0x0000002A /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_2_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3 0x004018AC /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_BUNDLE 0x0000002B /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_3_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4 0x004018B0 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_BUNDLE 0x0000002C /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_4_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5 0x004018B4 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_BUNDLE 0x0000002D /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_GREEN 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_5_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_6 0x004018B8 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_6_BUNDLE 0x0000002E /* ----B */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_6_BLUE 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_6_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_6_GREEN 15:8 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_6_GREEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_6_RED 23:16 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_6_RED_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINEFACTOR1_6_ALPHA 31:24 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_6_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7 0x004018BC /* RW-4R */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_BUNDLE 0x0000002F /* ----B */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_BLUE 7:0 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_BLUE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_GREEN 15:8 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_GREEN_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_RED 23:16 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEFACTOR1_7_ALPHA 31:24 /* RWXUF */
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|
#define NV_PGRAPH_COMBINEFACTOR1_7_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINEALPHAI0 0x004018C0 /* RW-4R */
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|
#define NV_PGRAPH_COMBINEALPHAI0_BUNDLE 0x00000030 /* ----B */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP 31:29 /* RWXVF */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_AMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_A_ALPHA 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_A_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_ASOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP 23:21 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_B_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_BSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_C_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_CSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP 7:5 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI0_DMAP_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_COMBINEALPHAI0_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI0_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI0_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1 0x004018C4 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAI1_BUNDLE 0x00000031 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI1_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2 0x004018C8 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAI2_BUNDLE 0x00000032 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI2_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3 0x004018CC /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAI3_BUNDLE 0x00000033 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI3_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4 0x004018D0 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAI4_BUNDLE 0x00000034 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI4_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5 0x004018D4 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAI5_BUNDLE 0x00000035 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI5_DSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINEALPHAI6 0x004018D8 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_BUNDLE 0x00000036 /* ----B */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_AMAP 31:29 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI6_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI6_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI6_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI6_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_AMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_A_ALPHA 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_A_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_A 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_B 0x0000000B /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI6_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7 0x004018DC /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAI7_BUNDLE 0x00000037 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_CSOURCE_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_COMBINEALPHAI7_DMAP 7:5 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI7_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI7_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAI7_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_D_ALPHA 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_D_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_D_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_D_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE 3:0 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_0 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_1 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_2 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINEALPHAI7_DSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINEALPHAO0 0x004018E0 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINEALPHAO0_BUNDLE 0x00000038 /* ----B */
|
|
#define NV_PGRAPH_COMBINEALPHAO0_OP 17:15 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINEALPHAO0_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO0_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO0_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO0_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO1 0x004018E4 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO1_BUNDLE 0x00000039 /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO1_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO1_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO1_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO1_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO2 0x004018E8 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO2_BUNDLE 0x0000003A /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO2_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO2_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO2_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO2_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO3 0x004018EC /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO3_BUNDLE 0x0000003B /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO3_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO3_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO3_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO3_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO4 0x004018F0 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO4_BUNDLE 0x0000003C /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO4_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO4_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO4_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO4_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO5 0x004018F4 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO5_BUNDLE 0x0000003D /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO5_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO5_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO5_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO5_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO6 0x004018F8 /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO6_BUNDLE 0x0000003E /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO6_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO6_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO6_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO6_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO7 0x004018FC /* RW-4R */
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#define NV_PGRAPH_COMBINEALPHAO7_BUNDLE 0x0000003F /* ----B */
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#define NV_PGRAPH_COMBINEALPHAO7_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO7_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO7_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINEALPHAO7_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI0 0x00401900 /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORI0_BUNDLE 0x00000040 /* ----B */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_AMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI0_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI0_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_8 0x00000008 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_9 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_A 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_B 0x0000000B /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_C 0x0000000C /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_ASOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP 23:21 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_B_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_B 0x0000000B /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_C 0x0000000C /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_BSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CMAP 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_C_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_9 0x00000009 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_CSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP 7:5 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_D_ALPHA 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_D_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_D_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_D_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE 3:0 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_1 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_9 0x00000009 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_B 0x0000000B /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI0_DSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI1 0x00401904 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINECOLORI1_BUNDLE 0x00000041 /* ----B */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP 31:29 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_AMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI1_A_ALPHA 28:28 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI1_A_ALPHA_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_A_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI1_ASOURCE 27:24 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI1_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI1_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI1_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI1_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_C_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI1_CSOURCE 11:8 /* RWXVF */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_0 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_2 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_8 0x00000008 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_9 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_A 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_B 0x0000000B /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_CSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP 7:5 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_D_ALPHA 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI1_D_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_D_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_D_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE 3:0 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI1_DSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI2 0x00401908 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINECOLORI2_BUNDLE 0x00000042 /* ----B */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP 31:29 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_AMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_A_ALPHA 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI2_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_A_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_1 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_3 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_REG_D 0x0000000D /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_ASOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_BMAP 23:21 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_B_ALPHA 20:20 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_B_ALPHA_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_B_ALPHA_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_B_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_BSOURCE 19:16 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_REG_D 0x0000000D /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_BSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_CMAP 15:13 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI2_C_ALPHA_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_C_ALPHA_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_C_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_CSOURCE 11:8 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_8 0x00000008 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_A 0x0000000A /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP 7:5 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI2_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI2_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI2_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE 3:0 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI2_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3 0x0040190C /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORI3_BUNDLE 0x00000043 /* ----B */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_AMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BMAP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3_B_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_B_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_B_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_B_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_BSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP 15:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI3_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI3_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_C_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_CSOURCE 11:8 /* RWXVF */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_1 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_2 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_3 0x00000003 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_4 0x00000004 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_5 0x00000005 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_8 0x00000008 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_9 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_CSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP 7:5 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_D_ALPHA 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI3_D_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_D_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_D_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE 3:0 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI3_DSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI4 0x00401910 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BUNDLE 0x00000044 /* ----B */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP 31:29 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_AMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_A_ALPHA 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_A_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_3 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_8 0x00000008 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_9 0x00000009 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_A 0x0000000A /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_B 0x0000000B /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_C 0x0000000C /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_ASOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BMAP 23:21 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_B_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_3 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_BSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CMAP 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI4_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_C_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_3 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_8 0x00000008 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_C 0x0000000C /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_REG_D 0x0000000D /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_CSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP 7:5 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI4_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI4_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI4_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI4_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI5 0x00401914 /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORI5_BUNDLE 0x00000045 /* ----B */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP 31:29 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_AMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI5_A_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI5_A_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_A_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_A_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI5_ASOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_ASOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI5_BMAP 23:21 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI5_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI5_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI5_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI5_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI5_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI5_BMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_B_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_1 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_BSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_C_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_CSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP 7:5 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_D_ALPHA 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_D_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_D_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_D_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE 3:0 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI5_DSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6 0x00401918 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BUNDLE 0x00000046 /* ----B */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP 31:29 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_AMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_A_ALPHA 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_A_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_ASOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP 23:21 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_B_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_BSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_C_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_3 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_4 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_5 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_8 0x00000008 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_9 0x00000009 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_A 0x0000000A /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_B 0x0000000B /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_C 0x0000000C /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_REG_D 0x0000000D /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_CSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP 7:5 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI6_D_ALPHA 4:4 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI6_D_ALPHA_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_D_ALPHA_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_D_ALPHA_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DSOURCE 3:0 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_0 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI6_DSOURCE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI7 0x0040191C /* RW-4R */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BUNDLE 0x00000047 /* ----B */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP 31:29 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_AMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_A_ALPHA 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_A_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_ASOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP 23:21 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_B_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_BSOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CMAP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_C_ALPHA 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_C_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_C_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_C_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CSOURCE 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_CSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP 7:5 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_UNSIGNED_IDENTITY 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_UNSIGNED_INVERT 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_EXPAND_NORMAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_EXPAND_NEGATE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_HALFBIAS_NORMAL 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_HALFBIAS_NEGATE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_SIGNED_IDENTITY 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_SIGNED_NEGATE 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DMAP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORI7_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI7_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORI7_DSOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO0 0x00401920 /* RW-4R */
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|
#define NV_PGRAPH_COMBINECOLORO0_BUNDLE 0x00000048 /* ----B */
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|
#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_AB 19:19 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_AB_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO0_OP 17:15 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORO0_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_OP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO0_MUX_ENABLE 14:14 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORO0_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_MUX_ENABLE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO0_AB_DOT_ENABLE 13:13 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORO0_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO0_CD_DOT_ENABLE 12:12 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORO0_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO0_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO0_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO0_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1 0x00401924 /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORO1_BUNDLE 0x00000049 /* ----B */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_AB 19:19 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_AB_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DOT_ENABLE 13:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DOT_ENABLE 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_AB_DST_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO1_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_B 0x0000000B /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_C 0x0000000C /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO1_CD_DST_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO1_CD_DST_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2 0x00401928 /* RW-4R */
|
|
#define NV_PGRAPH_COMBINECOLORO2_BUNDLE 0x0000004A /* ----B */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_AB 19:19 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_AB_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_CD 18:18 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_B_TO_A_CD_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP 17:15 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_NOSHIFT 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_OP_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_MUX_ENABLE 14:14 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_MUX_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_AB_DOT_ENABLE 13:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_CD_DOT_ENABLE 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST 11:8 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_SUM_DST_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO2_AB_DST 7:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO2_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3 0x0040192C /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORO3_BUNDLE 0x0000004B /* ----B */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_AB 19:19 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_AB_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DOT_ENABLE 13:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DOT_ENABLE 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO3_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4 0x00401930 /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORO4_BUNDLE 0x0000004C /* ----B */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_AB 19:19 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_AB_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DOT_ENABLE 13:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DOT_ENABLE 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO4_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO5 0x00401934 /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORO5_BUNDLE 0x0000004D /* ----B */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_AB 19:19 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_AB_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO5_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO5_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_OP_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_COMBINECOLORO5_MUX_ENABLE 14:14 /* RWXVF */
|
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#define NV_PGRAPH_COMBINECOLORO5_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_MUX_ENABLE_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_COMBINECOLORO5_AB_DOT_ENABLE 13:13 /* RWXVF */
|
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#define NV_PGRAPH_COMBINECOLORO5_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DOT_ENABLE 12:12 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_COMBINECOLORO5_SUM_DST 11:8 /* RWXVF */
|
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#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_0 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_9 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_SUM_DST_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST 7:4 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_4 0x00000004 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_AB_DST_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DST 3:0 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_9 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO5_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6 0x00401938 /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORO6_BUNDLE 0x0000004E /* ----B */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_AB 19:19 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_AB_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DOT_ENABLE 13:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DOT_ENABLE 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO6_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7 0x0040193C /* RW-4R */
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#define NV_PGRAPH_COMBINECOLORO7_BUNDLE 0x0000004F /* ----B */
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|
#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_AB 19:19 /* RWXVF */
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|
#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_AB_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_AB_AB_DST_ENABLE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_AB_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_CD 18:18 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_CD_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_CD_CD_DST_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_B_TO_A_CD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7_OP 17:15 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_OP_NOSHIFT 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_OP_NOSHIFT_BIAS 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_OP_SHIFTLEFTBY1 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_OP_SHIFTLEFTBY2 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_OP_SHIFTRIGHTBY1 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_OP_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINECOLORO7_MUX_ENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_MUX_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_MUX_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_MUX_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DOT_ENABLE 13:13 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DOT_ENABLE 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DOT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DOT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DOT_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_SUM_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST 7:4 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_AB_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINECOLORO7_CD_DST_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECTL 0x00401940 /* RW-4R */
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#define NV_PGRAPH_COMBINECTL_BUNDLE 0x00000050 /* ----B */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_ONE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_TWO 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_THREE 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_FOUR 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_FIVE 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_SIX 0x00000006 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_SEVEN 0x00000007 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_EIGHT 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_ITERATION_COUNT_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_COMBINECTL_MUX_SELECT 8:8 /* RWXVF */
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#define NV_PGRAPH_COMBINECTL_MUX_SELECT_LSB 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_MUX_SELECT_MSB 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_MUX_SELECT_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_COMBINECTL_FACTOR0 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINECTL_FACTOR0_SAME_FACTOR_ALL 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_FACTOR0_EACH_STAGE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_FACTOR0_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINECTL_FACTOR1 16:16 /* RWXVF */
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#define NV_PGRAPH_COMBINECTL_FACTOR1_SAME_FACTOR_ALL 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINECTL_FACTOR1_EACH_STAGE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINECTL_FACTOR1_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_COMBINESPECFOG0 0x00401944 /* RW-4R */
|
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#define NV_PGRAPH_COMBINESPECFOG0_BUNDLE 0x00000051 /* ----B */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_A_INVERSE 29:29 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG0_A_INVERSE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_INVERSE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_INVERSE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_ALPHA 28:28 /* RWXVF */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_ALPHA_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_ALPHA_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE 27:24 /* RWXVF */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_1 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_5 0x00000005 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_8 0x00000008 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_9 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_A 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_B 0x0000000B /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_C 0x0000000C /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_D 0x0000000D /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_SPECLIT 0x0000000E /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_REG_EF_PROD 0x0000000F /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_A_SOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_INVERSE 21:21 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_INVERSE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_INVERSE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_INVERSE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_ALPHA 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_ALPHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_ALPHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_ALPHA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE 19:16 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_0 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_1 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_2 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_3 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_4 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_5 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_8 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_9 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_A 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_B 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_C 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_D 0x0000000D /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_SPECLIT 0x0000000E /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_REG_EF_PROD 0x0000000F /* RW--V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_B_SOURCE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_C_INVERSE 13:13 /* RWXVF */
|
|
#define NV_PGRAPH_COMBINESPECFOG0_C_INVERSE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_COMBINESPECFOG0_C_INVERSE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_INVERSE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG0_C_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_SPECLIT 0x0000000E /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_REG_EF_PROD 0x0000000F /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_C_SOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_INVERSE 5:5 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG0_D_INVERSE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_INVERSE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_INVERSE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_ALPHA 4:4 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG0_D_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE 3:0 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_SPECLIT 0x0000000E /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_REG_EF_PROD 0x0000000F /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG0_D_SOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1 0x00401948 /* RW-4R */
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#define NV_PGRAPH_COMBINESPECFOG1_BUNDLE 0x00000052 /* ----B */
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#define NV_PGRAPH_COMBINESPECFOG1_E_INVERSE 29:29 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_E_INVERSE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_INVERSE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_INVERSE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_ALPHA 28:28 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_E_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE 27:24 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_E_SOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_INVERSE 21:21 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_F_INVERSE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_INVERSE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_INVERSE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_ALPHA 20:20 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_F_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE 19:16 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_F_SOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_INVERSE 13:13 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_G_INVERSE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_INVERSE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_INVERSE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_ALPHA 12:12 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_G_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE 11:8 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_4 0x00000004 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_5 0x00000005 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_8 0x00000008 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_9 0x00000009 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_A 0x0000000A /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_B 0x0000000B /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_C 0x0000000C /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_REG_D 0x0000000D /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_G_SOURCE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECULAR_CLAMP 7:7 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECULAR_CLAMP_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECULAR_CLAMP_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECULAR_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR5 6:6 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR5_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR5_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR5_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR12 5:5 /* RWXVF */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR12_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR12_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_COMBINESPECFOG1_SPECADDINVR12_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0 0x0040194C /* RW-4R */
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#define NV_PGRAPH_CONTROL_0_BUNDLE 0x00000053 /* ----B */
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#define NV_PGRAPH_CONTROL_0_CSCONVERT 31:30 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_CSCONVERT_PASS 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_CSCONVERT_CRYCB_TO_RGB 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_CSCONVERT_SCRYSCB_TO_RGB 0x00000002 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_CSCONVERT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_Z_PERSPECTIVE_ENABLE 23:23 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_Z_PERSPECTIVE_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE 25:25 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_STENCIL_WRITE_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_ALPHATESTENABLE 12:12 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_ALPHATESTENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHATESTENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHATESTENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_ZENABLE 14:14 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_ZENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_DITHERENABLE 22:22 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_DITHERENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_DITHERENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_DITHERENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC 11:8 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_NEVER 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_LESS 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_EQUAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_LEQUAL 0x00000003 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_GREATER 0x00000004 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_NOTEQUAL 0x00000005 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_GEQUAL 0x00000006 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_ALWAYS 0x00000007 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHAFUNC_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_ALPHAREF 7:0 /* RWXUF */
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#define NV_PGRAPH_CONTROL_0_ALPHAREF_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC 19:16 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_NEVER 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_LESS 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_EQUAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_LEQUAL 0x00000003 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_GREATER 0x00000004 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_NOTEQUAL 0x00000005 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_GEQUAL 0x00000006 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_ALWAYS 0x00000007 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ZFUNC_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_0_ALPHA_WRITE_ENABLE 26:26 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_ALPHA_WRITE_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHA_WRITE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_ALPHA_WRITE_ENABLE_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_CONTROL_0_RED_WRITE_ENABLE 27:27 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_RED_WRITE_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_RED_WRITE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_0_RED_WRITE_ENABLE_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_CONTROL_0_GREEN_WRITE_ENABLE 28:28 /* RWXVF */
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#define NV_PGRAPH_CONTROL_0_GREEN_WRITE_ENABLE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_CONTROL_0_GREEN_WRITE_ENABLE_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_CONTROL_0_GREEN_WRITE_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTROL_0_BLUE_WRITE_ENABLE 29:29 /* RWXVF */
|
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#define NV_PGRAPH_CONTROL_0_BLUE_WRITE_ENABLE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_CONTROL_0_BLUE_WRITE_ENABLE_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_CONTROL_0_BLUE_WRITE_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTROL_0_ZWRITEENABLE 24:24 /* RWXVF */
|
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#define NV_PGRAPH_CONTROL_0_ZWRITEENABLE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_CONTROL_0_ZWRITEENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_0_ZWRITEENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTROL_1 0x00401950 /* RW-4R */
|
|
#define NV_PGRAPH_CONTROL_1_BUNDLE 0x00000054 /* ----B */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_TEST_ENABLE 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_TEST_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_TEST_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_TEST_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_MASK_WRITE 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_MASK_WRITE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC 7:4 /* RWXVF */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_NEVER 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_LESS 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_EQUAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_LEQUAL 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_GREATER 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_NOTEQUAL 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_GEQUAL 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_ALWAYS 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_FUNC_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTROL_1_STENCIL_REF 15:8 /* RWXUF */
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#define NV_PGRAPH_CONTROL_1_STENCIL_REF_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_1_STENCIL_MASK_READ 23:16 /* RWXUF */
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#define NV_PGRAPH_CONTROL_1_STENCIL_MASK_READ_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_2 0x00401954 /* RW-4R */
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#define NV_PGRAPH_CONTROL_2_BUNDLE 0x00000055 /* ----B */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL 3:0 /* RWXVF */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_KEEP 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_ZERO 0x00000002 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_REPLACE 0x00000003 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_INCRSAT 0x00000004 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_DECRSAT 0x00000005 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_INVERT 0x00000006 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_INCR 0x00000007 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_DECR 0x00000008 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_FAIL_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL 7:4 /* RWXVF */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_KEEP 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_ZERO 0x00000002 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_REPLACE 0x00000003 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_INCRSAT 0x00000004 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_DECRSAT 0x00000005 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_INVERT 0x00000006 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_INCR 0x00000007 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_DECR 0x00000008 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZFAIL_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS 11:8 /* RWXVF */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_KEEP 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_ZERO 0x00000002 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_REPLACE 0x00000003 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_INCRSAT 0x00000004 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_DECRSAT 0x00000005 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_INVERT 0x00000006 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_INCR 0x00000007 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_DECR 0x00000008 /* RW--V */
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#define NV_PGRAPH_CONTROL_2_STENCIL_OP_ZPASS_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3 0x00401958 /* RW-4R */
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#define NV_PGRAPH_CONTROL_3_BUNDLE 0x00000056 /* ----B */
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#define NV_PGRAPH_CONTROL_3_PREMULTALPHA 2:2 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_PREMULTALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_PREMULTALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_PREMULTALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_TEXTUREPERSPECTIVE 6:6 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_TEXTUREPERSPECTIVE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_WBUFFER_SELECT 13:10 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_WBUFFER_SELECT_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_WBUFFER_SELECT_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_WBUFFER_SELECT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE 18:16 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_LINEAR 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP2 0x00000003 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP_ABS 0x00000005 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_EXP2_ABS 0x00000007 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_LINEAR_ABS 0x00000004 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOG_MODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_FOGENABLE 8:8 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_FOGENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOGENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FOGENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_POINTPARAMSENABLE 9:9 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_POINTPARAMSENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_POINTPARAMSENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_POINTPARAMSENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_SHADEMODE 7:7 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_SHADEMODE_FLAT 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_SHADEMODE_SMOOTH 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_SHADEMODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_SPECULARENABLE 5:5 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_SPECULARENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_SPECULARENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_SPECULARENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_FLATSHADE_OP 0:0 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_FLATSHADE_OP_LAST_VTX 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FLATSHADE_OP_FIRST_VTX 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_FLATSHADE_OP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CONTROL_3_ZP 20:20 /* RWXVF */
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#define NV_PGRAPH_CONTROL_3_ZP_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_ZP_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CONTROL_3_ZP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FOGCOLOR 0x00401980 /* RW-4R */
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#define NV_PGRAPH_FOGCOLOR_BUNDLE 0x00000060 /* ----B */
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#define NV_PGRAPH_FOGCOLOR_RED 23:16 /* RWXUF */
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#define NV_PGRAPH_FOGCOLOR_RED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FOGCOLOR_GREEN 15:8 /* RWXUF */
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#define NV_PGRAPH_FOGCOLOR_GREEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FOGCOLOR_BLUE 7:0 /* RWXUF */
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#define NV_PGRAPH_FOGCOLOR_BLUE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FOGCOLOR_ALPHA 31:24 /* RWXUF */
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#define NV_PGRAPH_FOGCOLOR_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FOGPARAM0 0x00401984 /* RW-4R */
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#define NV_PGRAPH_FOGPARAM0_BUNDLE 0x00000061 /* ----B */
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#define NV_PGRAPH_FOGPARAM0_V 31:0 /* RWXFF */
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#define NV_PGRAPH_FOGPARAM0_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FOGPARAM1 0x00401988 /* RW-4R */
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#define NV_PGRAPH_FOGPARAM1_BUNDLE 0x00000062 /* ----B */
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#define NV_PGRAPH_FOGPARAM1_V 31:0 /* RWXFF */
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#define NV_PGRAPH_FOGPARAM1_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_POINTSIZE 0x0040198C /* RW-4R */
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#define NV_PGRAPH_POINTSIZE_BUNDLE 0x00000063 /* ----B */
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#define NV_PGRAPH_POINTSIZE_V 8:0 /* RWXUF */
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#define NV_PGRAPH_POINTSIZE_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER 0x00401990 /* RW-4R */
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#define NV_PGRAPH_SETUPRASTER_BUNDLE 0x00000064 /* ----B */
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#define NV_PGRAPH_SETUPRASTER_Z_FORMAT 29:29 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_Z_FORMAT_FIXED 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_Z_FORMAT_FLOAT 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_Z_FORMAT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE 31:31 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE_INCLUSIVE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE_EXCLUSIVE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_WINDOWCLIPTYPE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_CULLENABLE 28:28 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_CULLENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULLENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULLENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_POINTSMOOTHENABLE 9:9 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_POINTSMOOTHENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POINTSMOOTHENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POINTSMOOTHENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_LINESMOOTHENABLE 10:10 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_LINESMOOTHENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_LINESMOOTHENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_LINESMOOTHENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_POLYSMOOTHENABLE 11:11 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_POLYSMOOTHENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POLYSMOOTHENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POLYSMOOTHENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_STIPPLE_EN 4:4 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_STIPPLE_EN_OFF 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_STIPPLE_EN_POLYGON 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_STIPPLE_EN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETPOINTENABLE 6:6 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_POFFSETPOINTENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETPOINTENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETPOINTENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETLINEENABLE 7:7 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_POFFSETLINEENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETLINEENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETLINEENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETFILLENABLE 8:8 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_POFFSETFILLENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETFILLENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_POFFSETFILLENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_LINEWIDTH 20:12 /* RWXUF */
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#define NV_PGRAPH_SETUPRASTER_LINEWIDTH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE 1:0 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_POINT 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_LINE 0x00000002 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_FILL 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACEMODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_BACKFACEMODE 3:2 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_BACKFACEMODE_POINT 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_BACKFACEMODE_LINE 0x00000002 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_BACKFACEMODE_FILL 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_BACKFACEMODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_CULLCTRL 22:21 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_CULLCTRL_FRONT 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULLCTRL_BACK 0x00000002 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULLCTRL_FRONT_AND_BACK 0x00000003 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULLCTRL_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACE 23:23 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACE_CW 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACE_CCW 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_FRONTFACE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH 27:25 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_8 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_16 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_32 0x00000002 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_64 0x00000003 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_128 0x00000004 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_OFF 0x00000007 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_SWATHWIDTH_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_CULL_NEAR_FAR_EN 30:30 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_CULL_NEAR_FAR_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULL_NEAR_FAR_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_CULL_NEAR_FAR_EN_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_IGNORE_WSIGN 5:5 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_IGNORE_WSIGN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_IGNORE_WSIGN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_IGNORE_WSIGN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SETUPRASTER_TWO_SIDED_LIGHTING 24:24 /* RWXVF */
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#define NV_PGRAPH_SETUPRASTER_TWO_SIDED_LIGHTING_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_TWO_SIDED_LIGHTING_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SETUPRASTER_TWO_SIDED_LIGHTING_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE 0x00401994 /* RW-4R */
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#define NV_PGRAPH_SHADERCLIPMODE_BUNDLE 0x00000065 /* ----B */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_S 0:0 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_S_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_S_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_S_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_T 1:1 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_T_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_T_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_T_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_R 2:2 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_R_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_R_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_Q 3:3 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_Q_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_Q_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE0_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_S 4:4 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_S_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_S_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_S_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_T 5:5 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_T_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_T_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_T_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_R 6:6 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_R_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_R_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_Q 7:7 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_Q_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_Q_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE1_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_S 8:8 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_S_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_S_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_S_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_T 9:9 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_T_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_T_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_T_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_R 10:10 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_R_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_R_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_Q 11:11 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_Q_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_Q_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE2_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_S 12:12 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_S_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_S_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_S_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_T 13:13 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_T_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_T_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_T_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_R 14:14 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_R_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_R_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_Q 15:15 /* RWXVF */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_Q_CLIPLTZ 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_Q_CLIPGEZ 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCLIPMODE_STAGE3_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCTL 0x00401998 /* RW-4R */
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#define NV_PGRAPH_SHADERCTL_BUNDLE 0x00000066 /* ----B */
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#define NV_PGRAPH_SHADERCTL_MAP1 2:0 /* RWXVF */
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#define NV_PGRAPH_SHADERCTL_MAP1_ZERO_TO_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_MINUS_1_TO_1_MS 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_MINUS_1_TO_1_GL 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_MINUS_1_TO_1_NV 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_HILO_1 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_HILO_HEMISPHERE_MS 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_HILO_HEMISPHERE_GL 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_HILO_HEMISPHERE_NV 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP1_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCTL_MAP2 5:3 /* RWXVF */
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#define NV_PGRAPH_SHADERCTL_MAP2_ZERO_TO_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_MINUS_1_TO_1_MS 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_MINUS_1_TO_1_GL 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_MINUS_1_TO_1_NV 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_HILO_1 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_HILO_HEMISPHERE_MS 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_HILO_HEMISPHERE_GL 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_HILO_HEMISPHERE_NV 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP2_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCTL_MAP3 8:6 /* RWXVF */
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#define NV_PGRAPH_SHADERCTL_MAP3_ZERO_TO_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_MINUS_1_TO_1_MS 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_MINUS_1_TO_1_GL 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_MINUS_1_TO_1_NV 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_HILO_1 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_HILO_HEMISPHERE_MS 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_HILO_HEMISPHERE_GL 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_HILO_HEMISPHERE_NV 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_MAP3_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCTL_OUT1 15:15 /* RWXVF */
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#define NV_PGRAPH_SHADERCTL_OUT1_INSTAGE_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_OUT1_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCTL_OUT2 16:16 /* RWXVF */
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#define NV_PGRAPH_SHADERCTL_OUT2_INSTAGE_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_OUT2_INSTAGE_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_OUT2_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERCTL_OUT3 21:20 /* RWXVF */
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#define NV_PGRAPH_SHADERCTL_OUT3_INSTAGE_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_OUT3_INSTAGE_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_OUT3_INSTAGE_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERCTL_OUT3_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG 0x0040199C /* RW-4R */
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#define NV_PGRAPH_SHADERPROG_BUNDLE 0x00000067 /* ----B */
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#define NV_PGRAPH_SHADERPROG_PASSTHROUGH 3:3 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_PASSTHROUGH_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_PASSTHROUGH_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_PASSTHROUGH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_0 30:30 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_0_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_1 31:31 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_W_DIVIDE_1_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG_STAGE0 2:0 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_STAGE0_PROGRAM_NONE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE0_2D_PROJECTIVE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE0_3D_PROJECTIVE 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE0_CUBE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE0_PASS_THROUGH 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE0_CLIP_PLANE 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE0_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG_STAGE1 9:5 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_STAGE1_PROGRAM_NONE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_2D_PROJECTIVE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_3D_PROJECTIVE 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_CUBE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_PASS_THROUGH 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_CLIP_PLANE 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_BUMPENVMAP 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_BUMPENVMAP_LUMINANCE 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_DEPENDENT_AR 0x0000000F /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_DEPENDENT_GB 0x00000010 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_DOT_PRODUCT 0x00000011 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE1_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG_STAGE2 14:10 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_STAGE2_PROGRAM_NONE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_2D_PROJECTIVE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_3D_PROJECTIVE 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_CUBE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_PASS_THROUGH 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_CLIP_PLANE 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_BUMPENVMAP 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_BUMPENVMAP_LUMINANCE 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_BRDF 0x00000008 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_DOT_ST 0x00000009 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_DOT_ZW 0x0000000A /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_DOT_REFLECT_DIFFUSE 0x0000000B /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_DEPENDENT_AR 0x0000000F /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_DEPENDENT_GB 0x00000010 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_DOT_PRODUCT 0x00000011 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE2_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADERPROG_STAGE3 19:15 /* RWXVF */
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#define NV_PGRAPH_SHADERPROG_STAGE3_PROGRAM_NONE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_2D_PROJECTIVE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_3D_PROJECTIVE 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_CUBE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_PASS_THROUGH 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_CLIP_PLANE 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_BUMPENVMAP 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_BUMPENVMAP_LUMINANCE 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_BRDF 0x00000008 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DOT_ST 0x00000009 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DOT_ZW 0x0000000A /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DOT_REFLECT_SPECULAR 0x0000000C /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DOT_STR_3D 0x0000000D /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DOT_STR_CUBE 0x0000000E /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DEPENDENT_AR 0x0000000F /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DEPENDENT_GB 0x00000010 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_DOT_REFLECT_SPECULAR_CONST 0x00000012 /* RW--V */
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#define NV_PGRAPH_SHADERPROG_STAGE3_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SEMAPHOREOFFSET 0x004019A0 /* RW-4R */
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#define NV_PGRAPH_SEMAPHOREOFFSET_BUNDLE 0x00000068 /* ----B */
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#define NV_PGRAPH_SEMAPHOREOFFSET_V 31:0 /* RWXUF */
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#define NV_PGRAPH_SEMAPHOREOFFSET_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOWCTL 0x004019A4 /* RW-4R */
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#define NV_PGRAPH_SHADOWCTL_BUNDLE 0x00000069 /* ----B */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC 2:0 /* RWXVF */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_NEVER 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_LESS 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_EQUAL 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_LEQUAL 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_GREATER 0x00000004 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_NOTEQUAL 0x00000005 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_GEQUAL 0x00000006 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_ALWAYS 0x00000007 /* RW--V */
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#define NV_PGRAPH_SHADOWCTL_SHADOW_ZFUNC_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOWZSLOPETHRESHOLD 0x004019A8 /* RW-4R */
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#define NV_PGRAPH_SHADOWZSLOPETHRESHOLD_BUNDLE 0x0000006A /* ----B */
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#define NV_PGRAPH_SHADOWZSLOPETHRESHOLD_SHADOW_ZOFFSET 31:0 /* RWXFF */
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#define NV_PGRAPH_SHADOWZSLOPETHRESHOLD_SHADOW_ZOFFSET_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SPECFOGFACTOR0 0x004019AC /* RW-4R */
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#define NV_PGRAPH_SPECFOGFACTOR0_BUNDLE 0x0000006B /* ----B */
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#define NV_PGRAPH_SPECFOGFACTOR0_BLUE 7:0 /* RWXUF */
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#define NV_PGRAPH_SPECFOGFACTOR0_BLUE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SPECFOGFACTOR0_GREEN 15:8 /* RWXUF */
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#define NV_PGRAPH_SPECFOGFACTOR0_GREEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SPECFOGFACTOR0_RED 23:16 /* RWXUF */
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#define NV_PGRAPH_SPECFOGFACTOR0_RED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SPECFOGFACTOR0_ALPHA 31:24 /* RWXUF */
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#define NV_PGRAPH_SPECFOGFACTOR0_ALPHA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SPECFOGFACTOR1 0x004019B0 /* RW-4R */
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#define NV_PGRAPH_SPECFOGFACTOR1_BUNDLE 0x0000006C /* ----B */
|
|
#define NV_PGRAPH_SPECFOGFACTOR1_BLUE 7:0 /* RWXUF */
|
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#define NV_PGRAPH_SPECFOGFACTOR1_BLUE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SPECFOGFACTOR1_GREEN 15:8 /* RWXUF */
|
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#define NV_PGRAPH_SPECFOGFACTOR1_GREEN_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_SPECFOGFACTOR1_RED 23:16 /* RWXUF */
|
|
#define NV_PGRAPH_SPECFOGFACTOR1_RED_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SPECFOGFACTOR1_ALPHA 31:24 /* RWXUF */
|
|
#define NV_PGRAPH_SPECFOGFACTOR1_ALPHA_097 0x00000000 /* RWC-V */
|
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#define NV_PGRAPH_SURFACECLIPX 0x004019B4 /* RW-4R */
|
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#define NV_PGRAPH_SURFACECLIPX_BUNDLE 0x0000006D /* ----B */
|
|
#define NV_PGRAPH_SURFACECLIPX_X 15:0 /* RWXUF */
|
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#define NV_PGRAPH_SURFACECLIPX_X_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACECLIPX_WIDTH 31:16 /* RWXUF */
|
|
#define NV_PGRAPH_SURFACECLIPX_WIDTH_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACECLIPY 0x004019B8 /* RW-4R */
|
|
#define NV_PGRAPH_SURFACECLIPY_BUNDLE 0x0000006E /* ----B */
|
|
#define NV_PGRAPH_SURFACECLIPY_Y 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_SURFACECLIPY_Y_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SURFACECLIPY_HEIGHT 31:16 /* RWXUF */
|
|
#define NV_PGRAPH_SURFACECLIPY_HEIGHT_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXADDRESS0 0x004019BC /* RW-4R */
|
|
#define NV_PGRAPH_TEXADDRESS0_BUNDLE 0x0000006F /* ----B */
|
|
#define NV_PGRAPH_TEXADDRESS0_ADDRU 2:0 /* RWXVF */
|
|
#define NV_PGRAPH_TEXADDRESS0_ADDRU_WRAP 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TEXADDRESS0_ADDRU_MIRROR 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_TEXADDRESS0_ADDRU_CLAMP_TO_EDGE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_TEXADDRESS0_ADDRU_BORDER 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_TEXADDRESS0_ADDRU_CLAMP_OGL 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_TEXADDRESS0_ADDRU_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_U 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_U_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_U_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV 10:8 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRV_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_V 12:12 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_V_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_V_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP 18:16 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_ADDRP_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_P 20:20 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_P_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_P_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_Q 24:24 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_Q_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_Q_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS0_WRAP_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1 0x004019C0 /* RW-4R */
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#define NV_PGRAPH_TEXADDRESS1_BUNDLE 0x00000070 /* ----B */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU 2:0 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRU_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_U 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_U_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_U_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV 10:8 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRV_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_V 12:12 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_V_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_V_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP 18:16 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_ADDRP_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_P 20:20 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_P_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_P_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_Q 24:24 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_Q_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_Q_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS1_WRAP_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2 0x004019C4 /* RW-4R */
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#define NV_PGRAPH_TEXADDRESS2_BUNDLE 0x00000071 /* ----B */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU 2:0 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRU_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_U 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_U_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_U_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV 10:8 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRV_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_V 12:12 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_V_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_V_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP 18:16 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_ADDRP_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_P 20:20 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_P_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_P_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_Q 24:24 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_Q_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_Q_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS2_WRAP_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3 0x004019C8 /* RW-4R */
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#define NV_PGRAPH_TEXADDRESS3_BUNDLE 0x00000072 /* ----B */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU 2:0 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRU_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_U 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_U_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_U_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV 10:8 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRV_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_V 12:12 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_V_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_V_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP 18:16 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP_WRAP 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP_MIRROR 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP_CLAMP_TO_EDGE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP_BORDER 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP_CLAMP_OGL 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_ADDRP_097 0x00000003 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_P 20:20 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_P_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_P_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_Q 24:24 /* RWXVF */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_Q_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_Q_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXADDRESS3_WRAP_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0 0x004019CC /* RW-4R */
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#define NV_PGRAPH_TEXCTL0_0_BUNDLE 0x00000073 /* ----B */
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#define NV_PGRAPH_TEXCTL0_0_ENABLE 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_0_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0_MIN_LOD_CLAMP 29:18 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_0_MIN_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0_MAX_LOD_CLAMP 17:6 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_0_MAX_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0_LOG_MAX_ANISO 5:4 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_0_LOG_MAX_ANISO_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_LOG_MAX_ANISO_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_LOG_MAX_ANISO_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_LOG_MAX_ANISO_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_LOG_MAX_ANISO_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0_IMAGEFIELDEN 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_0_IMAGEFIELDEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_IMAGEFIELDEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_IMAGEFIELDEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0_ALPHAKILLEN 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_0_ALPHAKILLEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_ALPHAKILLEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_ALPHAKILLEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_0_COLORKEYOP 1:0 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_0_COLORKEYOP_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_COLORKEYOP_ALPHA 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_COLORKEYOP_RGBA 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_COLORKEYOP_KILL 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_0_COLORKEYOP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1 0x004019D0 /* RW-4R */
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#define NV_PGRAPH_TEXCTL0_1_BUNDLE 0x00000074 /* ----B */
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#define NV_PGRAPH_TEXCTL0_1_ENABLE 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_1_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1_MIN_LOD_CLAMP 29:18 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_1_MIN_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1_MAX_LOD_CLAMP 17:6 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_1_MAX_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1_LOG_MAX_ANISO 5:4 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_1_LOG_MAX_ANISO_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_LOG_MAX_ANISO_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_LOG_MAX_ANISO_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_LOG_MAX_ANISO_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_LOG_MAX_ANISO_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1_IMAGEFIELDEN 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_1_IMAGEFIELDEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_IMAGEFIELDEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_IMAGEFIELDEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1_ALPHAKILLEN 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_1_ALPHAKILLEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_ALPHAKILLEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_ALPHAKILLEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_1_COLORKEYOP 1:0 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_1_COLORKEYOP_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_COLORKEYOP_ALPHA 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_COLORKEYOP_RGBA 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_COLORKEYOP_KILL 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_1_COLORKEYOP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2 0x004019D4 /* RW-4R */
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#define NV_PGRAPH_TEXCTL0_2_BUNDLE 0x00000075 /* ----B */
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#define NV_PGRAPH_TEXCTL0_2_ENABLE 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_2_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2_MIN_LOD_CLAMP 29:18 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_2_MIN_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2_MAX_LOD_CLAMP 17:6 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_2_MAX_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2_LOG_MAX_ANISO 5:4 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_2_LOG_MAX_ANISO_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_LOG_MAX_ANISO_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_LOG_MAX_ANISO_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_LOG_MAX_ANISO_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_LOG_MAX_ANISO_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2_IMAGEFIELDEN 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_2_IMAGEFIELDEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_IMAGEFIELDEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_IMAGEFIELDEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2_ALPHAKILLEN 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_2_ALPHAKILLEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_ALPHAKILLEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_ALPHAKILLEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_2_COLORKEYOP 1:0 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_2_COLORKEYOP_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_COLORKEYOP_ALPHA 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_COLORKEYOP_RGBA 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_COLORKEYOP_KILL 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_2_COLORKEYOP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3 0x004019D8 /* RW-4R */
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#define NV_PGRAPH_TEXCTL0_3_BUNDLE 0x00000076 /* ----B */
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#define NV_PGRAPH_TEXCTL0_3_ENABLE 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_3_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3_MIN_LOD_CLAMP 29:18 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_3_MIN_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3_MAX_LOD_CLAMP 17:6 /* RWXUF */
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#define NV_PGRAPH_TEXCTL0_3_MAX_LOD_CLAMP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3_LOG_MAX_ANISO 5:4 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_3_LOG_MAX_ANISO_0 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_LOG_MAX_ANISO_1 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_LOG_MAX_ANISO_2 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_LOG_MAX_ANISO_3 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_LOG_MAX_ANISO_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3_IMAGEFIELDEN 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_3_IMAGEFIELDEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_IMAGEFIELDEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_IMAGEFIELDEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3_ALPHAKILLEN 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_3_ALPHAKILLEN_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_ALPHAKILLEN_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_ALPHAKILLEN_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL0_3_COLORKEYOP 1:0 /* RWXVF */
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#define NV_PGRAPH_TEXCTL0_3_COLORKEYOP_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_COLORKEYOP_ALPHA 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_COLORKEYOP_RGBA 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_COLORKEYOP_KILL 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXCTL0_3_COLORKEYOP_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL1_0 0x004019DC /* RW-4R */
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#define NV_PGRAPH_TEXCTL1_0_BUNDLE 0x00000077 /* ----B */
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#define NV_PGRAPH_TEXCTL1_0_IMAGE_PITCH 31:16 /* RWXUF */
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#define NV_PGRAPH_TEXCTL1_0_IMAGE_PITCH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXCTL1_1 0x004019E0 /* RW-4R */
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#define NV_PGRAPH_TEXCTL1_1_BUNDLE 0x00000078 /* ----B */
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#define NV_PGRAPH_TEXCTL1_1_IMAGE_PITCH 31:16 /* RWXUF */
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#define NV_PGRAPH_TEXCTL1_1_IMAGE_PITCH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXCTL1_2 0x004019E4 /* RW-4R */
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#define NV_PGRAPH_TEXCTL1_2_BUNDLE 0x00000079 /* ----B */
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#define NV_PGRAPH_TEXCTL1_2_IMAGE_PITCH 31:16 /* RWXUF */
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#define NV_PGRAPH_TEXCTL1_2_IMAGE_PITCH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXCTL1_3 0x004019E8 /* RW-4R */
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#define NV_PGRAPH_TEXCTL1_3_BUNDLE 0x0000007A /* ----B */
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#define NV_PGRAPH_TEXCTL1_3_IMAGE_PITCH 31:16 /* RWXUF */
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#define NV_PGRAPH_TEXCTL1_3_IMAGE_PITCH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXCTL2_0 0x004019EC /* RW-4R */
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#define NV_PGRAPH_TEXCTL2_0_BUNDLE 0x0000007B /* ----B */
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#define NV_PGRAPH_TEXCTL2_0_PERTURB_DU 11:0 /* RWXSF */
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#define NV_PGRAPH_TEXCTL2_0_PERTURB_DU_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL2_0_PERTURB_DV 23:12 /* RWXSF */
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#define NV_PGRAPH_TEXCTL2_0_PERTURB_DV_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL2_0_IMAGE_LODF 31:24 /* RWXUF */
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#define NV_PGRAPH_TEXCTL2_0_IMAGE_LODF_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL2_1 0x004019F0 /* RW-4R */
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#define NV_PGRAPH_TEXCTL2_1_BUNDLE 0x0000007C /* ----B */
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#define NV_PGRAPH_TEXCTL2_1_PERTURB_DU 11:0 /* RWXSF */
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#define NV_PGRAPH_TEXCTL2_1_PERTURB_DU_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL2_1_PERTURB_DV 23:12 /* RWXSF */
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#define NV_PGRAPH_TEXCTL2_1_PERTURB_DV_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXCTL2_1_IMAGE_LODF 31:24 /* RWXUF */
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#define NV_PGRAPH_TEXCTL2_1_IMAGE_LODF_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0 0x004019F4 /* RW-4R */
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#define NV_PGRAPH_TEXFILTER0_BUNDLE 0x0000007D /* ----B */
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#define NV_PGRAPH_TEXFILTER0_MIPMAP_LOD_BIAS 12:0 /* RWXSF */
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#define NV_PGRAPH_TEXFILTER0_MIPMAP_LOD_BIAS_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_CONVOLUTION_KERNEL 15:13 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_CONVOLUTION_KERNEL_QUINCUNX 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_CONVOLUTION_KERNEL_GAUSSIAN_3 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_CONVOLUTION_KERNEL_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_MIN 21:16 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_MIN_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_BOX_NEARESTLOD 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_TENT_NEARESTLOD 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_BOX_TENT_LOD 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_TENT_TENT_LOD 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_CONVOLUTION_2D_LOD0 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MIN_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_MAG 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_MAG_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MAG_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MAG_CONVOLUTION_2D_LOD0 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_MAG_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_ASIGNED 28:28 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_ASIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_ASIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_ASIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_RSIGNED 29:29 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_RSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_RSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_RSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_GSIGNED 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_GSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_GSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_GSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER0_BSIGNED 31:31 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER0_BSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_BSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER0_BSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1 0x004019F8 /* RW-4R */
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#define NV_PGRAPH_TEXFILTER1_BUNDLE 0x0000007E /* ----B */
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#define NV_PGRAPH_TEXFILTER1_MIPMAP_LOD_BIAS 12:0 /* RWXSF */
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#define NV_PGRAPH_TEXFILTER1_MIPMAP_LOD_BIAS_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_CONVOLUTION_KERNEL 15:13 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_CONVOLUTION_KERNEL_QUINCUNX 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_CONVOLUTION_KERNEL_GAUSSIAN_3 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_CONVOLUTION_KERNEL_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_MIN 21:16 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_MIN_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_BOX_NEARESTLOD 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_TENT_NEARESTLOD 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_BOX_TENT_LOD 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_TENT_TENT_LOD 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_CONVOLUTION_2D_LOD0 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MIN_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_MAG 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_MAG_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MAG_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MAG_CONVOLUTION_2D_LOD0 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_MAG_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_ASIGNED 28:28 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_ASIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_ASIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_ASIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_RSIGNED 29:29 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_RSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_RSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_RSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_GSIGNED 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_GSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_GSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_GSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER1_BSIGNED 31:31 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER1_BSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_BSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER1_BSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2 0x004019FC /* RW-4R */
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#define NV_PGRAPH_TEXFILTER2_BUNDLE 0x0000007F /* ----B */
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#define NV_PGRAPH_TEXFILTER2_MIPMAP_LOD_BIAS 12:0 /* RWXSF */
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#define NV_PGRAPH_TEXFILTER2_MIPMAP_LOD_BIAS_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_CONVOLUTION_KERNEL 15:13 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_CONVOLUTION_KERNEL_QUINCUNX 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_CONVOLUTION_KERNEL_GAUSSIAN_3 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_CONVOLUTION_KERNEL_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_MIN 21:16 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_MIN_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_BOX_NEARESTLOD 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_TENT_NEARESTLOD 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_BOX_TENT_LOD 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_TENT_TENT_LOD 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_CONVOLUTION_2D_LOD0 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MIN_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_MAG 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_MAG_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MAG_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MAG_CONVOLUTION_2D_LOD0 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_MAG_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_ASIGNED 28:28 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_ASIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_ASIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_ASIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_RSIGNED 29:29 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_RSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_RSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_RSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_GSIGNED 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_GSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_GSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_GSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER2_BSIGNED 31:31 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER2_BSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_BSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER2_BSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3 0x00401A00 /* RW-4R */
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#define NV_PGRAPH_TEXFILTER3_BUNDLE 0x00000080 /* ----B */
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#define NV_PGRAPH_TEXFILTER3_MIPMAP_LOD_BIAS 12:0 /* RWXSF */
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#define NV_PGRAPH_TEXFILTER3_MIPMAP_LOD_BIAS_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_CONVOLUTION_KERNEL 15:13 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_CONVOLUTION_KERNEL_QUINCUNX 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_CONVOLUTION_KERNEL_GAUSSIAN_3 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_CONVOLUTION_KERNEL_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_MIN 21:16 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_MIN_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_BOX_NEARESTLOD 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_TENT_NEARESTLOD 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_BOX_TENT_LOD 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_TENT_TENT_LOD 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_CONVOLUTION_2D_LOD0 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MIN_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_MAG 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_MAG_BOX_LOD0 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MAG_TENT_LOD0 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MAG_CONVOLUTION_2D_LOD0 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_MAG_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_ASIGNED 28:28 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_ASIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_ASIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_ASIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_RSIGNED 29:29 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_RSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_RSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_RSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_GSIGNED 30:30 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_GSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_GSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_GSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFILTER3_BSIGNED 31:31 /* RWXVF */
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#define NV_PGRAPH_TEXFILTER3_BSIGNED_BIT_DISABLED 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_BSIGNED_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFILTER3_BSIGNED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0 0x00401A04 /* RW-4R */
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#define NV_PGRAPH_TEXFMT0_BUNDLE 0x00000081 /* ----B */
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#define NV_PGRAPH_TEXFMT0_CONTEXT_DMA 1:1 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_CONTEXT_DMA_A 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_CONTEXT_DMA_B 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_CONTEXT_DMA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_CUBEMAPENABLE 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_CUBEMAPENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_CUBEMAPENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_CUBEMAPENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_BORDER_SOURCE 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_TEXTURE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BORDER_SOURCE_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_ORIGIN_ZOH 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_ORIGIN_ZOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_ORIGIN_ZOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_ORIGIN_FOH 5:5 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_ORIGIN_FOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_ORIGIN_FOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_DIMENSIONALITY 7:6 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_DIMENSIONALITY_ONE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_DIMENSIONALITY_TWO 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_DIMENSIONALITY_THREE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_DIMENSIONALITY_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_COLOR 14:8 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_Y8 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_AY8 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_A1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_X1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_A4R4G4B4 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_A8R8G8B8 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_X8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_I8_A1R5G5B5 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_I8_R5G6B5 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_I8_A4R4G4B4 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_I8_A8R8G8B8 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_L_DXT1_A1R5G5B5 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_L_DXT23_A8R8G8B8 0x0000000E /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_L_DXT45_A8R8G8B8 0x0000000F /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A1R5G5B5 0x00000010 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_R5G6B5 0x00000011 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A8R8G8B8 0x00000012 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_Y8 0x00000013 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_SY8 0x00000014 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_X7SY9 0x00000015 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_R8B8 0x00000016 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_G8B8 0x00000017 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_SG8SB8 0x00000018 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_A8 0x00000019 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_A8Y8 0x0000001A /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_AY8 0x0000001B /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_X1R5G5B5 0x0000001C /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A4R4G4B4 0x0000001D /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_X8R8G8B8 0x0000001E /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A8 0x0000001F /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A8Y8 0x00000020 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x00000024 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x00000025 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A8CR8CB8Y8 0x00000026 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_R6G5B5 0x00000027 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_G8B8 0x00000028 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_R8B8 0x00000029 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x0000002A /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x0000002B /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_DEPTH_Y16_FIXED 0x0000002C /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_DEPTH_Y16_FLOAT 0x0000002D /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x0000002E /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_DEPTH_X8_Y24_FLOAT 0x0000002F /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x00000030 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x00000031 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_Y16 0x00000032 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_YB_16_YA_16 0x00000033 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x00000034 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_Y16 0x00000035 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_YB16YA16 0x00000036 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_R6G5B5 0x00000037 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_R5G5B5A1 0x00000038 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_R4G4B4A4 0x00000039 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_A8B8G8R8 0x0000003A /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_B8G8R8A8 0x0000003B /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_SZ_R8G8B8A8 0x0000003C /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_R5G5B5A1 0x0000003D /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_R4G4B4A4 0x0000003E /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_A8B8G8R8 0x0000003F /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_B8G8R8A8 0x00000040 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_LU_IMAGE_R8G8B8A8 0x00000041 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_COLOR_097 0x00000005 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_MIPMAP_LEVELS 19:16 /* RWXUF */
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#define NV_PGRAPH_TEXFMT0_MIPMAP_LEVELS_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U 23:20 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_1024 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_2048 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_4096 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_1024 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_2048 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_4096 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P 31:28 /* RWXVF */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT0_BASE_SIZE_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1 0x00401A08 /* RW-4R */
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#define NV_PGRAPH_TEXFMT1_BUNDLE 0x00000082 /* ----B */
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#define NV_PGRAPH_TEXFMT1_CONTEXT_DMA 1:1 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_CONTEXT_DMA_A 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_CONTEXT_DMA_B 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_CONTEXT_DMA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_CUBEMAPENABLE 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_CUBEMAPENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_CUBEMAPENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_CUBEMAPENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_BORDER_SOURCE 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_BORDER_SOURCE_TEXTURE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BORDER_SOURCE_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BORDER_SOURCE_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_ORIGIN_ZOH 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_ORIGIN_ZOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_ORIGIN_ZOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_ORIGIN_FOH 5:5 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_ORIGIN_FOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_ORIGIN_FOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_DIMENSIONALITY 7:6 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_DIMENSIONALITY_ONE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_DIMENSIONALITY_TWO 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_DIMENSIONALITY_THREE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_DIMENSIONALITY_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_COLOR 14:8 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_Y8 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_AY8 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_A1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_X1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_A4R4G4B4 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_A8R8G8B8 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_X8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_I8_A1R5G5B5 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_I8_R5G6B5 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_I8_A4R4G4B4 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_I8_A8R8G8B8 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_L_DXT1_A1R5G5B5 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_L_DXT23_A8R8G8B8 0x0000000E /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_L_DXT45_A8R8G8B8 0x0000000F /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A1R5G5B5 0x00000010 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_R5G6B5 0x00000011 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A8R8G8B8 0x00000012 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_Y8 0x00000013 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_SY8 0x00000014 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_X7SY9 0x00000015 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_R8B8 0x00000016 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_G8B8 0x00000017 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_SG8SB8 0x00000018 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_A8 0x00000019 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_A8Y8 0x0000001A /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_AY8 0x0000001B /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_X1R5G5B5 0x0000001C /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A4R4G4B4 0x0000001D /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_X8R8G8B8 0x0000001E /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A8 0x0000001F /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A8Y8 0x00000020 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x00000024 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x00000025 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A8CR8CB8Y8 0x00000026 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_R6G5B5 0x00000027 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_G8B8 0x00000028 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_R8B8 0x00000029 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x0000002A /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x0000002B /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_DEPTH_Y16_FIXED 0x0000002C /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_DEPTH_Y16_FLOAT 0x0000002D /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x0000002E /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_DEPTH_X8_Y24_FLOAT 0x0000002F /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x00000030 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x00000031 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_Y16 0x00000032 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_YB_16_YA_16 0x00000033 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x00000034 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_Y16 0x00000035 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_YB16YA16 0x00000036 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_R6G5B5 0x00000037 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_R5G5B5A1 0x00000038 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_R4G4B4A4 0x00000039 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_A8B8G8R8 0x0000003A /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_B8G8R8A8 0x0000003B /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_SZ_R8G8B8A8 0x0000003C /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_R5G5B5A1 0x0000003D /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_R4G4B4A4 0x0000003E /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_A8B8G8R8 0x0000003F /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_B8G8R8A8 0x00000040 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_LU_IMAGE_R8G8B8A8 0x00000041 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_COLOR_097 0x00000005 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_MIPMAP_LEVELS 19:16 /* RWXUF */
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#define NV_PGRAPH_TEXFMT1_MIPMAP_LEVELS_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U 23:20 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_1024 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_2048 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_4096 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_1024 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_2048 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_4096 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P 31:28 /* RWXVF */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT1_BASE_SIZE_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2 0x00401A0C /* RW-4R */
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#define NV_PGRAPH_TEXFMT2_BUNDLE 0x00000083 /* ----B */
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#define NV_PGRAPH_TEXFMT2_CONTEXT_DMA 1:1 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_CONTEXT_DMA_A 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_CONTEXT_DMA_B 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_CONTEXT_DMA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2_CUBEMAPENABLE 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_CUBEMAPENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_CUBEMAPENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_CUBEMAPENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2_BORDER_SOURCE 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_BORDER_SOURCE_TEXTURE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BORDER_SOURCE_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BORDER_SOURCE_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2_ORIGIN_ZOH 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_ORIGIN_ZOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_ORIGIN_ZOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2_ORIGIN_FOH 5:5 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_ORIGIN_FOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_ORIGIN_FOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2_DIMENSIONALITY 7:6 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_DIMENSIONALITY_ONE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_DIMENSIONALITY_TWO 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_DIMENSIONALITY_THREE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_DIMENSIONALITY_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_TEXFMT2_COLOR 14:8 /* RWXVF */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_Y8 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_AY8 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_A1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_X1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_A4R4G4B4 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_A8R8G8B8 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_X8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_I8_A1R5G5B5 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_I8_R5G6B5 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_I8_A4R4G4B4 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_I8_A8R8G8B8 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_L_DXT1_A1R5G5B5 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_L_DXT23_A8R8G8B8 0x0000000E /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_L_DXT45_A8R8G8B8 0x0000000F /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A1R5G5B5 0x00000010 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_R5G6B5 0x00000011 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A8R8G8B8 0x00000012 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_Y8 0x00000013 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_SY8 0x00000014 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_X7SY9 0x00000015 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_R8B8 0x00000016 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_G8B8 0x00000017 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_SG8SB8 0x00000018 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_A8 0x00000019 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_A8Y8 0x0000001A /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_AY8 0x0000001B /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_X1R5G5B5 0x0000001C /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A4R4G4B4 0x0000001D /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_X8R8G8B8 0x0000001E /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A8 0x0000001F /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A8Y8 0x00000020 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x00000024 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x00000025 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A8CR8CB8Y8 0x00000026 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_R6G5B5 0x00000027 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_G8B8 0x00000028 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_R8B8 0x00000029 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x0000002A /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x0000002B /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_DEPTH_Y16_FIXED 0x0000002C /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_DEPTH_Y16_FLOAT 0x0000002D /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x0000002E /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_DEPTH_X8_Y24_FLOAT 0x0000002F /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x00000030 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x00000031 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_Y16 0x00000032 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_YB_16_YA_16 0x00000033 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x00000034 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_Y16 0x00000035 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_YB16YA16 0x00000036 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_R6G5B5 0x00000037 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_R5G5B5A1 0x00000038 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_R4G4B4A4 0x00000039 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_A8B8G8R8 0x0000003A /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_B8G8R8A8 0x0000003B /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_SZ_R8G8B8A8 0x0000003C /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_R5G5B5A1 0x0000003D /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_R4G4B4A4 0x0000003E /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_A8B8G8R8 0x0000003F /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_B8G8R8A8 0x00000040 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_LU_IMAGE_R8G8B8A8 0x00000041 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_COLOR_097 0x00000005 /* RWC-V */
|
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#define NV_PGRAPH_TEXFMT2_MIPMAP_LEVELS 19:16 /* RWXUF */
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#define NV_PGRAPH_TEXFMT2_MIPMAP_LEVELS_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U 23:20 /* RWXVF */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_64 0x00000006 /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_512 0x00000009 /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_1024 0x0000000A /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_2048 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_4096 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_U_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V 27:24 /* RWXVF */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_1 0x00000000 /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_2 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_4 0x00000002 /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_8 0x00000003 /* RW--V */
|
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_16 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_32 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_64 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_128 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_256 0x00000008 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_512 0x00000009 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_1024 0x0000000A /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_2048 0x0000000B /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_4096 0x0000000C /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P 31:28 /* RWXVF */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_1 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_2 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT2_BASE_SIZE_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3 0x00401A10 /* RW-4R */
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#define NV_PGRAPH_TEXFMT3_BUNDLE 0x00000084 /* ----B */
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#define NV_PGRAPH_TEXFMT3_CONTEXT_DMA 1:1 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_CONTEXT_DMA_A 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_CONTEXT_DMA_B 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_CONTEXT_DMA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_CUBEMAPENABLE 2:2 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_CUBEMAPENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_CUBEMAPENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_CUBEMAPENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_BORDER_SOURCE 3:3 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_BORDER_SOURCE_TEXTURE 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BORDER_SOURCE_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BORDER_SOURCE_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_ORIGIN_ZOH 4:4 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_ORIGIN_ZOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_ORIGIN_ZOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_ORIGIN_FOH 5:5 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_ORIGIN_FOH_CORNER 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_ORIGIN_FOH_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_DIMENSIONALITY 7:6 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_DIMENSIONALITY_ONE 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_DIMENSIONALITY_TWO 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_DIMENSIONALITY_THREE 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_DIMENSIONALITY_097 0x00000002 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_COLOR 14:8 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_Y8 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_AY8 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_A1R5G5B5 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_X1R5G5B5 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_A4R4G4B4 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_R5G6B5 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_A8R8G8B8 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_X8R8G8B8 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_I8_A1R5G5B5 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_I8_R5G6B5 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_I8_A4R4G4B4 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_I8_A8R8G8B8 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_L_DXT1_A1R5G5B5 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_L_DXT23_A8R8G8B8 0x0000000E /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_L_DXT45_A8R8G8B8 0x0000000F /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A1R5G5B5 0x00000010 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_R5G6B5 0x00000011 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A8R8G8B8 0x00000012 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_Y8 0x00000013 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_SY8 0x00000014 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_X7SY9 0x00000015 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_R8B8 0x00000016 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_G8B8 0x00000017 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_SG8SB8 0x00000018 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_A8 0x00000019 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_A8Y8 0x0000001A /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_AY8 0x0000001B /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_X1R5G5B5 0x0000001C /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A4R4G4B4 0x0000001D /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_X8R8G8B8 0x0000001E /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A8 0x0000001F /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A8Y8 0x00000020 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x00000024 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x00000025 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A8CR8CB8Y8 0x00000026 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_R6G5B5 0x00000027 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_G8B8 0x00000028 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_R8B8 0x00000029 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x0000002A /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x0000002B /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_DEPTH_Y16_FIXED 0x0000002C /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_DEPTH_Y16_FLOAT 0x0000002D /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x0000002E /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_DEPTH_X8_Y24_FLOAT 0x0000002F /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x00000030 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x00000031 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_Y16 0x00000032 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_YB_16_YA_16 0x00000033 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x00000034 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_Y16 0x00000035 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_YB16YA16 0x00000036 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_R6G5B5 0x00000037 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_R5G5B5A1 0x00000038 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_R4G4B4A4 0x00000039 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_A8B8G8R8 0x0000003A /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_B8G8R8A8 0x0000003B /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_SZ_R8G8B8A8 0x0000003C /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_R5G5B5A1 0x0000003D /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_R4G4B4A4 0x0000003E /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_A8B8G8R8 0x0000003F /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_B8G8R8A8 0x00000040 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_LU_IMAGE_R8G8B8A8 0x00000041 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_COLOR_097 0x00000005 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_MIPMAP_LEVELS 19:16 /* RWXUF */
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#define NV_PGRAPH_TEXFMT3_MIPMAP_LEVELS_097 0x00000001 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U 23:20 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_1024 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_2048 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_4096 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_U_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V 27:24 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_1024 0x0000000A /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_2048 0x0000000B /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_4096 0x0000000C /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P 31:28 /* RWXVF */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_1 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_2 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_4 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_8 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_16 0x00000004 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_32 0x00000005 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_64 0x00000006 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_128 0x00000007 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_256 0x00000008 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_512 0x00000009 /* RW--V */
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#define NV_PGRAPH_TEXFMT3_BASE_SIZE_P_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT0 0x00401A14 /* RW-4R */
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#define NV_PGRAPH_TEXIMAGERECT0_BUNDLE 0x00000085 /* ----B */
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#define NV_PGRAPH_TEXIMAGERECT0_WIDTH 28:16 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT0_WIDTH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT0_HEIGHT 12:0 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT0_HEIGHT_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT1 0x00401A18 /* RW-4R */
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#define NV_PGRAPH_TEXIMAGERECT1_BUNDLE 0x00000086 /* ----B */
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#define NV_PGRAPH_TEXIMAGERECT1_WIDTH 28:16 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT1_WIDTH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT1_HEIGHT 12:0 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT1_HEIGHT_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT2 0x00401A1C /* RW-4R */
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#define NV_PGRAPH_TEXIMAGERECT2_BUNDLE 0x00000087 /* ----B */
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#define NV_PGRAPH_TEXIMAGERECT2_WIDTH 28:16 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT2_WIDTH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT2_HEIGHT 12:0 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT2_HEIGHT_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT3 0x00401A20 /* RW-4R */
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#define NV_PGRAPH_TEXIMAGERECT3_BUNDLE 0x00000088 /* ----B */
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#define NV_PGRAPH_TEXIMAGERECT3_WIDTH 28:16 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT3_WIDTH_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXIMAGERECT3_HEIGHT 12:0 /* RWXUF */
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#define NV_PGRAPH_TEXIMAGERECT3_HEIGHT_097 0x00000008 /* RWC-V */
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#define NV_PGRAPH_TEXOFFSET0 0x00401A24 /* RW-4R */
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#define NV_PGRAPH_TEXOFFSET0_BUNDLE 0x00000089 /* ----B */
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#define NV_PGRAPH_TEXOFFSET0_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_TEXOFFSET0_VALUE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXOFFSET1 0x00401A28 /* RW-4R */
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#define NV_PGRAPH_TEXOFFSET1_BUNDLE 0x0000008A /* ----B */
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#define NV_PGRAPH_TEXOFFSET1_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_TEXOFFSET1_VALUE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXOFFSET2 0x00401A2C /* RW-4R */
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#define NV_PGRAPH_TEXOFFSET2_BUNDLE 0x0000008B /* ----B */
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#define NV_PGRAPH_TEXOFFSET2_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_TEXOFFSET2_VALUE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXOFFSET3 0x00401A30 /* RW-4R */
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#define NV_PGRAPH_TEXOFFSET3_BUNDLE 0x0000008C /* ----B */
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#define NV_PGRAPH_TEXOFFSET3_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_TEXOFFSET3_VALUE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXPALETTE0 0x00401A34 /* RW-4R */
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#define NV_PGRAPH_TEXPALETTE0_BUNDLE 0x0000008D /* ----B */
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#define NV_PGRAPH_TEXPALETTE0_CONTEXT_DMA 0:0 /* RWXVF */
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#define NV_PGRAPH_TEXPALETTE0_CONTEXT_DMA_A 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE0_CONTEXT_DMA_B 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE0_CONTEXT_DMA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXPALETTE0_LENGTH 3:2 /* RWXVF */
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#define NV_PGRAPH_TEXPALETTE0_LENGTH_256 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE0_LENGTH_128 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE0_LENGTH_64 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE0_LENGTH_32 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE0_LENGTH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXPALETTE0_OFFSET 31:6 /* RWXUF */
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#define NV_PGRAPH_TEXPALETTE0_OFFSET_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXPALETTE1 0x00401A38 /* RW-4R */
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#define NV_PGRAPH_TEXPALETTE1_BUNDLE 0x0000008E /* ----B */
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#define NV_PGRAPH_TEXPALETTE1_CONTEXT_DMA 0:0 /* RWXVF */
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#define NV_PGRAPH_TEXPALETTE1_CONTEXT_DMA_A 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE1_CONTEXT_DMA_B 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE1_CONTEXT_DMA_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXPALETTE1_LENGTH 3:2 /* RWXVF */
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#define NV_PGRAPH_TEXPALETTE1_LENGTH_256 0x00000000 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE1_LENGTH_128 0x00000001 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE1_LENGTH_64 0x00000002 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE1_LENGTH_32 0x00000003 /* RW--V */
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#define NV_PGRAPH_TEXPALETTE1_LENGTH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_TEXPALETTE1_OFFSET 31:6 /* RWXUF */
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#define NV_PGRAPH_TEXPALETTE1_OFFSET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXPALETTE2 0x00401A3C /* RW-4R */
|
|
#define NV_PGRAPH_TEXPALETTE2_BUNDLE 0x0000008F /* ----B */
|
|
#define NV_PGRAPH_TEXPALETTE2_CONTEXT_DMA 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_TEXPALETTE2_CONTEXT_DMA_A 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE2_CONTEXT_DMA_B 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE2_CONTEXT_DMA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXPALETTE2_LENGTH 3:2 /* RWXVF */
|
|
#define NV_PGRAPH_TEXPALETTE2_LENGTH_256 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE2_LENGTH_128 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE2_LENGTH_64 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE2_LENGTH_32 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE2_LENGTH_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXPALETTE2_OFFSET 31:6 /* RWXUF */
|
|
#define NV_PGRAPH_TEXPALETTE2_OFFSET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXPALETTE3 0x00401A40 /* RW-4R */
|
|
#define NV_PGRAPH_TEXPALETTE3_BUNDLE 0x00000090 /* ----B */
|
|
#define NV_PGRAPH_TEXPALETTE3_CONTEXT_DMA 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_TEXPALETTE3_CONTEXT_DMA_A 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE3_CONTEXT_DMA_B 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE3_CONTEXT_DMA_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXPALETTE3_LENGTH 3:2 /* RWXVF */
|
|
#define NV_PGRAPH_TEXPALETTE3_LENGTH_256 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE3_LENGTH_128 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE3_LENGTH_64 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE3_LENGTH_32 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_TEXPALETTE3_LENGTH_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_TEXPALETTE3_OFFSET 31:6 /* RWXUF */
|
|
#define NV_PGRAPH_TEXPALETTE3_OFFSET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX0 0x00401A44 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX0_BUNDLE 0x00000091 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX0_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX0_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX0_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX0_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX1 0x00401A48 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX1_BUNDLE 0x00000092 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX1_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX1_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX1_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX1_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX2 0x00401A4C /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX2_BUNDLE 0x00000093 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX2_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX2_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX2_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX2_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX3 0x00401A50 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX3_BUNDLE 0x00000094 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX3_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX3_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX3_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX3_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX4 0x00401A54 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX4_BUNDLE 0x00000095 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX4_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX4_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX4_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX4_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX5 0x00401A58 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX5_BUNDLE 0x00000096 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX5_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX5_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX5_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX5_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX6 0x00401A5C /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX6_BUNDLE 0x00000097 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX6_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX6_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX6_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX6_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX7 0x00401A60 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPX7_BUNDLE 0x00000098 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPX7_XMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX7_XMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPX7_XMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPX7_XMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY0 0x00401A64 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY0_BUNDLE 0x00000099 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY0_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY0_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY0_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY0_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY1 0x00401A68 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY1_BUNDLE 0x0000009A /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY1_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY1_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY1_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY1_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY2 0x00401A6C /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY2_BUNDLE 0x0000009B /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY2_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY2_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY2_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY2_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY3 0x00401A70 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY3_BUNDLE 0x0000009C /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY3_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY3_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY3_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY3_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY4 0x00401A74 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY4_BUNDLE 0x0000009D /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY4_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY4_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY4_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY4_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY5 0x00401A78 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY5_BUNDLE 0x0000009E /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY5_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY5_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY5_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY5_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY6 0x00401A7C /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY6_BUNDLE 0x0000009F /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY6_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY6_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY6_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY6_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY7 0x00401A80 /* RW-4R */
|
|
#define NV_PGRAPH_WINDOWCLIPY7_BUNDLE 0x000000A0 /* ----B */
|
|
#define NV_PGRAPH_WINDOWCLIPY7_YMIN 11:0 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY7_YMIN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_WINDOWCLIPY7_YMAX 27:16 /* RWXUF */
|
|
#define NV_PGRAPH_WINDOWCLIPY7_YMAX_097 0x000007FF /* RWC-V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE 0x00401A84 /* RW-4R */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_BUNDLE 0x000000A1 /* ----B */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_ZCLAMP_EN 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_ZCLAMP_EN_CULL 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_ZCLAMP_EN_CLAMP 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_ZCLAMP_EN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_COMPRESS_ZEN 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_COMPRESS_ZEN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_COMPRESS_ZEN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_COMPRESS_ZEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_ZEN 1:1 /* RWXVF */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_ZEN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_ZEN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_ZEN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_STENCIL_EN 2:2 /* RWXVF */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_STENCIL_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_STENCIL_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_ZCOMPRESSOCCLUDE_OCCLUDE_STENCIL_EN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZSTENCILCLEARVALUE 0x00401A88 /* RW-4R */
|
|
#define NV_PGRAPH_ZSTENCILCLEARVALUE_BUNDLE 0x000000A2 /* ----B */
|
|
#define NV_PGRAPH_ZSTENCILCLEARVALUE_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_ZSTENCILCLEARVALUE_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZCLIPMAX 0x00401A8C /* RW-4R */
|
|
#define NV_PGRAPH_ZCLIPMAX_BUNDLE 0x000000A3 /* ----B */
|
|
#define NV_PGRAPH_ZCLIPMAX_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_ZCLIPMAX_V_097 0x4B7FFFFF /* RWC-V */
|
|
#define NV_PGRAPH_ZCLIPMIN 0x00401A90 /* RW-4R */
|
|
#define NV_PGRAPH_ZCLIPMIN_BUNDLE 0x000000A4 /* ----B */
|
|
#define NV_PGRAPH_ZCLIPMIN_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_ZCLIPMIN_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTEXTDMAA 0x00401A94 /* RW-4R */
|
|
#define NV_PGRAPH_CONTEXTDMAA_BUNDLE 0x000000A5 /* ----B */
|
|
#define NV_PGRAPH_CONTEXTDMAA_V 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_CONTEXTDMAA_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTEXTDMAA_TARGET 25:24 /* RWXVF */
|
|
#define NV_PGRAPH_CONTEXTDMAA_TARGET_NVM 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAA_TARGET_NVM_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAA_TARGET_PCI 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAA_TARGET_AGP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAA_TARGET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTEXTDMAB 0x00401A98 /* RW-4R */
|
|
#define NV_PGRAPH_CONTEXTDMAB_BUNDLE 0x000000A6 /* ----B */
|
|
#define NV_PGRAPH_CONTEXTDMAB_V 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_CONTEXTDMAB_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTEXTDMAB_TARGET 25:24 /* RWXVF */
|
|
#define NV_PGRAPH_CONTEXTDMAB_TARGET_NVM 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAB_TARGET_NVM_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAB_TARGET_PCI 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAB_TARGET_AGP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CONTEXTDMAB_TARGET_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTEXTVTXA 0x00401A9C /* RW-4R */
|
|
#define NV_PGRAPH_CONTEXTVTXA_BUNDLE 0x000000A7 /* ----B */
|
|
#define NV_PGRAPH_CONTEXTVTXA_V 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_CONTEXTVTXA_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CONTEXTVTXB 0x00401AA0 /* RW-4R */
|
|
#define NV_PGRAPH_CONTEXTVTXB_BUNDLE 0x000000A8 /* ----B */
|
|
#define NV_PGRAPH_CONTEXTVTXB_V 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_CONTEXTVTXB_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZOFFSETBIAS 0x00401AA4 /* RW-4R */
|
|
#define NV_PGRAPH_ZOFFSETBIAS_BUNDLE 0x000000A9 /* ----B */
|
|
#define NV_PGRAPH_ZOFFSETBIAS_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_ZOFFSETBIAS_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_ZOFFSETFACTOR 0x00401AA8 /* RW-4R */
|
|
#define NV_PGRAPH_ZOFFSETFACTOR_BUNDLE 0x000000AA /* ----B */
|
|
#define NV_PGRAPH_ZOFFSETFACTOR_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_ZOFFSETFACTOR_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_EYEVEC0 0x00401AAC /* RW-4R */
|
|
#define NV_PGRAPH_EYEVEC0_BUNDLE 0x000000AB /* ----B */
|
|
#define NV_PGRAPH_EYEVEC0_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_EYEVEC0_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_EYEVEC1 0x00401AB0 /* RW-4R */
|
|
#define NV_PGRAPH_EYEVEC1_BUNDLE 0x000000AC /* ----B */
|
|
#define NV_PGRAPH_EYEVEC1_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_EYEVEC1_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_EYEVEC2 0x00401AB4 /* RW-4R */
|
|
#define NV_PGRAPH_EYEVEC2_BUNDLE 0x000000AD /* ----B */
|
|
#define NV_PGRAPH_EYEVEC2_V 31:0 /* RWXFF */
|
|
#define NV_PGRAPH_EYEVEC2_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE0 0x00401C00 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE0_BUNDLE 0x00000100 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE0_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE0_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE1 0x00401C04 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE1_BUNDLE 0x00000101 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE1_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE1_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE2 0x00401C08 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE2_BUNDLE 0x00000102 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE2_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE2_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE3 0x00401C0C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE3_BUNDLE 0x00000103 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE3_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE3_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE4 0x00401C10 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE4_BUNDLE 0x00000104 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE4_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE4_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE5 0x00401C14 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE5_BUNDLE 0x00000105 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE5_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE5_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE6 0x00401C18 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE6_BUNDLE 0x00000106 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE6_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE6_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE7 0x00401C1C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE7_BUNDLE 0x00000107 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE7_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE7_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE8 0x00401C20 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE8_BUNDLE 0x00000108 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE8_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE8_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE9 0x00401C24 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE9_BUNDLE 0x00000109 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE9_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE9_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE10 0x00401C28 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE10_BUNDLE 0x0000010A /* ----B */
|
|
#define NV_PGRAPH_STIPPLE10_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE10_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE11 0x00401C2C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE11_BUNDLE 0x0000010B /* ----B */
|
|
#define NV_PGRAPH_STIPPLE11_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE11_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE12 0x00401C30 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE12_BUNDLE 0x0000010C /* ----B */
|
|
#define NV_PGRAPH_STIPPLE12_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE12_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE13 0x00401C34 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE13_BUNDLE 0x0000010D /* ----B */
|
|
#define NV_PGRAPH_STIPPLE13_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE13_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE14 0x00401C38 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE14_BUNDLE 0x0000010E /* ----B */
|
|
#define NV_PGRAPH_STIPPLE14_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE14_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE15 0x00401C3C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE15_BUNDLE 0x0000010F /* ----B */
|
|
#define NV_PGRAPH_STIPPLE15_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE15_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE16 0x00401C40 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE16_BUNDLE 0x00000110 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE16_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE16_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE17 0x00401C44 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE17_BUNDLE 0x00000111 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE17_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE17_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE18 0x00401C48 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE18_BUNDLE 0x00000112 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE18_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE18_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE19 0x00401C4C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE19_BUNDLE 0x00000113 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE19_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE19_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE20 0x00401C50 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE20_BUNDLE 0x00000114 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE20_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE20_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE21 0x00401C54 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE21_BUNDLE 0x00000115 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE21_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE21_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE22 0x00401C58 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE22_BUNDLE 0x00000116 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE22_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE22_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE23 0x00401C5C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE23_BUNDLE 0x00000117 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE23_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE23_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE24 0x00401C60 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE24_BUNDLE 0x00000118 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE24_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE24_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE25 0x00401C64 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE25_BUNDLE 0x00000119 /* ----B */
|
|
#define NV_PGRAPH_STIPPLE25_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE25_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE26 0x00401C68 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE26_BUNDLE 0x0000011A /* ----B */
|
|
#define NV_PGRAPH_STIPPLE26_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE26_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE27 0x00401C6C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE27_BUNDLE 0x0000011B /* ----B */
|
|
#define NV_PGRAPH_STIPPLE27_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE27_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE28 0x00401C70 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE28_BUNDLE 0x0000011C /* ----B */
|
|
#define NV_PGRAPH_STIPPLE28_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE28_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE29 0x00401C74 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE29_BUNDLE 0x0000011D /* ----B */
|
|
#define NV_PGRAPH_STIPPLE29_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE29_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE30 0x00401C78 /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE30_BUNDLE 0x0000011E /* ----B */
|
|
#define NV_PGRAPH_STIPPLE30_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE30_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_STIPPLE31 0x00401C7C /* RW-4R */
|
|
#define NV_PGRAPH_STIPPLE31_BUNDLE 0x0000011F /* ----B */
|
|
#define NV_PGRAPH_STIPPLE31_V 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_STIPPLE31_V_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0 0x00400F90 /* RW-4R */
|
|
#define NV_PGRAPH_BEGINPATCH0_POSITION_DEGREE 3:0 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_POSITION_DEGREE_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM1_DEGREE 7:4 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM1_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM2_DEGREE 11:8 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM2_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM3_DEGREE 15:12 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM3_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM4_DEGREE 19:16 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM4_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM5_DEGREE 23:20 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM5_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM6_DEGREE 27:24 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM6_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM7_DEGREE 31:28 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH0_PARAM7_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1 0x00400F94 /* RW-4R */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM8_DEGREE 3:0 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM8_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM9_DEGREE 7:4 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM9_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM10_DEGREE 11:8 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM10_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM11_DEGREE 15:12 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM11_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM12_DEGREE 19:16 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM12_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM13_DEGREE 23:20 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM13_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM14_DEGREE 27:24 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM14_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM15_DEGREE 31:28 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH1_PARAM15_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH2 0x00400F98 /* RW-4R */
|
|
#define NV_PGRAPH_BEGINPATCH2_SWATCH_ROWS 7:0 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH2_SWATCH_ROWS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH2_SWATCH_COLS 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH2_SWATCH_COLS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH2_SWATCH_SIZE 20:16 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH2_SWATCH_SIZE_097 0x00000004 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH2_PARTIAL_SWATCH_WIDTH 25:21 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH2_PARTIAL_SWATCH_WIDTH_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH2_PARTIAL_SWATCH_HEIGHT 30:26 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINPATCH2_PARTIAL_SWATCH_HEIGHT_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH3 0x00400F9C /* RW-4R */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS 2:0 /* RWXVF */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_NONE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_FIRST 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_LAST 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_FIRST_AND_LAST 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_REV_FIRST 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_REV_LAST 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_ROW_TRNS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS 5:3 /* RWXVF */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_NONE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_FIRST 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_LAST 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_FIRST_AND_LAST 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_REV_FIRST 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_REV_LAST 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_COL_TRNS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH3_PRIM 15:14 /* RWXVF */
|
|
#define NV_PGRAPH_BEGINPATCH3_PRIM_TRI_STRIP 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_PRIM_REVERSED_TRI_STRIP 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_PRIM_BW_TRI_STRIP 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_PRIM_BW_REVERSED_TRI_STRIP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_PRIM_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINPATCH3_TESS 16:16 /* RWXVF */
|
|
#define NV_PGRAPH_BEGINPATCH3_TESS_ADAPTIVE_STITCH 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_TESS_FIXED_STITCH 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_BEGINPATCH3_TESS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CURVE 0x00400FA0 /* RW-4R */
|
|
#define NV_PGRAPH_CURVE_CMD 2:0 /* RWXVF */
|
|
#define NV_PGRAPH_CURVE_CMD_END_CURVE_DATA 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_STRIP_CURVE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_LEFT_GUARD_CURVE 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_RIGHT_GUARD_CURVE 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_OUTER_TRANSITION_CURVE 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_INNER_TRANSITION_CURVE 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_OUTER_END_PT 0x00000006 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_INNER_END_PT 0x00000007 /* RW--V */
|
|
#define NV_PGRAPH_CURVE_CMD_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0 0x00400FA4 /* RW-4R */
|
|
#define NV_PGRAPH_BEGINTRANS0_POSITION_DEGREE 3:0 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_POSITION_DEGREE_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM1_DEGREE 7:4 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM1_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM2_DEGREE 11:8 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM2_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM3_DEGREE 15:12 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM3_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM4_DEGREE 19:16 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM4_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM5_DEGREE 23:20 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM5_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM6_DEGREE 27:24 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM6_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM7_DEGREE 31:28 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS0_PARAM7_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1 0x00400FA8 /* RW-4R */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM8_DEGREE 3:0 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM8_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM9_DEGREE 7:4 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM9_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM10_DEGREE 11:8 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM10_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM11_DEGREE 15:12 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM11_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM12_DEGREE 19:16 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM12_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM13_DEGREE 23:20 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM13_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM14_DEGREE 27:24 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM14_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM15_DEGREE 31:28 /* RWXUF */
|
|
#define NV_PGRAPH_BEGINTRANS1_PARAM15_DEGREE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D 0x00400FB4 /* RW-4R */
|
|
#define NV_PGRAPH_CSV0_D_FOG_MODE 21:21 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_FOG_MODE_LINEAR 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOG_MODE_EXP 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOG_MODE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE 24:22 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE_SPEC_ALPHA 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE_RADIAL 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE_PLANAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE_ABS_PLANAR 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE_FOG_X 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGGENMODE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_FOGENABLE 19:19 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_FOGENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_FOGENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_POINTPARAMSENABLE 25:25 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_POINTPARAMSENABLE_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_POINTPARAMSENABLE_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_POINTPARAMSENABLE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_D_SKIN 28:26 /* RWXVF */
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|
#define NV_PGRAPH_CSV0_D_SKIN_OFF 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_SKIN_2G 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_SKIN_2 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_SKIN_3G 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_SKIN_3 0x00000004 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_SKIN_4G 0x00000005 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_SKIN_4 0x00000006 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_SKIN_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT0 1:0 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT0_OFF 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT0_INFINITE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT0_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT0_SPOT 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT0_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT1 3:2 /* RWXVF */
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|
#define NV_PGRAPH_CSV0_D_LIGHT1_OFF 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV0_D_LIGHT1_INFINITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT1_LOCAL 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT1_SPOT 0x00000003 /* RW--V */
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#define NV_PGRAPH_CSV0_D_LIGHT1_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT2 5:4 /* RWXVF */
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|
#define NV_PGRAPH_CSV0_D_LIGHT2_OFF 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT2_INFINITE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT2_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT2_SPOT 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT2_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT3 7:6 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT3_OFF 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT3_INFINITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT3_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT3_SPOT 0x00000003 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_LIGHT3_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT4 9:8 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT4_OFF 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT4_INFINITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT4_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT4_SPOT 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT4_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT5 11:10 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT5_OFF 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT5_INFINITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT5_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT5_SPOT 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT5_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT6 13:12 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT6_OFF 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT6_INFINITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT6_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT6_SPOT 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT6_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT7 15:14 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT7_OFF 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT7_INFINITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT7_LOCAL 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT7_SPOT 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_LIGHT7_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_TEXGEN_REF 20:20 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_TEXGEN_REF_LOCAL_VIEWER 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_TEXGEN_REF_INFINITE_VIEWER 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_TEXGEN_REF_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_PASSTHROUGH 31:30 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_PASSTHROUGH_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_PASSTHROUGH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_PASSTHROUGH_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_MODE 31:30 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_MODE_FIXED 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_MODE_PROGRAM 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_MODE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_RANGE_MODE 18:18 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_RANGE_MODE_USER 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_RANGE_MODE_PRIV 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_D_RANGE_MODE_097 0x00000001 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_D_CHEOPS_STALL 29:29 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_D_CHEOPS_STALL_READ_ONLY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_CHEOPS_STALL_READ_WRITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_D_CHEOPS_STALL_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C 0x00400FB8 /* RW-4R */
|
|
#define NV_PGRAPH_CSV0_C_EYETYPE_LOCAL 30:30 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_EYETYPE_LOCAL_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_EYETYPE_LOCAL_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_EYETYPE_LOCAL_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_SOUT 17:17 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_SOUT_ZERO_OUT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_SOUT_PASSTHROUGH 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_SOUT_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C_LIGHT_ATTENUATION 28:28 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_LIGHT_ATTENUATION_INVERT 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_LIGHT_ATTENUATION_NOT_INVERT 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_LIGHT_ATTENUATION_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C_SEPARATE_SPECULAR_ENABLE 18:18 /* RWXVF */
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|
#define NV_PGRAPH_CSV0_C_SEPARATE_SPECULAR_ENABLE_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_SEPARATE_SPECULAR_ENABLE_TRUE 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_SEPARATE_SPECULAR_ENABLE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C_EMISSION 26:25 /* RWXVF */
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|
#define NV_PGRAPH_CSV0_C_EMISSION_DISABLE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_EMISSION_DIFFUSE_VTX_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV0_C_EMISSION_SPECULAR_VTX_COLOR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV0_C_EMISSION_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV0_C_AMBIENT 24:23 /* RWXVF */
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#define NV_PGRAPH_CSV0_C_AMBIENT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV0_C_AMBIENT_DIFFUSE_VTX_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV0_C_AMBIENT_SPECULAR_VTX_COLOR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV0_C_AMBIENT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV0_C_DIFFUSE 22:21 /* RWXVF */
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#define NV_PGRAPH_CSV0_C_DIFFUSE_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV0_C_DIFFUSE_DIFFUSE_VTX_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV0_C_DIFFUSE_SPECULAR_VTX_COLOR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV0_C_DIFFUSE_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C_SPECULAR 20:19 /* RWXVF */
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#define NV_PGRAPH_CSV0_C_SPECULAR_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV0_C_SPECULAR_DIFFUSE_VTX_COLOR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV0_C_SPECULAR_SPECULAR_VTX_COLOR 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_SPECULAR_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C_BCK_EMSSN 7:6 /* RWXVF */
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#define NV_PGRAPH_CSV0_C_BCK_EMSSN_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV0_C_BCK_EMSSN_DIFF_VTX_COLOR 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_BCK_EMSSN_SPEC_VTX_COLOR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV0_C_BCK_EMSSN_097 0x00000000 /* RWC-V */
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|
#define NV_PGRAPH_CSV0_C_BCK_AMBNT 5:4 /* RWXVF */
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#define NV_PGRAPH_CSV0_C_BCK_AMBNT_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV0_C_BCK_AMBNT_DIFF_VTX_COLOR 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_BCK_AMBNT_SPEC_VTX_COLOR 0x00000002 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_BCK_AMBNT_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_BCK_DFFUS 3:2 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_BCK_DFFUS_DISABLE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_BCK_DFFUS_DIFF_VTX_COLOR 0x00000001 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_BCK_DFFUS_SPEC_VTX_COLOR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_BCK_DFFUS_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_BCK_SPCLR 1:0 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_BCK_SPCLR_DISABLE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_CSV0_C_BCK_SPCLR_DIFF_VTX_COLOR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_BCK_SPCLR_SPEC_VTX_COLOR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_BCK_SPCLR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_LIGHTING 31:31 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_LIGHTING_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_LIGHTING_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_LIGHTING_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_NORMALIZATION_ENABLE 27:27 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_NORMALIZATION_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_NORMALIZATION_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_NORMALIZATION_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_SPECULARENABLE 16:16 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_SPECULARENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_SPECULARENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_SPECULARENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_CHEOPS_PROGRAM_START 15:8 /* RWXUF */
|
|
#define NV_PGRAPH_CSV0_C_CHEOPS_PROGRAM_START_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV0_C_TWO_SIDED_LIGHTING 29:29 /* RWXVF */
|
|
#define NV_PGRAPH_CSV0_C_TWO_SIDED_LIGHTING_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_TWO_SIDED_LIGHTING_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV0_C_TWO_SIDED_LIGHTING_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B 0x00400FBC /* RW-4R */
|
|
#define NV_PGRAPH_CSV1_B_T2_S 6:4 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_NORMAL_MAP 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_REFLECTION_MAP 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_EYE_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_OBJECT_LINEAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_SPHERE_MAP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_S_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T 9:7 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_NORMAL_MAP 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_REFLECTION_MAP 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_EYE_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_OBJECT_LINEAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_SPHERE_MAP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_T_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T2_R 12:10 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_R_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_R_NORMAL_MAP 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_R_REFLECTION_MAP 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_R_EYE_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_R_OBJECT_LINEAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_R_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T2_Q 15:13 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_Q_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_Q_EYE_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_Q_OBJECT_LINEAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_Q_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T2_MODE 1:1 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_MODE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_MODE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_MODE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T2_TEXTURE 2:2 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_TEXTURE_2D 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_TEXTURE_3D 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_TEXTURE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T2_ENABLE 0:0 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T2_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T2_ENABLE_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S 22:20 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_NORMAL_MAP 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_REFLECTION_MAP 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_EYE_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_OBJECT_LINEAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_SPHERE_MAP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_S_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T 25:23 /* RWXVF */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_NORMAL_MAP 0x00000004 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_REFLECTION_MAP 0x00000005 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_EYE_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_OBJECT_LINEAR 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_SPHERE_MAP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_CSV1_B_T3_T_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_CSV1_B_T3_R 28:26 /* RWXVF */
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#define NV_PGRAPH_CSV1_B_T3_R_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_R_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_R_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_R_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_R_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_B_T3_Q 31:29 /* RWXVF */
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#define NV_PGRAPH_CSV1_B_T3_Q_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_Q_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_Q_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_B_T3_MODE 17:17 /* RWXVF */
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#define NV_PGRAPH_CSV1_B_T3_MODE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_MODE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_MODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_B_T3_TEXTURE 18:18 /* RWXVF */
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#define NV_PGRAPH_CSV1_B_T3_TEXTURE_2D 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_TEXTURE_3D 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_TEXTURE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_B_T3_ENABLE 16:16 /* RWXVF */
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#define NV_PGRAPH_CSV1_B_T3_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_B_T3_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A 0x00400FC0 /* RW-4R */
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#define NV_PGRAPH_CSV1_A_T0_S 6:4 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_S_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_S_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_S_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_S_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_S_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_S_SPHERE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_S_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T0_T 9:7 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_T_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_T_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_T_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_T_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_T_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_T_SPHERE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_T_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T0_R 12:10 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_R_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_R_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_R_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_R_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_R_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T0_Q 15:13 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_Q_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_Q_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_Q_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T0_MODE 1:1 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_MODE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_MODE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_MODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T0_TEXTURE 2:2 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_TEXTURE_2D 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_TEXTURE_3D 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_TEXTURE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T0_ENABLE 0:0 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T0_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T0_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_S 22:20 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_S_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_S_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_S_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_S_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_S_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_S_SPHERE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_S_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_T 25:23 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_T_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_T_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_T_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_T_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_T_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_T_SPHERE_MAP 0x00000003 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_T_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_R 28:26 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_R_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_R_NORMAL_MAP 0x00000004 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_R_REFLECTION_MAP 0x00000005 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_R_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_R_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_R_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_Q 31:29 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_Q_DISABLE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_Q_EYE_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_Q_OBJECT_LINEAR 0x00000002 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_Q_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_MODE 17:17 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_MODE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_MODE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_MODE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_TEXTURE 18:18 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_TEXTURE_2D 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_TEXTURE_3D 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_TEXTURE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CSV1_A_T1_ENABLE 16:16 /* RWXVF */
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#define NV_PGRAPH_CSV1_A_T1_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_CSV1_A_T1_ENABLE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CHEOPS_OFFSET 0x00400FC4 /* RW-4R */
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#define NV_PGRAPH_CHEOPS_OFFSET_PROG_LD_PTR 7:0 /* RWXUF */
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#define NV_PGRAPH_CHEOPS_OFFSET_PROG_LD_PTR_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_CHEOPS_OFFSET_CONST_LD_PTR 15:8 /* RWXUF */
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#define NV_PGRAPH_CHEOPS_OFFSET_CONST_LD_PTR_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_ZCULLINTERLOCK 0x00000000 /* ---4P */
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#define NV_PGRAPH_ZCULLINTERLOCK_BUNDLE 0x1D0 /* ----B */
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#define NV_PGRAPH_ZCULLINTERLOCK_SEMA 9:0 /* ---VF */
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#define NV_PGRAPH_BLTFIRSTSPAN 0x00000000 /* ---4P */
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#define NV_PGRAPH_BLTFIRSTSPAN_BUNDLE 0x000001D1 /* ----B */
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#define NV_PGRAPH_BLTFIRSTSPAN_SRCMINUSDST 6:0 /* ---VF */
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#define NV_PGRAPH_BLTFIRSTSPAN_SRCANCHORPART 17:16 /* ---VF */
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#define NV_PGRAPH_BLTFIRSTSPAN_DSTANCHORPART 19:18 /* ---VF */
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#define NV_PGRAPH_BLTFIRSTSPAN_L2R 20:20 /* ---VF */
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#define NV_PGRAPH_BLTFIRSTSPAN_L2R_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_BLTFIRSTSPAN_L2R_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_BLTFIRSTSPAN_RRW 21:21 /* ---VF */
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#define NV_PGRAPH_BLTFIRSTSPAN_RRW_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_BLTFIRSTSPAN_RRW_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_BLTNTHSPAN 0x00000000 /* ---4P */
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#define NV_PGRAPH_BLTNTHSPAN_BUNDLE 0x000001D2 /* ----B */
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#define NV_PGRAPH_BLTNTHSPAN_SRCMINUSDST 6:0 /* ---VF */
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#define NV_PGRAPH_BLTNTHSPAN_SRCANCHORPART 17:16 /* ---VF */
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#define NV_PGRAPH_BLTNTHSPAN_DSTANCHORPART 19:18 /* ---VF */
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#define NV_PGRAPH_BLTNTHSPAN_L2R 20:20 /* ---VF */
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#define NV_PGRAPH_BLTNTHSPAN_L2R_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_BLTNTHSPAN_L2R_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_BLTNTHSPAN_RRW 21:21 /* ---VF */
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#define NV_PGRAPH_BLTNTHSPAN_RRW_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_BLTNTHSPAN_RRW_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_BLTEND 0x00000000 /* ---4P */
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#define NV_PGRAPH_BLTEND_BUNDLE 0x000001D3 /* ----B */
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#define NV_PGRAPH_ROPFLUSH 0x00000000 /* ---4P */
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#define NV_PGRAPH_ROPFLUSH_BUNDLE 0x1D4 /* ----B */
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#define NV_PGRAPH_PALLOAD_BUNDLE 0x1D5 /* ----B */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL 2:0 /* ---VF */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S0_N8 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S0_N4 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S4_N4 0x00000002 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S0_N2 0x00000003 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S2_N2 0x00000004 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S4_N2 0x00000005 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_S6_N2 0x00000006 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_ALLOCCTL_NONE 0x00000007 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_LOAD_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX0_LOAD_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL 6:4 /* ---VF */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S0_N8 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S0_N4 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S4_N4 0x00000002 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S0_N2 0x00000003 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S2_N2 0x00000004 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S4_N2 0x00000005 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_S6_N2 0x00000006 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_ALLOCCTL_NONE 0x00000007 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_LOAD_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX1_LOAD_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL 10:8 /* ---VF */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S0_N8 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S0_N4 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S4_N4 0x00000002 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S0_N2 0x00000003 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S2_N2 0x00000004 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S4_N2 0x00000005 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_S6_N2 0x00000006 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_ALLOCCTL_NONE 0x00000007 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_LOAD_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX2_LOAD_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL 14:12 /* ---VF */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S0_N8 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S0_N4 0x00000001 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S4_N4 0x00000002 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S0_N2 0x00000003 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S2_N2 0x00000004 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S4_N2 0x00000005 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_S6_N2 0x00000006 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_ALLOCCTL_NONE 0x00000007 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_LOAD_FALSE 0x00000000 /* ----V */
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#define NV_PGRAPH_PALLOAD_TEX3_LOAD_TRUE 0x00000001 /* ----V */
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#define NV_PGRAPH_PIPE_ADDRESS 0x00400F50 /* RW-4R */
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#define NV_PGRAPH_PIPE_ADDRESS_VALUE 16:2 /* RWXVF */
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#define NV_PGRAPH_PIPE_DATA 0x00400F54 /* RW-4R */
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#define NV_PGRAPH_PIPE_DATA_VALUE 31:0 /* RWXVF */
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#define NV_PGRAPH_SHADOW 0x00400F5C /* RW-4R */
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|
#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND 0:0 /* RWXVF */
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#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_SECONDARY_COLOR_EN 2:2 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_SECONDARY_COLOR_EN_FALSE 0x00000000 /* RW--V */
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|
#define NV_PGRAPH_SHADOW_SECONDARY_COLOR_EN_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_SECONDARY_COLOR_EN_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_COLORMATERIAL_SPECULAR 3:3 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_COLORMATERIAL_SPECULAR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_COLORMATERIAL_SPECULAR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_COLORMATERIAL_SPECULAR_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH 4:4 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH0 5:5 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH0_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH0_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH0_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH1 6:6 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH1_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH1_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH1_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH2 7:7 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH2_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH2_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_PATCH2_097 0x00000000 /* RWC-V */
|
|
#define NV_PGRAPH_SHADOW_IN_SWATCH 8:8 /* RWXVF */
|
|
#define NV_PGRAPH_SHADOW_IN_SWATCH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_SHADOW_IN_SWATCH_TRUE 0x00000001 /* RW--V */
|
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#define NV_PGRAPH_SHADOW_IN_SWATCH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_GUARD 10:9 /* RWXVF */
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#define NV_PGRAPH_SHADOW_GUARD_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_GUARD_LEFT_SET 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_GUARD_RIGHT_SET 0x00000002 /* RW--V */
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#define NV_PGRAPH_SHADOW_GUARD_BOTH_SET 0x00000003 /* RW--V */
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#define NV_PGRAPH_SHADOW_GUARD_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION 11:11 /* RWXVF */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION0 12:12 /* RWXVF */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION0_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION0_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION0_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION1 13:13 /* RWXVF */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION1_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION1_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_IN_TRANSITION1_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_CURVE 15:15 /* RWXVF */
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#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_CURVE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_CURVE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_WITHIN_BEGINEND_CURVE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_SWATCH_DONE 16:16 /* RWXVF */
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#define NV_PGRAPH_SHADOW_SWATCH_DONE_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_SWATCH_DONE_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_SWATCH_DONE_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_OUTER_END_PT 17:17 /* RWXVF */
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#define NV_PGRAPH_SHADOW_OUTER_END_PT_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_OUTER_END_PT_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_OUTER_END_PT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_OUTER_TRANSITION 18:18 /* RWXVF */
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#define NV_PGRAPH_SHADOW_OUTER_TRANSITION_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_OUTER_TRANSITION_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_OUTER_TRANSITION_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_INNER_TRANSITION 19:19 /* RWXVF */
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#define NV_PGRAPH_SHADOW_INNER_TRANSITION_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_INNER_TRANSITION_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_INNER_TRANSITION_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_PARK 20:20 /* RWXVF */
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#define NV_PGRAPH_SHADOW_PARK_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_PARK_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_PARK_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_DIRTY_ECOLMAT 21:21 /* RWXVF */
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#define NV_PGRAPH_SHADOW_DIRTY_ECOLMAT_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_DIRTY_ECOLMAT_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_DIRTY_ECOLMAT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_DIRTY_ACOLMAT 22:22 /* RWXVF */
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#define NV_PGRAPH_SHADOW_DIRTY_ACOLMAT_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_DIRTY_ACOLMAT_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_DIRTY_ACOLMAT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_INNER_END_PT 23:23 /* RWXVF */
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#define NV_PGRAPH_SHADOW_INNER_END_PT_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_INNER_END_PT_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_INNER_END_PT_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SHADOW_FD_ERROR_DETECTED 24:24 /* RWXVF */
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#define NV_PGRAPH_SHADOW_FD_ERROR_DETECTED_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_SHADOW_FD_ERROR_DETECTED_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_SHADOW_FD_ERROR_DETECTED_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_DATA 0x00400F60 /* RW-4R */
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#define NV_PGRAPH_FD_DATA_COUNTER_COEFF 9:0 /* RWXUF */
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#define NV_PGRAPH_FD_DATA_COUNTER_COEFF_097 0x0000000 /* RWC-V */
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#define NV_PGRAPH_FD_DATA_GUARD_CURVE_SPEC 17:12 /* RWXUF */
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#define NV_PGRAPH_FD_DATA_GUARD_CURVE_097 0x0000000 /* RWC-V */
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#define NV_PGRAPH_FD_DATA_CURVE_SPEC 25:18 /* RWXUF */
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#define NV_PGRAPH_FD_DATA_CURVE_SPEC_097 0x0000000 /* RWC-V */
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#define NV_PGRAPH_FD_DATA_PT_SPEC 31:28 /* RWXUF */
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#define NV_PGRAPH_FD_DATA_PT_SPEC_097 0x0000000 /* RWC-V */
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#define NV_PGRAPH_FD_SWATCH 0x00400F64 /* RW-4R */
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#define NV_PGRAPH_FD_SWATCH_CURVES_PER_SWATCH_SPEC 7:0 /* RWXUF */
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#define NV_PGRAPH_FD_SWATCH_CURVES_PER_SWATCH_SPEC_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_SWATCH_HT_COUNTER 15:8 /* RWXUF */
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#define NV_PGRAPH_FD_SWATCH_HT_COUNTER_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_SWATCH_WD_COUNTER 23:16 /* RWXUF */
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#define NV_PGRAPH_FD_SWATCH_WD_COUNTER_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_SWATCH_NEW_SWATH 24:24 /* RWXVF */
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#define NV_PGRAPH_FD_SWATCH_NEW_SWATH_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_FD_SWATCH_NEW_SWATH_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_FD_SWATCH_NEW_SWATH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_SWATCH_SKIP_FIRST_ROW 25:25 /* RWXVF */
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#define NV_PGRAPH_FD_SWATCH_SKIP_FIRST_ROW_FALSE 0x00000000 /* RW--V */
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#define NV_PGRAPH_FD_SWATCH_SKIP_FIRST_ROW_TRUE 0x00000001 /* RW--V */
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#define NV_PGRAPH_FD_SWATCH_SKIP_FIRST_ROW_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_SWATCH_SHORT_SWATCH 26:26 /* RWXVF */
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#define NV_PGRAPH_FD_SWATCH_SHORT_SWATCH_FULL_HEIGHT 0x00000000 /* RW--V */
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#define NV_PGRAPH_FD_SWATCH_SHORT_SWATCH_PARTIAL_HEIGHT 0x00000001 /* RW--V */
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#define NV_PGRAPH_FD_SWATCH_SHORT_SWATCH_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_EXTRAS 0x00400F68 /* RW-4R */
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#define NV_PGRAPH_FD_EXTRAS_TRANSITION_COUNTER 2:0 /* RWXUF */
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#define NV_PGRAPH_FD_EXTRAS_TRANSITION_COUNTER_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_EXTRAS_TRANSITION_TOTAL 6:4 /* RWXUF */
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#define NV_PGRAPH_FD_EXTRAS_TRANSITION_TOTAL_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_EXTRAS_PT_SPEC0 27:24 /* RWXUF */
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#define NV_PGRAPH_FD_EXTRAS_PT_SPEC0_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_FD_EXTRAS_PT_SPEC1 31:28 /* RWXUF */
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#define NV_PGRAPH_FD_EXTRAS_PT_SPEC1_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_EMISSION_BACKUP_0 0x00400F6C /* RW-4R */
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#define NV_PGRAPH_EMISSION_BACKUP_0_V 31:0 /* RWXFF */
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#define NV_PGRAPH_EMISSION_BACKUP_0_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_EMISSION_BACKUP_1 0x00400F70 /* RW-4R */
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#define NV_PGRAPH_EMISSION_BACKUP_1_V 31:0 /* RWXFF */
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#define NV_PGRAPH_EMISSION_BACKUP_1_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_EMISSION_BACKUP_2 0x00400F74 /* RW-4R */
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#define NV_PGRAPH_EMISSION_BACKUP_2_V 31:0 /* RWXFF */
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#define NV_PGRAPH_EMISSION_BACKUP_2_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_0 0x00400F78 /* RW-4R */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_0_V 31:0 /* RWXFF */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_0_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_1 0x00400F7C /* RW-4R */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_1_V 31:0 /* RWXFF */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_1_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_2 0x00400F80 /* RW-4R */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_2_V 31:0 /* RWXFF */
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#define NV_PGRAPH_SCENE_AMBIENT_BACKUP_2_V_097 0x00000000 /* RWC-V */
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#define NV_PGRAPH_GETSTATE 0x00400F84 /* RW-4R */
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#define NV_PGRAPH_GETSTATE_DMA_INSTANCE 15:0 /* RWXUF */
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#define NV_PGRAPH_GETSTATE_DMA_INSTANCE_INVALID 0x0000 /* RW--V */
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#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */
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#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */
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#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */
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#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */
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#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */
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#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */
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#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */
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#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */
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#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */
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#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */
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#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */
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#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */
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#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */
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#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */
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#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */
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#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */
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#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */
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#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */
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#define NV_PGRAPH_DMA_STATE 0x00401034 /* R--4R */
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#define NV_PGRAPH_DMA_STATE_PMA 2:0 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_PMA_DRP 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_PMA_DRA 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_PMA_DWA 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_PMA_DW0 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_PMA_DW1 0x00000004 /* R---V */
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#define NV_PGRAPH_DMA_STATE_PMA_DW2 0x00000005 /* R---V */
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#define NV_PGRAPH_DMA_STATE_PMA_DW3 0x00000006 /* R---V */
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#define NV_PGRAPH_DMA_STATE_PMA_DWX 0x00000007 /* R---V */
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#define NV_PGRAPH_DMA_STATE_FE 4:3 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_FE_0 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_FE_1 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_FE_2 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_FE_3 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_FBA 5:5 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_FBA_DR 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_FBA_DW 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA 11:8 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DRDMA_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_REQ 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_TIME_REQ 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_ADJ 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_TLB 0x00000004 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_PTE_REQ 0x00000005 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_PTE 0x00000006 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_MEM_REQ 0x00000007 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_MEM 0x00000008 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_PITCH 0x00000009 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRDMA_INTR 0x0000000A /* R---V */
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#define NV_PGRAPH_DMA_STATE_DR 13:12 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DR_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DR_TRX 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DR_PART 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRTLB 15:14 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DRTLB_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DRTLB_TLB 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRTLB_LIM 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DRTLB_PTE 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DR_Q_FULL 16:16 /* R-X-F */
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#define NV_PGRAPH_DMA_STATE_DR_Q_EMPTY 17:17 /* R-X-F */
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#define NV_PGRAPH_DMA_STATE_DR_Q_BUSY 18:18 /* R-X-F */
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#define NV_PGRAPH_DMA_STATE_DR_C_FULL 19:19 /* R-X-F */
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#define NV_PGRAPH_DMA_STATE_DWDMA 23:20 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DWDMA_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_ADJ 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_TLB 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_PTE_REQ 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_PTE 0x00000004 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_MEM_REQ 0x00000005 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_MEM 0x00000006 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_PITCH 0x00000007 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_FE_TRX 0x00000008 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWDMA_INTR 0x00000009 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DW 26:24 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DW_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DW_FIRST 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DW_SECOND 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DW_MID 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DW_WAIT 0x00000004 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWTLB 28:27 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DWTLB_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DWTLB_TLB 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWTLB_LIM 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DWTLB_PTE 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DF 31:29 /* R-IVF */
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#define NV_PGRAPH_DMA_STATE_DF_IDLE 0x00000000 /* R-I-V */
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#define NV_PGRAPH_DMA_STATE_DF_REQ 0x00000001 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DF_REQ2 0x00000002 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DF_LO 0x00000003 /* R---V */
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#define NV_PGRAPH_DMA_STATE_DF_HI 0x00000004 /* R---V */
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#define NV_PGRAPH_DMA_RETURN 0x00401038 /* RW-4R */
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#define NV_PGRAPH_DMA_RETURN_VALUE 31:0 /* RWXUF */
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#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */
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#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */
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#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */
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#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */
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#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */
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#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */
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#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */
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#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM_TILED 0x00000001 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */
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#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */
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#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */
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#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */
|
|
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */
|
|
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */
|
|
#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM_TILED 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */
|
|
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */
|
|
#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */
|
|
#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */
|
|
#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */
|
|
/* dev_int_graph.ref */
|
|
#define NV_IGRAPH 0x0001FFFF:0x00000000 /* RW--D */
|
|
#define NV_IGRAPH_ATTR_OFFSET(i) (0x00000000+(i)*8) /* RW-4A */
|
|
#define NV_IGRAPH_ATTR_OFFSET__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_ATTR_OFFSET_OFFSET_FIELD 27:0 /* RWX-F */
|
|
#define NV_IGRAPH_ATTR_OFFSET_CTXDMA_FIELD 31:31 /* RWX-F */
|
|
#define NV_IGRAPH_ATTR_OFFSET_CTXDMA_VTXA 0x0 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_OFFSET_CTXDMA_VTXB 0x1 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT(i) (0x00000004+(i)*8) /* RW-4A */
|
|
#define NV_IGRAPH_ATTR_FORMAT__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_FIELD 2:0 /* RWX-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_UB_D3D 0x0 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_S1 0x1 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_F 0x2 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_UB_OGL 0x4 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_S32K 0x5 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_TYPE_CMP 0x6 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_SIZE_FIELD 6:4 /* RWI-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_DISABLED 0x0 /* RWI-V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_SIZE_1 0x1 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_SIZE_2 0x2 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_SIZE_3 0x3 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_SIZE_4 0x4 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_SIZE_3W 0x7 /* RW--V */
|
|
#define NV_IGRAPH_ATTR_FORMAT_STRIDE_FIELD 15:8 /* RWX-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_CMP_DATA_0H_FIELD 10:0 /* RWI-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_CMP_DATA_0L_FIELD 9:5 /* RWI-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_CMP_DATA_1H_FIELD 21:11 /* RWI-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_CMP_DATA_1L_FIELD 20:16 /* RWI-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_CMP_DATA_2H_FIELD 31:22 /* RWI-F */
|
|
#define NV_IGRAPH_ATTR_FORMAT_CMP_DATA_2L_FIELD 30:25 /* RWI-F */
|
|
#define NV_IGRAPH_PRIM_TYPE 0x00000080 /* RW-4R */
|
|
#define NV_IGRAPH_PRIM_TYPE_FIELD 3:0 /* RWI-F */
|
|
#define NV_IGRAPH_PRIM_TYPE_NONE 0x0 /* RWI-V */
|
|
#define NV_IGRAPH_PRIM_TYPE_POINT 0x1 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_LINE 0x2 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_LINEL 0x3 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_LINES 0x4 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_TRI 0x5 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_TRIS 0x6 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_TRIF 0x7 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_QUAD 0x8 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_QUADS 0x9 /* RW--V */
|
|
#define NV_IGRAPH_PRIM_TYPE_POLY 0xA /* RW--V */
|
|
#define NV_IGRAPH_EDGE_FLAG 0x00000084 /* RW-4R */
|
|
#define NV_IGRAPH_EDGE_FLAG_FIELD 0:0 /* RWI-F */
|
|
#define NV_IGRAPH_EDGE_FLAG_INIT 0x1 /* RWI-V */
|
|
#define NV_IGRAPH_INLINE_VTX_0 0x000000C0 /* -W-4R */
|
|
#define NV_IGRAPH_INLINE_VTX_0_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_INLINE_VTX_1 0x000000C4 /* -W-4R */
|
|
#define NV_IGRAPH_INLINE_VTX_1_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_IDX32_0 0x000000C8 /* -W-4R */
|
|
#define NV_IGRAPH_IDX32_0_FIELD 19:0 /* -W--F */
|
|
#define NV_IGRAPH_IDX32_0_SIGN_FIELD 31:31 /* -W--F */
|
|
#define NV_IGRAPH_IDX32_1 0x000000CC /* -W-4R */
|
|
#define NV_IGRAPH_IDX32_1_FIELD 19:0 /* -W--F */
|
|
#define NV_IGRAPH_IDX32_1_SIGN_FIELD 31:31 /* -W--F */
|
|
#define NV_IGRAPH_VERTEX_FILE_SIZE 0x18 /* ----T */
|
|
#define NV_IGRAPH_MAX_REL_INDEX 0xf /* ----T */
|
|
#define NV_IGRAPH_IDX16_0 0x000000D0 /* -W-4R */
|
|
#define NV_IGRAPH_IDX16_0_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_IDX16_0_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_IDX16_1 0x000000D4 /* -W-4R */
|
|
#define NV_IGRAPH_IDX16_1_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_IDX16_1_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_IDX_ARRAY 0x000000D8 /* -W-4R */
|
|
#define NV_IGRAPH_IDX_ARRAY_BASE_FIELD 19:0 /* -W--F */
|
|
#define NV_IGRAPH_IDX_ARRAY_COUNT_FIELD 31:24 /* -W--F */
|
|
#define NV_IGRAPH_INVALIDATE_CACHE 0x000000F8 /* -W-4R */
|
|
#define NV_IGRAPH_INVALIDATE_CACHE_FIELD 0:0 /* -W--F */
|
|
#define NV_IGRAPH_INVALIDATE_FILE 0x000000FC /* -W-4R */
|
|
#define NV_IGRAPH_INVALIDATE_FILE_FIELD 0:0 /* -W--F */
|
|
#define NV_IGRAPH_STATE_BUNDLE(i) (0x00000800+(i)*4) /* -W-4A */
|
|
#define NV_IGRAPH_STATE_BUNDLE__SIZE_1 512 /* */
|
|
#define NV_IGRAPH_STATE_BUNDLE_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_1UB(i) (0x1100+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_1UB__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_1UB_FIELD 7:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2UB(i) (0x1200+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_2UB__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_2UB_0_FIELD 7:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2UB_1_FIELD 15:8 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3UB(i) (0x1300+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_3UB__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_3UB_0_FIELD 7:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3UB_1_FIELD 15:8 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3UB_2_FIELD 23:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4UB(i) (0x1000+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_4UB__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_4UB_0_FIELD 7:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4UB_1_FIELD 15:8 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4UB_2_FIELD 23:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4UB_3_FIELD 31:24 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_1S32K(i) (0x1500+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_1S32K__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_1S32K_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2S32K(i) (0x1600+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_2S32K__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_2S32K_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2S32K_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3S32K(i) (0x1700+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_3S32K__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_3S32K_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3S32K_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4S32K(i) (0x1400+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_4S32K__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_4S32K_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4S32K_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_1S1(i) (0x1900+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_1S1__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_1S1_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2S1(i) (0x1A00+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_2S1__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_2S1_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2S1_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3S1(i) (0x1B00+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_3S1__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_3S1_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3S1_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4S1(i) (0x1800+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_4S1__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_4S1_0_FIELD 15:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4S1_1_FIELD 31:16 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_1F(i) (0x1D00+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_1F__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_1F_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_2F(i) (0x1E00+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_2F__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_2F_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_3F(i) (0x1F00+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_3F__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_3F_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_VTX_ATTR_4F(i) (0x1C00+(i)*16) /* -W-4A */
|
|
#define NV_IGRAPH_VTX_ATTR_4F__SIZE_1 16 /* */
|
|
#define NV_IGRAPH_VTX_ATTR_4F_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_FD(i) (0x4000+(i)*4) /* RW-4A */
|
|
#define NV_IGRAPH_FD__SIZE_1 4096 /* */
|
|
#define NV_IGRAPH_FD_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_FD2PIPE(c,a) (((c)<<10)|(a)) /* ----T */
|
|
#define NV_IGRAPH_PIPE2FD_CMD(a) (((a)>>10)&31) /* ----T */
|
|
#define NV_IGRAPH_PIPE2FD_ADDR(a) ((a)&0x3ff) /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_END_PATCH 0x16 /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_END_TRANSITION 0x17 /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_REG 0x1a /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_GUARD 0x19 /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_COEFF 0x18 /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_FLUSH 0x1f /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_GO 0x11 /* ----T */
|
|
#define NV_IGRAPH_FD_CMD_NOP 0x10 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_PATCH0 0x00 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_PATCH1 0x04 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_PATCH2 0x10 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_PATCH3 0x14 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_SWATCH 0x20 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_TRANSITION0 0x00 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_TRANSITION1 0x04 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_TRANSITION2 0x30 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_TRANSITION_CONTROL 0x40 /* ----T */
|
|
#define NV_IGRAPH_FD_REG_CURVE 0x50 /* ----T */
|
|
#define NV_IGRAPH_XF(i) (0x10000+(i)*4) /* RW-4A */
|
|
#define NV_IGRAPH_XF__SIZE_1 16384 /* */
|
|
#define NV_IGRAPH_XF_FIELD 31:0 /* -W--F */
|
|
#define NV_IGRAPH_XF_CMD_NOP 0x0 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_VAB 0x1 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_XFPR 0x2 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_LTPR 0x3 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_IBUF 0x4 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_PASSTHR 0x5 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_PROSTART 0x6 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_MODE 0x7 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_RSVD_8 0x8 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_XFCTX 0x9 /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_LTCTX 0xa /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_LTC0 0xb /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_LTC1 0xc /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_LTC2 0xd /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_LTC3 0xe /* ----T */
|
|
#define NV_IGRAPH_XF_CMD_SYNC 0xf /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_POS 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_WGHT 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_NRM 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_DIFF 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_SPEC 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_FOG 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_PS 0x06 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_BDIFF 0x07 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_BSPEC 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT0 0x09 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT1 0x0a /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT2 0x0b /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT3 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT4 0x0d /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT5 0x0e /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_TXT6 0x0f /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_PASS 0x10 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_INVAL 0x1f /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_0 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_1 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_2 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_3 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_4 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_5 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_6 0x06 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_7 0x07 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_8 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_9 0x09 /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_A 0x0a /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_B 0x0b /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_C 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_D 0x0d /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_E 0x0e /* ----T */
|
|
#define NV_IGRAPH_XF_VAB_F 0x0f /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_POS 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_RSVD1 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_RSVD2 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_DIFF 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_SPEC 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_FOG 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_PS 0x06 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_BDIFF 0x07 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_BSPEC 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT0 0x09 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT1 0x0a /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT2 0x0b /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT3 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT4 0x0d /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT5 0x0e /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_TXT6 0x0f /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_PASS 0x10 /* ----T */
|
|
#define NV_IGRAPH_XF_OUT_NOP 0x1f /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_CMAT0 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_PMAT0 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_MMAT0 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_IMMAT0 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_MMAT1 0x10 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_IMMAT1 0x14 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_MMAT2 0x18 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_IMMAT2 0x1c /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_MMAT3 0x20 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_IMMAT3 0x24 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT0 0x28 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT1 0x29 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT2 0x2a /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT3 0x2b /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT4 0x2c /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT5 0x2d /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT6 0x2e /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_LIT7 0x2f /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT0 0x30 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT1 0x31 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT2 0x32 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT3 0x33 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT4 0x34 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT5 0x35 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT6 0x36 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_SPOT7 0x37 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_EYEP 0x38 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_FOG 0x39 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_VPSCL 0x3a /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_VPOFF 0x3b /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_CONS0 0x3c /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_CONS1 0x3d /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_CONS2 0x3e /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_CONS3 0x3f /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_TG0MAT 0x40 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_T0MAT 0x44 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_TG1MAT 0x48 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_T1MAT 0x4c /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_TG2MAT 0x50 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_T2MAT 0x54 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_TG3MAT 0x58 /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_T3MAT 0x5c /* ----T */
|
|
#define NV_IGRAPH_XF_XFCTX_PRSPACE 0x60 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_AMB 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_DIF 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_SPC 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_K 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_SPT 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_BAMB 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_BDIF 0x06 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L0_BSPC 0x07 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_AMB 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_DIF 0x09 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_SPC 0x0a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_K 0x0b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_SPT 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_BAMB 0x0d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_BDIF 0x0e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L1_BSPC 0x0f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_AMB 0x10 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_DIF 0x11 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_SPC 0x12 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_K 0x13 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_SPT 0x14 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_BAMB 0x15 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_BDIF 0x16 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L2_BSPC 0x17 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_AMB 0x18 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_DIF 0x19 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_SPC 0x1a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_K 0x1b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_SPT 0x1c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_BAMB 0x1d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_BDIF 0x1e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L3_BSPC 0x1f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_AMB 0x20 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_DIF 0x21 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_SPC 0x22 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_K 0x23 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_SPT 0x24 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_BAMB 0x25 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_BDIF 0x26 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L4_BSPC 0x27 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_AMB 0x28 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_DIF 0x29 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_SPC 0x2a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_K 0x2b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_SPT 0x2c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_BAMB 0x2d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_BDIF 0x2e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L5_BSPC 0x2f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_AMB 0x30 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_DIF 0x31 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_SPC 0x32 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_K 0x33 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_SPT 0x34 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_BAMB 0x35 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_BDIF 0x36 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L6_BSPC 0x37 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_AMB 0x38 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_DIF 0x39 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_SPC 0x3a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_K 0x3b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_SPT 0x3c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_BAMB 0x3d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_BDIF 0x3e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_L7_BSPC 0x3f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_EYED 0x40 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_FR_AMB 0x41 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_BR_AMB 0x42 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_CM_COL 0x43 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_BCM_COL 0x44 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_FOG_K 0x45 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_ZERO 0x46 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_PT0 0x47 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_PT1 0x48 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_FOGLIN 0x49 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_VPOFFSET 0x4a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTX_ONE 0x4b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L0_K 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L0_SPT 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L1_K 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L1_SPT 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L2_K 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L2_SPT 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L3_K 0x06 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L3_SPT 0x07 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L4_K 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L4_SPT 0x09 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L5_K 0x0a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L5_SPT 0x0b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L6_K 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L6_SPT 0x0d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L7_K 0x0e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_L7_SPT 0x0f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_EYED 0x10 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_FR_AMB 0x11 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_BR_AMB 0x12 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_CM_COL 0x13 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_BCM_COL 0x14 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_FOG_K 0x15 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_ZERO 0x16 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_PT0 0x17 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXA_FOGLIN 0x18 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L0_AMB 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L0_DIF 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L0_SPC 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L0_BAMB 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L0_BDIF 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L0_BSPC 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L1_AMB 0x06 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L1_DIF 0x07 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L1_SPC 0x08 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L1_BAMB 0x09 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L1_BDIF 0x0a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L1_BSPC 0x0b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L2_AMB 0x0c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L2_DIF 0x0d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L2_SPC 0x0e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L2_BAMB 0x0f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L2_BDIF 0x10 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L2_BSPC 0x11 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L3_AMB 0x12 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L3_DIF 0x13 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L3_SPC 0x14 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L3_BAMB 0x15 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L3_BDIF 0x16 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L3_BSPC 0x17 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L4_AMB 0x18 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L4_DIF 0x19 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L4_SPC 0x1a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L4_BAMB 0x1b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L4_BDIF 0x1c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L4_BSPC 0x1d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L5_AMB 0x1e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L5_DIF 0x1f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L5_SPC 0x20 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L5_BAMB 0x21 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L5_BDIF 0x22 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L5_BSPC 0x23 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L6_AMB 0x24 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L6_DIF 0x25 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L6_SPC 0x26 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L6_BAMB 0x27 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L6_BDIF 0x28 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L6_BSPC 0x29 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L7_AMB 0x2a /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L7_DIF 0x2b /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L7_SPC 0x2c /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L7_BAMB 0x2d /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L7_BDIF 0x2e /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_L7_BSPC 0x2f /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_PT1 0x30 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_ONE 0x31 /* ----T */
|
|
#define NV_IGRAPH_XF_LTCTXB_VPOFFSET 0x32 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC0_ONE0 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC0_MONE 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC0_l1 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC0_Bl1 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_ZERO1 0x00 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_l0 0x01 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_Bl0 0x02 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_PP 0x03 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_r0 0x04 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_r1 0x05 /* ----T */
|
|
#define NV_IGRAPH_XF_LTC1_r2 0x06 /* ----T */
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#define NV_IGRAPH_XF_LTC1_r3 0x07 /* ----T */
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#define NV_IGRAPH_XF_LTC1_r4 0x08 /* ----T */
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#define NV_IGRAPH_XF_LTC1_r5 0x09 /* ----T */
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#define NV_IGRAPH_XF_LTC1_r6 0x0a /* ----T */
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#define NV_IGRAPH_XF_LTC1_r7 0x0b /* ----T */
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#define NV_IGRAPH_XF_LTC1_L0 0x0c /* ----T */
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#define NV_IGRAPH_XF_LTC1_L1 0x0d /* ----T */
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#define NV_IGRAPH_XF_LTC1_L2 0x0e /* ----T */
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#define NV_IGRAPH_XF_LTC1_L3 0x0f /* ----T */
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#define NV_IGRAPH_XF_LTC1_L4 0x10 /* ----T */
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#define NV_IGRAPH_XF_LTC1_L5 0x11 /* ----T */
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#define NV_IGRAPH_XF_LTC1_L6 0x12 /* ----T */
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#define NV_IGRAPH_XF_LTC1_L7 0x13 /* ----T */
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#define NV_IGRAPH_XF_LTC2_ONE2 0x00 /* ----T */
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#define NV_IGRAPH_XF_LTC2_m0 0x01 /* ----T */
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#define NV_IGRAPH_XF_LTC2_Bm0 0x02 /* ----T */
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#define NV_IGRAPH_XF_LTC2_m1 0x03 /* ----T */
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#define NV_IGRAPH_XF_LTC2_Bm1 0x04 /* ----T */
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#define NV_IGRAPH_XF_LTC2_n1 0x05 /* ----T */
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#define NV_IGRAPH_XF_LTC2_Bn1 0x06 /* ----T */
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#define NV_IGRAPH_XF_LTC2_M0 0x07 /* ----T */
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#define NV_IGRAPH_XF_LTC2_M1 0x08 /* ----T */
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#define NV_IGRAPH_XF_LTC2_M2 0x09 /* ----T */
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#define NV_IGRAPH_XF_LTC2_M3 0x0a /* ----T */
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#define NV_IGRAPH_XF_LTC2_M4 0x0b /* ----T */
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#define NV_IGRAPH_XF_LTC2_M5 0x0c /* ----T */
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#define NV_IGRAPH_XF_LTC2_M6 0x0d /* ----T */
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#define NV_IGRAPH_XF_LTC2_M7 0x0e /* ----T */
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#define NV_IGRAPH_XF_LTC3_ZERO3 0x00 /* ----T */
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#define NV_IGRAPH_XF_LTC3_PPADD 0x01 /* ----T */
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#define NV_IGRAPH_XF_LTC3_n0 0x02 /* ----T */
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#define NV_IGRAPH_XF_LTC3_Bn0 0x03 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N0 0x04 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N1 0x05 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N2 0x06 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N3 0x07 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N4 0x08 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N5 0x09 /* ----T */
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#define NV_IGRAPH_XF_LTC3_N6 0x0a /* ----T */
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#define NV_IGRAPH_XF_LTC3_N7 0x0b /* ----T */
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#define NV_IGRAPH_XF_LTC3_MATA 0x0c /* ----T */
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#define NV_IGRAPH_XF_LTC3_BMATA 0x0d /* ----T */
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#define NV_IGRAPH_XF2PIPE(c,a) ((1<<16)|((c)<<12)|(a)) /* ----T */
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#define NV_IGRAPH_PIPE2XF_CMD(a) (((a)>>12)&0xf) /* ----T */
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#define NV_IGRAPH_PIPE2XF_ADDR(a) ((a)&0xfff) /* ----T */
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#define NV_IGRAPH_TC_MISSDEBUG_INDEX_SELECT 0x000000E9 /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_SELECT 0x000000EA /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_CFG0_ADDRESS 0x00000000 /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_CFG1_ADDRESS 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_SELECT_REQ_ADDRESS 0x00000002 /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_SELECT_REQ_BIT 16:16 /* RWIVF */
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#define NV_IGRAPH_TC_MINTFCDEBUG_SELECT_REQ_BIT_DEFAULT 0x0 /* RWI-V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_ZOFFSET_ADDRESS 0x00000003 /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_TILE_ADDRESS(i) (0x0004+(i)) /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_TLIMIT_ADDRESS(i) (0x000c+(i)) /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_TPITCH_ADDRESS(i) (0x0014+(i)) /* RW--V */
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#define NV_IGRAPH_TC_MINTFCDEBUG_ZCOMP_ADDRESS(i) (0x0024+(i)) /* RW--V */
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#define NV_IGRAPH_TC_RBACKDEBUG_INDEX_SELECT 0x000000EB /* RW--V */
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#define NV_IGRAPH_TC_TPA_INDEX_SELECT_FIELD 24:16 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_INDEX_SELECT 0x000000E0 /* RW--V */
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#define NV_IGRAPH_TC_TPB_INDEX_SELECT_FIELD 24:16 /* RWXVF */
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#define NV_IGRAPH_TC_TPB_INDEX_SELECT 0x000000E1 /* RW--V */
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#define NV_IGRAPH_TC_TPA_CLEAR_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_CLEAR_INDEX_ADDRESS 0x00 /* RW--V */
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#define NV_IGRAPH_TC_TPA_CLEAR_FIELD 0:0 /* -W--F */
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#define NV_IGRAPH_TC_TPA_CLEAR_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_4SEC_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_FRC_4SEC_INDEX_ADDRESS 0x01 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_4SEC_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_FRC_4SEC_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_FRC_4SEC_TRUE 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_MISS_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_FRC_MISS_INDEX_ADDRESS 0x02 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_MISS_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_FRC_MISS_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_FRC_MISS_TRUE 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_HIT_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_FRC_HIT_INDEX_ADDRESS 0x03 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_HIT_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_FRC_HIT_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_FRC_HIT_TRUE 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_LAST_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_FRC_LAST_INDEX_ADDRESS 0x04 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_LAST_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_FRC_LAST_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_FRC_LAST_TRUE 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_GT4_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_FRC_GT4_INDEX_ADDRESS 0x05 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_GT4_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_FRC_GT4_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_FRC_GT4_ON 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_FRC_GT4_OFF 0x00000002 /* RW--V */
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#define NV_IGRAPH_TC_TPA_NOSYNC_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_NOSYNC_INDEX_ADDRESS 0x06 /* RW--V */
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#define NV_IGRAPH_TC_TPA_NOSYNC_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_NOSYNC_FALSE 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_NOSYNC_TRUE 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_INDEX_ADDRESS 0x07 /* RW--V */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_FIELD 1:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_NOP 0x00000000 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_HIT 0x00000001 /* RW--V */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_SECMISS 0x00000002 /* RW--V */
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#define NV_IGRAPH_TC_TPA_INUSE_SEL_REPMISS 0x00000003 /* RW--V */
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#define NV_IGRAPH_TC_TPA_DONE0_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_DONE0_INDEX_ADDRESS 0x08 /* RW--V */
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#define NV_IGRAPH_TC_TPA_DONE0_FIELD 31:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_DONE1_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_DONE1_INDEX_ADDRESS 0x09 /* RW--V */
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#define NV_IGRAPH_TC_TPA_DONE1_FIELD 31:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_DONE2_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_DONE2_INDEX_ADDRESS 0x0A /* RW--V */
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#define NV_IGRAPH_TC_TPA_DONE2_FIELD 31:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_DONE3_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_DONE3_INDEX_ADDRESS 0x0B /* RW--V */
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#define NV_IGRAPH_TC_TPA_DONE3_FIELD 31:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_INDEX_ADDRESS 0x0C /* RW--V */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_WAVEID_FIELD 7:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_WAVEID_PEND_FIELD 15:8 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_SYNC0_FIELD 16:16 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_SYNC1_FIELD 17:17 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_SYNC2_FIELD 18:18 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_SYNC3_FIELD 19:19 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_VALID0_FIELD 20:20 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_VALID1_FIELD 21:21 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_VALID2_FIELD 22:22 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_VALID3_FIELD 23:23 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_SYNCWAVE_PEND_FIELD 28:28 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_IDLE_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_IDLE_INDEX_ADDRESS 0x0D /* RW--V */
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#define NV_IGRAPH_TC_TPA_IDLE_X_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_IDLE_T_FIELD 4:4 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_IDLE_R_FIELD 8:8 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_IDLE_D_FIELD 12:12 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_IDLE_W_FIELD 16:16 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_IDLE_TP_FIELD 20:20 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_RBFRDEPTH_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_RBFRDEPTH_INDEX_ADDRESS 0x0E /* RW--V */
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#define NV_IGRAPH_TC_TPA_RBFRDEPTH_FIELD 5:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_RBFRDEPTH_DEFAULT 0x24 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_XBFR_SSTEP_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_XBFR_SSTEP_INDEX_ADDRESS 0x0F /* RW--V */
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#define NV_IGRAPH_TC_TPA_XBFR_SSTEP_FIELD 0:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_XBFR_SSTEP_FALSE 0x0 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_XBFR_SSTEP_TRUE 0x1 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_INDEX_ADDRESS 0x10 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_FIELD 3:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_REPLACE 0x0 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_SECMISS 0x1 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_HIT 0x2 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_REGLD 0x3 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_NOP 0x4 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_PIXEL 0x5 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_GT4 0x6 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_COLLISION 0x7 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMSTATSEL_ISAGP 0x8 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMTEXIDSEL_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_PMTEXIDSEL_INDEX_ADDRESS 0x11 /* RW--V */
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#define NV_IGRAPH_TC_TPA_PMTEXIDSEL_FIELD 3:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_PMTEXIDSEL_DEFAULT 0xf /* RW--V */
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#define NV_IGRAPH_TC_TPA_XBFRDEPTH_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_XBFRDEPTH_INDEX_ADDRESS 0x12 /* RW--V */
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#define NV_IGRAPH_TC_TPA_XBFRDEPTH_FIELD 4:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_XBFRDEPTH_DEFAULT 0x1f /* RWI-V */
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#define NV_IGRAPH_TC_TPA_WAVEIDDEPTH_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_WAVEIDDEPTH_INDEX_ADDRESS 0x13 /* RW--V */
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#define NV_IGRAPH_TC_TPA_WAVEIDDEPTH_FIELD 4:0 /* RWIVF */
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#define NV_IGRAPH_TC_TPA_WAVEIDDEPTH_DEFAULT 0x16 /* RWI-V */
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#define NV_IGRAPH_TC_TPA_DXTDITH_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
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#define NV_IGRAPH_TC_TPA_DXTDITH_INDEX_ADDRESS 0x14 /* RW--V */
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#define NV_IGRAPH_TC_TPA_DXTDITH_FIELD 0:0 /* -W--F */
|
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#define NV_IGRAPH_TC_TPA_DXTDITH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_IGRAPH_TC_TPA_DXTDITH_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_IGRAPH_TC_DXP_INDEX_SELECT_FIELD 24:16 /* RWXVF */
|
|
#define NV_IGRAPH_TC_DXP_INDEX_SELECT 0x000000DF /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_BLOCKWEN_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
|
|
#define NV_IGRAPH_TC_DXP_BLOCKWEN_INDEX_ADDRESS 0x00 /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_BLOCKWEN_FIELD 0:0 /* -W--F */
|
|
#define NV_IGRAPH_TC_DXP_BLOCKWEN_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_IGRAPH_TC_DXP_BLOCKWEN_TRUE 0x00000001 /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_DLYRDAFTERWR_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
|
|
#define NV_IGRAPH_TC_DXP_DLYRDAFTERWR_INDEX_ADDRESS 0x01 /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_DLYRDAFTERWR_FIELD 0:0 /* -W--F */
|
|
#define NV_IGRAPH_TC_DXP_DLYRDAFTERWR_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_IGRAPH_TC_DXP_DLYRDAFTERWR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_DXTDITH_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
|
|
#define NV_IGRAPH_TC_DXP_DXTDITH_INDEX_ADDRESS 0x02 /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_DXTDITH_FIELD 0:0 /* -W--F */
|
|
#define NV_IGRAPH_TC_DXP_DXTDITH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_IGRAPH_TC_DXP_DXTDITH_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_IGRAPH_TC_SHLAT_INDEX_SELECT_FIELD 24:16 /* RWXVF */
|
|
#define NV_IGRAPH_TC_SHLAT_INDEX_SELECT 0x000000EC /* RW--V */
|
|
#define NV_IGRAPH_TC_SHLAT_HIWATER_INDEX_ADDRESS_FIELD 12:2 /* RWXVF */
|
|
#define NV_IGRAPH_TC_SHLAT_HIWATER_INDEX_ADDRESS 0x00 /* RW--V */
|
|
#define NV_IGRAPH_TC_SHLAT_HIWATER_FIELD 7:0 /* RWIVF */
|
|
#define NV_IGRAPH_TC_SHLAT_HIWATER_DEFAULT 0x77 /* RWI-V */
|
|
/* dev_video.ref */
|
|
#define NV_PVIDEO 0x00008FFF:0x00008000 /* RW--D */
|
|
#define NV_PVIDEO_DEBUG_0 0x00008080 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_0_HLF_RATE_ROW_RD 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_0_HLF_RATE_ROW_RD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_0_HLF_RATE_ROW_RD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_0_LIMIT_CHECK 4:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_0_LIMIT_CHECK_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_0_LIMIT_CHECK_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_0_HUE_FOLD 8:8 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_0_HUE_FOLD_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_0_HUE_FOLD_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_0_ODD_FIELD_TOP 12:12 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_0_ODD_FIELD_TOP_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_0_ODD_FIELD_TOP_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_1 0x00008084 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_1_REQ_DELAY 10:0 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_1_REQ_DELAY_DEFAULT 0x00000064 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_1_REQ_DELAY_INIT 0x00000050 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_2 0x00008088 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_2_BURST1 11:6 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_2_BURST1_DEFAULT 0x00000008 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_2_BURST1_INIT 0x00000010 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_2_BURST2 27:22 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_2_BURST2_DEFAULT 0x00000010 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_2_BURST2_INIT 0x00000018 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_3 0x0000808c /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_3_WATER_MARK1 11:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_3_WATER_MARK1_DEFAULT 0x0000004b /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_3_WATER_MARK1_INIT 0x00000040 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_3_WATER_MARK2 27:20 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_3_WATER_MARK2_DEFAULT 0x0000003b /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_3_WATER_MARK2_INIT 0x00000040 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_4 0x00008090 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_4_V_COEFF_B 23:5 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_4_V_COEFF_B_DEFAULT 0x0000b505 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_4_V_COEFF_B_ALWAYS 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_4_V_COEFF_B_NEVER 0x0007ffff /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_5 0x00008094 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_5_H_L_COEFF_D 21:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_5_H_L_COEFF_D_DEFAULT 0x00018816 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_5_H_L_COEFF_D_ALWAYS 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_5_H_L_COEFF_D_NEVER 0x0003ffff /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_6 0x00008098 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_6_H_L_COEFF_C 21:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_6_H_L_COEFF_C_DEFAULT 0x00012c73 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_6_H_L_COEFF_C_ALWAYS 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_6_H_L_COEFF_C_NEVER 0x0003ffff /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_7 0x0000809c /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_7_H_L_COEFF_B 21:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_7_H_L_COEFF_B_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_7_H_L_COEFF_B_ALWAYS 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_7_H_L_COEFF_B_NEVER 0x0003ffff /* RW--V */
|
|
#define NV_PVIDEO_DEBUG_8 0x000080a0 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_8_PIPE_FILL 10:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_8_PIPE_FILL_DEFAULT 0x0000000b /* RWI-V */
|
|
#define NV_PVIDEO_DEBUG_9 0x000080a4 /* RW-4R */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_TRUE 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_UNDERFLOW_RESET 0x00000001 /* -W--C */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_OVERFLOW 4:4 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_TRUE 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_A_OVERFLOW_RESET 0x00000001 /* -W--C */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW 8:8 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_TRUE 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_UNDERFLOW_RESET 0x00000001 /* -W--C */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_OVERFLOW 12:12 /* RWIVF */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_TRUE 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_9_FIFO_B_OVERFLOW_RESET 0x00000001 /* -W--C */
|
|
#define NV_PVIDEO_DEBUG_10 0x000080a8 /* R--4R */
|
|
#define NV_PVIDEO_DEBUG_10_SCREEN_LINE 12:0 /* R-XVF */
|
|
#define NV_PVIDEO_DEBUG_10_SCREEN_LINE_FIRST 0x00000000 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_10_SCAN_COUNT 20:16 /* R-XVF */
|
|
#define NV_PVIDEO_DEBUG_10_SCAN_COUNT_FIRST 0x00000000 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_10_SCAN_COUNT_OVERFLOW 0x00000010 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_10_SCANNING 25:24 /* R-XVF */
|
|
#define NV_PVIDEO_DEBUG_10_SCANNING_NEITHER 0x00000000 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_10_SCANNING_BUFFER_0 0x00000002 /* R---V */
|
|
#define NV_PVIDEO_DEBUG_10_SCANNING_BUFFER_1 0x00000003 /* R---V */
|
|
#define NV_PVIDEO_INTR 0x00008100 /* RW-4R */
|
|
#define NV_PVIDEO_INTR_BUFFER_0 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_INTR_BUFFER_0_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_INTR_BUFFER_0_PENDING 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_INTR_BUFFER_0_RESET 0x00000001 /* -W--C */
|
|
#define NV_PVIDEO_INTR_BUFFER_1 4:4 /* RWIVF */
|
|
#define NV_PVIDEO_INTR_BUFFER_1_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_INTR_BUFFER_1_PENDING 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_INTR_BUFFER_1_RESET 0x00000001 /* -W--C */
|
|
#define NV_PVIDEO_INTR_REASON 0x00008104 /* R--4R */
|
|
#define NV_PVIDEO_INTR_REASON_BUFFER_0 0:0 /* R-IVF */
|
|
#define NV_PVIDEO_INTR_REASON_BUFFER_0_NOTIFICATION 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_INTR_REASON_BUFFER_0_PROTECTION_FAULT 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_INTR_REASON_BUFFER_1 4:4 /* R-IVF */
|
|
#define NV_PVIDEO_INTR_REASON_BUFFER_1_NOTIFICATION 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_INTR_REASON_BUFFER_1_PROTECTION_FAULT 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_INTR_EN 0x00008140 /* RW-4R */
|
|
#define NV_PVIDEO_INTR_EN_BUFFER_0 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_INTR_EN_BUFFER_0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_INTR_EN_BUFFER_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_INTR_EN_BUFFER_1 4:4 /* RWIVF */
|
|
#define NV_PVIDEO_INTR_EN_BUFFER_1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_INTR_EN_BUFFER_1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_BUFFER 0x00008700 /* RW-4R */
|
|
#define NV_PVIDEO_BUFFER_0_USE 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_BUFFER_0_USE_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_BUFFER_0_USE_PENDING 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_BUFFER_0_USE_SET 0x00000001 /* -W--S */
|
|
#define NV_PVIDEO_BUFFER_1_USE 4:4 /* RWIVF */
|
|
#define NV_PVIDEO_BUFFER_1_USE_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PVIDEO_BUFFER_1_USE_PENDING 0x00000001 /* R---V */
|
|
#define NV_PVIDEO_BUFFER_1_USE_SET 0x00000001 /* -W--S */
|
|
#define NV_PVIDEO_STOP 0x00008704 /* RW-4R */
|
|
#define NV_PVIDEO_STOP_OVERLAY 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_STOP_OVERLAY_INACTIVE 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_STOP_OVERLAY_ACTIVE 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_STOP_METHOD 4:4 /* RWIVF */
|
|
#define NV_PVIDEO_STOP_METHOD_IMMEDIATELY 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_STOP_METHOD_NORMALLY 0x00000001 /* RWI-V */
|
|
#define NV_PVIDEO_BASE(i) (0x00008900+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_BASE__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_BASE_VALUE 31:6 /* RWXVF */
|
|
#define NV_PVIDEO_LIMIT(i) (0x00008908+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_LIMIT__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_LIMIT_VALUE 31:6 /* RWXVF */
|
|
#define NV_PVIDEO_LIMIT_VALUE_MAX 0xffffffff /* RW--V */
|
|
#define NV_PVIDEO_LUMINANCE(i) (0x00008910+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_LUMINANCE__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_LUMINANCE_CONTRAST 12:3 /* RWXVF */
|
|
#define NV_PVIDEO_LUMINANCE_CONTRAST_47 0x00000200 /* RWC-V */
|
|
#define NV_PVIDEO_LUMINANCE_CONTRAST_83 0x00000200 /* RWC-V */
|
|
#define NV_PVIDEO_LUMINANCE_CONTRAST_UNITY 0x00000200 /* RW--V */
|
|
#define NV_PVIDEO_LUMINANCE_BRIGHTNESS 25:16 /* RWXVF */
|
|
#define NV_PVIDEO_LUMINANCE_BRIGHTNESS_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_LUMINANCE_BRIGHTNESS_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_LUMINANCE_BRIGHTNESS_UNITY 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_CHROMINANCE(i) (0x00008918+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_CHROMINANCE__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_COS 13:2 /* RWXVF */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_COS_47 0x00000400 /* RWC-V */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_COS_83 0x00000400 /* RWC-V */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_COS_UNITY 0x00000400 /* RW--V */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_SIN 29:18 /* RWXVF */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_SIN_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_SIN_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_CHROMINANCE_SAT_SIN_UNITY 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_OFFSET(i) (0x00008920+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_OFFSET__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_OFFSET_VALUE 31:6 /* RWXVF */
|
|
#define NV_PVIDEO_OFFSET_VALUE_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_OFFSET_VALUE_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_OFFSET_VALUE_ZERO 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_SIZE_IN(i) (0x00008928+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_SIZE_IN__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_SIZE_IN_WIDTH 10:1 /* RWXVF */
|
|
#define NV_PVIDEO_SIZE_IN_WIDTH_47 0x00000001 /* RWC-V */
|
|
#define NV_PVIDEO_SIZE_IN_WIDTH_83 0x00000001 /* RWC-V */
|
|
#define NV_PVIDEO_SIZE_IN_HEIGHT 26:16 /* RWXVF */
|
|
#define NV_PVIDEO_SIZE_IN_HEIGHT_47 0x00000002 /* RWC-V */
|
|
#define NV_PVIDEO_SIZE_IN_HEIGHT_83 0x00000002 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_IN(i) (0x00008930+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_POINT_IN__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_POINT_IN_S 14:0 /* RWXVF */
|
|
#define NV_PVIDEO_POINT_IN_S_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_IN_S_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_IN_S_ORIGIN 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_POINT_IN_T 31:17 /* RWXVF */
|
|
#define NV_PVIDEO_POINT_IN_T_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_IN_T_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_IN_T_ORIGIN 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_DS_DX(i) (0x00008938+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_DS_DX__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_DS_DX_RATIO 23:3 /* RWXVF */
|
|
#define NV_PVIDEO_DS_DX_RATIO_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_DS_DX_RATIO_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_DS_DX_RATIO_UNITY 0x00020000 /* RW--V */
|
|
#define NV_PVIDEO_DT_DY(i) (0x00008940+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_DT_DY__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_DT_DY_RATIO 23:4 /* RWXVF */
|
|
#define NV_PVIDEO_DT_DY_RATIO_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_DT_DY_RATIO_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_DT_DY_RATIO_UNITY 0x00010000 /* RW--V */
|
|
#define NV_PVIDEO_POINT_OUT(i) (0x00008948+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_POINT_OUT__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_POINT_OUT_X 11:0 /* RWXVF */
|
|
#define NV_PVIDEO_POINT_OUT_X_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_OUT_X_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_OUT_X_ORIGIN 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_POINT_OUT_Y 27:16 /* RWXVF */
|
|
#define NV_PVIDEO_POINT_OUT_Y_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_OUT_Y_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_POINT_OUT_Y_ORIGIN 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_SIZE_OUT(i) (0x00008950+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_SIZE_OUT__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_SIZE_OUT_WIDTH 11:0 /* RWXVF */
|
|
#define NV_PVIDEO_SIZE_OUT_WIDTH_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_SIZE_OUT_WIDTH_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_SIZE_OUT_HEIGHT 27:16 /* RWXVF */
|
|
#define NV_PVIDEO_SIZE_OUT_HEIGHT_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_SIZE_OUT_HEIGHT_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT(i) (0x00008958+(i)*4) /* RW-4A */
|
|
#define NV_PVIDEO_FORMAT__SIZE_1 2 /* */
|
|
#define NV_PVIDEO_FORMAT_PITCH 12:6 /* RWXVF */
|
|
#define NV_PVIDEO_FORMAT_PITCH_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_PITCH_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_COLOR 17:16 /* RWXVF */
|
|
#define NV_PVIDEO_FORMAT_COLOR_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_COLOR_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_COLOR_LE_YB8CR8YA8CB8 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_COLOR_LE_EYB8ECR8EYA8ECB8 0x00000002 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_COLOR_LE_ECR8EYB8ECB8EYA8 0x00000003 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_DISPLAY 20:20 /* RWXVF */
|
|
#define NV_PVIDEO_FORMAT_DISPLAY_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_DISPLAY_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_DISPLAY_ALWAYS 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY_EQUAL 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_MATRIX 24:24 /* RWXVF */
|
|
#define NV_PVIDEO_FORMAT_MATRIX_ITURBT601 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_FIELD 28:28 /* RWXVF */
|
|
#define NV_PVIDEO_FORMAT_FIELD_2A 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_FORMAT_FIELD_TOP 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_FORMAT_FIELD_BOTTOM 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_COLOR_KEY 0x00008b00 /* RW-4R */
|
|
#define NV_PVIDEO_COLOR_KEY_VALUE 31:0 /* RWXVF */
|
|
#define NV_PVIDEO_COLOR_KEY_VALUE_47 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_COLOR_KEY_VALUE_83 0x00000000 /* RWC-V */
|
|
#define NV_PVIDEO_COLOR_KEY_VALUE_DONT_CARE 0x00000000 /* RW--V */
|
|
#define NV_PVIDEO_TEST 0x00008d00 /* RW-4R */
|
|
#define NV_PVIDEO_TEST_MODE 0:0 /* RWIVF */
|
|
#define NV_PVIDEO_TEST_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_TEST_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_TEST_ADDRESS 15:8 /* RWXVF */
|
|
#define NV_PVIDEO_TST_WRITE(i) (0x00008d10+(i)*4) /* -W-4A */
|
|
#define NV_PVIDEO_TST_WRITE__SIZE_1 12 /* */
|
|
#define NV_PVIDEO_TST_WRITE_VALUE 31:0 /* -WXVF */
|
|
#define NV_PVIDEO_TST_READ(i) (0x00008d40+(i)*4) /* R--4A */
|
|
#define NV_PVIDEO_TST_READ__SIZE_1 12 /* */
|
|
#define NV_PVIDEO_TST_READ_VALUE 31:0 /* R-XVF */
|
|
#define NV_PVIDEO_RCR 0x00008d70 /* RW-4R */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ 7:0 /* RWIVF */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_NONE 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_4B 0x00000001 /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_8B 0x00000003 /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_16B 0x00000007 /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_32B 0x0000000f /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_64B 0x0000001f /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_128B 0x0000003f /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_256B 0x0000007f /* RW--V */
|
|
#define NV_PVIDEO_RCR_RNDM_REQ_512B 0x000000ff /* RW--V */
|
|
#define NV_PVIDEO_RCR_MBI 16:16 /* RWIVF */
|
|
#define NV_PVIDEO_RCR_MBI_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PVIDEO_RCR_MBI_ENABLE 0x00000001 /* RW--V */
|
|
/* dev_multichip_bridge.ref */
|
|
#define NV_PBRIDGE 0x0000CFFF:0x0000C000 /* RW--D */
|
|
#define NV_PBRIDGE_SYS_CONFIG 0x0000C800 /* R-X4R */
|
|
#define NV_PBRIDGE_SYS_CONFIG_NUM_DEVICES 2:0 /* R-XVF */
|
|
#define NV_PBRIDGE_SYS_CONFIG_DEVICE_NUM 6:4 /* R-XVF */
|
|
#define NV_PBRIDGE_SYS_CONFIG_NUM_DOWNSTREAM_DEVICES 10:8 /* R-XVF */
|
|
#define NV_PBRIDGE_SYS_CONFIG_TYPE 12:12 /* R-XVF */
|
|
#define NV_PBRIDGE_SYS_CONFIG_TYPE_INTEGRATED 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_SYS_CONFIG_TYPE_STANDALONE 0x00000001 /* RW--V */
|
|
#define NV_PBRIDGE_ARBITER 0x0000C810 /* RWI4R */
|
|
#define NV_PBRIDGE_ARBITER_BRG_XACTIONS 3:0 /* RWIVF */
|
|
#define NV_PBRIDGE_ARBITER_BRG_XACTIONS_DEFAULT 0x00000004 /* RWI-V */
|
|
#define NV_PBRIDGE_ARBITER_BRG_PRIORITY 7:4 /* RWIVF */
|
|
#define NV_PBRIDGE_ARBITER_BRG_PRIORITY_DEFAULT 0x00000002 /* RWI-V */
|
|
#define NV_PBRIDGE_ARBITER_LOC_XACTIONS 11:8 /* RWIVF */
|
|
#define NV_PBRIDGE_ARBITER_LOC_XACTIONS_DEFAULT 0x00000004 /* RWI-V */
|
|
#define NV_PBRIDGE_ARBITER_LOC_PRIORITY 15:12 /* RWIVF */
|
|
#define NV_PBRIDGE_ARBITER_LOC_PRIORITY_DEFAULT 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_ARBITER_REM_XACTIONS 19:16 /* RWIVF */
|
|
#define NV_PBRIDGE_ARBITER_REM_XACTIONS_DEFAULT 0x00000004 /* RWI-V */
|
|
#define NV_PBRIDGE_ARBITER_REM_PRIORITY 23:20 /* RWIVF */
|
|
#define NV_PBRIDGE_ARBITER_REM_PRIORITY_DEFAULT 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MIN 0x0000C900 /* RWI4R */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MIN_ADDR 31:6 /* RWIVF */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MIN_ADDR_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MAX 0x0000C910 /* RWI4R */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MAX_ADDR 31:6 /* RWIVF */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MAX_ADDR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_REDIRECT_RANGE_MAX_ADDR_ZERO 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MIN 0x0000C920 /* RWI4R */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MIN_ADDR 31:6 /* RWIVF */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MIN_ADDR_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MAX 0x0000C930 /* RWI4R */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MAX_ADDR 31:6 /* RWIVF */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MAX_ADDR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_REDIRECT_LOCAL_MAX_ADDR_ZERO 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO 0x0000CA00 /* RWI4R */
|
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#define NV_PBRIDGE_GPIO_0_OUTPUT 0:0 /* RWI-F */
|
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#define NV_PBRIDGE_GPIO_0_OUTPUT_0 0x00000000 /* RWI-V */
|
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#define NV_PBRIDGE_GPIO_0_ENABLE 1:1 /* R---F */
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#define NV_PBRIDGE_GPIO_0_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
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#define NV_PBRIDGE_GPIO_0_ENABLE_ENABLE 0x00000000 /* RW--V */
|
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#define NV_PBRIDGE_GPIO_0_INPUT 2:2 /* R---F */
|
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#define NV_PBRIDGE_GPIO_1_OUTPUT 4:4 /* RWI-F */
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#define NV_PBRIDGE_GPIO_1_OUTPUT_0 0x00000000 /* RWI-V */
|
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#define NV_PBRIDGE_GPIO_1_ENABLE 5:5 /* R---F */
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#define NV_PBRIDGE_GPIO_1_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
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#define NV_PBRIDGE_GPIO_1_ENABLE_ENABLE 0x00000000 /* RW--V */
|
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#define NV_PBRIDGE_GPIO_1_INPUT 6:6 /* R---F */
|
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#define NV_PBRIDGE_GPIO_2_OUTPUT 8:8 /* RWI-F */
|
|
#define NV_PBRIDGE_GPIO_2_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_2_ENABLE 9:9 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_2_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_2_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO_2_INPUT 10:10 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_3_OUTPUT 12:12 /* RWI-F */
|
|
#define NV_PBRIDGE_GPIO_3_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_3_ENABLE 13:13 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_3_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_3_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO_3_INPUT 14:14 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_4_OUTPUT 16:16 /* RWI-F */
|
|
#define NV_PBRIDGE_GPIO_4_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_4_ENABLE 17:17 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_4_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_4_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO_4_INPUT 18:18 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_5_OUTPUT 20:20 /* RWI-F */
|
|
#define NV_PBRIDGE_GPIO_5_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_5_ENABLE 21:21 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_5_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_5_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO_5_INPUT 22:22 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_6_OUTPUT 24:24 /* RWI-F */
|
|
#define NV_PBRIDGE_GPIO_6_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_6_ENABLE 25:25 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_6_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_6_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO_6_INPUT 26:26 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_7_OUTPUT 28:28 /* RWI-F */
|
|
#define NV_PBRIDGE_GPIO_7_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_7_ENABLE 29:29 /* R---F */
|
|
#define NV_PBRIDGE_GPIO_7_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PBRIDGE_GPIO_7_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PBRIDGE_GPIO_7_INPUT 30:30 /* R---F */
|
|
/* dev_vga.ref */
|
|
#define NV_PRMCIO 0x00601FFF:0x00601000 /* RW--D */
|
|
#define NV_PRMCIO_INP0 0x006013c2 /* R--1R */
|
|
#define NV_PRMCIO_INP0__MONO 0x006013ba /* R--1R */
|
|
#define NV_PRMCIO_INP0__COLOR 0x006013da /* R--1R */
|
|
#define NV_PRMCIO_INP0__READ_MONO 0x006013ca /* R--1R */
|
|
#define NV_PRMCIO_INP0__WRITE_MONO 0x006013ba /* -W-1R */
|
|
#define NV_PRMCIO_INP0__WRITE_COLOR 0x006013da /* -W-1R */
|
|
#define NV_PRMCIO_ARX 0x006013c0 /* RW-1R */
|
|
#define NV_PRMCIO_AR_PALETTE__WRITE 0x006013c0 /* -W-1R */
|
|
#define NV_PRMCIO_AR_PALETTE__READ 0x006013c1 /* R--1R */
|
|
#define NV_PRMCIO_AR_MODE__WRITE 0x006013c0 /* -W-1R */
|
|
#define NV_PRMCIO_AR_MODE__READ 0x006013c1 /* R--1R */
|
|
#define NV_PRMCIO_AR_MODE_INDEX 0x00000010 /* */
|
|
#define NV_PRMCIO_AR_OSCAN__WRITE 0x006013c0 /* -W-1R */
|
|
#define NV_PRMCIO_AR_OSCAN__READ 0x006013c1 /* R--1R */
|
|
#define NV_PRMCIO_AR_OSCAN_INDEX 0x00000011 /* */
|
|
#define NV_PRMCIO_AR_PLANE__WRITE 0x006013c0 /* -W-1R */
|
|
#define NV_PRMCIO_AR_PLANE__READ 0x006013c1 /* R--1R */
|
|
#define NV_PRMCIO_AR_PLANE_INDEX 0x00000012 /* */
|
|
#define NV_PRMCIO_AR_HPP__WRITE 0x006013c0 /* -W-1R */
|
|
#define NV_PRMCIO_AR_HPP__READ 0x006013c1 /* R--1R */
|
|
#define NV_PRMCIO_AR_HPP_INDEX 0x00000013 /* */
|
|
#define NV_PRMCIO_AR_CSEL__WRITE 0x006013c0 /* -W-1R */
|
|
#define NV_PRMCIO_AR_CSEL__READ 0x006013c1 /* R--1R */
|
|
#define NV_PRMCIO_AR_CSEL_INDEX 0x00000014 /* */
|
|
#define NV_PRMCIO_CRX__MONO 0x006013b4 /* RW-1R */
|
|
#define NV_PRMCIO_CRX__COLOR 0x006013d4 /* RW-1R */
|
|
#define NV_PRMCIO_CR__MONO 0x006013b5 /* RW-1R */
|
|
#define NV_PRMCIO_CR__COLOR 0x006013d5 /* RW-1R */
|
|
#define NV_PRMCIO_CRE__MONO 0x006013b5 /* RW-1R */
|
|
#define NV_PRMCIO_CRE__COLOR 0x006013d5 /* RW-1R */
|
|
/* dev_vga.ref */
|
|
#define NV_PCRTC_INTR_0 0x00600100 /* RWI4R */
|
|
#define NV_PCRTC_INTR_0_VBLANK 0:0 /* RWI-F */
|
|
#define NV_PCRTC_INTR_0_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PCRTC_INTR_0_VBLANK_PENDING 0x00000001 /* R---V */
|
|
#define NV_PCRTC_INTR_0_VBLANK_RESET 0x00000001 /* -W--V */
|
|
#define NV_PCRTC_INTR_EN_0 0x00600140 /* RWI4R */
|
|
#define NV_PCRTC_INTR_EN_0_VBLANK 0:0 /* RWIVF */
|
|
#define NV_PCRTC_INTR_EN_0_VBLANK_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_INTR_EN_0_VBLANK_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_START 0x00600800 /* RWI4R */
|
|
#define NV_PCRTC_START_ADDRESS 31:2 /* RWI-F */
|
|
#define NV_PCRTC_CONFIG 0x00600804 /* RWI4R */
|
|
#define NV_PCRTC_CONFIG_START_ADDRESS 2:0 /* RWI-F */
|
|
#define NV_PCRTC_CONFIG_START_ADDRESS_VGA 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC 0x00000002 /* RW--V */
|
|
#define NV_PCRTC_CONFIG_ENDIAN 31:31 /* RWI-F */
|
|
#define NV_PCRTC_CONFIG_ENDIAN_LITTLE 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CONFIG_ENDIAN_BIG 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_RASTER 0x00600808 /* R-I4R */
|
|
#define NV_PCRTC_RASTER_POSITION 10:0 /* R---F */
|
|
#define NV_PCRTC_RASTER_SA_LOAD 13:12 /* R---F */
|
|
#define NV_PCRTC_RASTER_SA_LOAD_DISPLAY 0x00000000 /* R---V */
|
|
#define NV_PCRTC_RASTER_SA_LOAD_BEFORE 0x00000001 /* R---V */
|
|
#define NV_PCRTC_RASTER_SA_LOAD_AFTER 0x00000002 /* R---V */
|
|
#define NV_PCRTC_RASTER_VERT_BLANK 16:16 /* R---F */
|
|
#define NV_PCRTC_RASTER_VERT_BLANK_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_PCRTC_RASTER_VERT_BLANK_INACTIVE 0x00000000 /* R---V */
|
|
#define NV_PCRTC_RASTER_FIELD 20:20 /* R---F */
|
|
#define NV_PCRTC_RASTER_FIELD_EVEN 0x00000000 /* R---V */
|
|
#define NV_PCRTC_RASTER_FIELD_ODD 0x00000001 /* R---V */
|
|
#define NV_PCRTC_CURSOR 0x0060080c /* RWI4R */
|
|
#define NV_PCRTC_CURSOR_ADDRESS 31:0 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG 0x00600810 /* RWI4R */
|
|
#define NV_PCRTC_CURSOR_CONFIG_ENABLE 0:0 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_ENABLE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_SCAN_DOUBLE 4:4 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_SCAN_DOUBLE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_SCAN_DOUBLE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE 8:8 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PINST 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_BPP 12:12 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_16 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS 16:16 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_32 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_LINES 27:20 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_32 0x00000020 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 0x00000040 /* RW--V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND 28:28 /* RW--F */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ROP 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ALPHA 0x00000001 /* RW--V */
|
|
#define NV_PCRTC_VIP_RASTER 0x00600814 /* R-I4R */
|
|
#define NV_PCRTC_VIP_RASTER_POSITION 10:0 /* R---F */
|
|
#define NV_PCRTC_GPIO 0x00600818 /* RWI4R */
|
|
#define NV_PCRTC_GPIO_1_OUTPUT 0:0 /* RWI-F */
|
|
#define NV_PCRTC_GPIO_1_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_1_ENABLE 4:4 /* R---F */
|
|
#define NV_PCRTC_GPIO_1_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_1_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PCRTC_GPIO_0_INPUT 8:8 /* R---F */
|
|
#define NV_PCRTC_GPIO_0_OUTPUT 16:16 /* RWI-F */
|
|
#define NV_PCRTC_GPIO_0_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_0_ENABLE 20:20 /* R---F */
|
|
#define NV_PCRTC_GPIO_0_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_0_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PCRTC_GPIO_1_INPUT 24:24 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT 0x0060081C /* RWI4R */
|
|
#define NV_PCRTC_GPIO_EXT_2_OUTPUT 0:0 /* RWI-F */
|
|
#define NV_PCRTC_GPIO_EXT_2_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_2_ENABLE 1:1 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_2_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_2_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PCRTC_GPIO_EXT_2_INPUT 2:2 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_3_OUTPUT 4:4 /* RWI-F */
|
|
#define NV_PCRTC_GPIO_EXT_3_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_3_ENABLE 5:5 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_3_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_3_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PCRTC_GPIO_EXT_3_INPUT 6:6 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_4_OUTPUT 8:8 /* RWI-F */
|
|
#define NV_PCRTC_GPIO_EXT_4_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_4_ENABLE 9:9 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_4_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_4_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PCRTC_GPIO_EXT_4_INPUT 10:10 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_5_OUTPUT 12:12 /* RWI-F */
|
|
#define NV_PCRTC_GPIO_EXT_5_OUTPUT_0 0x00000000 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_5_ENABLE 13:13 /* R---F */
|
|
#define NV_PCRTC_GPIO_EXT_5_ENABLE_DISABLE 0x00000001 /* RWI-V */
|
|
#define NV_PCRTC_GPIO_EXT_5_ENABLE_ENABLE 0x00000000 /* RW--V */
|
|
#define NV_PCRTC_GPIO_EXT_5_INPUT 14:14 /* R---F */
|
|
#define NV_PCRTC_RASTER_START 0x00600830 /* RWI4R */
|
|
#define NV_PCRTC_RASTER_START_VAL 15:0 /* RW--F */
|
|
#define NV_PCRTC_RASTER_POL 31:31 /* RW--F */
|
|
#define NV_PCRTC_RASTER_POL_IN_RANGE 0 /* RWI-V */
|
|
#define NV_PCRTC_RASTER_POL_OUT_RANGE 1 /* RW--V */
|
|
#define NV_PCRTC_RASTER_STOP 0x00600834 /* RWI4R */
|
|
#define NV_PCRTC_RASTER_STOP_VAL 15:0 /* RW--F */
|
|
#define NV_PCRTC_FIFO_CNTRL 0x00600838 /* RWI4R */
|
|
#define NV_PCRTC_FIFO_CNTRL_ADDRESS 6:0 /* RW--F */
|
|
#define NV_PCRTC_FIFO_CNTRL_RAM 12:12 /* RW--F */
|
|
#define NV_PCRTC_FIFO_CNTR_TESTMODE 16:16 /* RW--F */
|
|
#define NV_PCRTC_FIFO_CNTR_TESTMODE_ENABLE 1 /* RW--V */
|
|
#define NV_PCRTC_FIFO_CNTR_TESTMODE_DISABLE 0 /* RW--V */
|
|
#define NV_PCRTC_FIFO_DATA_0 0x00600840 /* RWI4R */
|
|
#define NV_PCRTC_FIFO_DATA_0_VAL 31:0 /* RW--F */
|
|
#define NV_PCRTC_FIFO_DATA_1 0x00600844 /* RWI4R */
|
|
#define NV_PCRTC_FIFO_DATA_1_VAL 31:0 /* RW--F */
|
|
#define NV_PCRTC_FIFO_DATA_2 0x00600848 /* RWI4R */
|
|
#define NV_PCRTC_FIFO_DATA_2_VAL 31:0 /* RW--F */
|
|
#define NV_PCRTC_FIFO_DATA_3 0x0060084c /* RWI4R */
|
|
#define NV_PCRTC_FIFO_DATA_3_VAL 31:0 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL 0x00600860 /* RWI4R */
|
|
#define NV_PCRTC_ENGINE_CTRL_GPIO 0:0 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_GPIO_DEFAULT 0x00000000 /* RWI-F */
|
|
#define NV_PCRTC_ENGINE_CTRL_GPIO_ENABLE 0x00000001 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_I2C 4:4 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_I2C_DEFAULT 0x00000000 /* RWI-F */
|
|
#define NV_PCRTC_ENGINE_CTRL_I2C_ENABLE 0x00000001 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_TV 8:8 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_TV_DEFAULT 0x00000000 /* RWI-F */
|
|
#define NV_PCRTC_ENGINE_CTRL_TV_ENABLE 0x00000001 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_VS 12:12 /* RW--F */
|
|
#define NV_PCRTC_ENGINE_CTRL_VS_DEFAULT 0x00000000 /* RWI-F */
|
|
#define NV_PCRTC_ENGINE_CTRL_VS_ENABLE 0x00000001 /* RW--F */
|
|
/* dev_vga.ref */
|
|
#define NV_CIO 0x3DF:0x3B0 /* ----D */
|
|
#define NV_CIO_INP0 0x000003c2 /* R--1R */
|
|
#define NV_CIO_INP0__MONO 0x000003ba /* R--1R */
|
|
#define NV_CIO_INP0__COLOR 0x000003da /* R--1R */
|
|
#define NV_CIO_INP0__READ_MONO 0x000003ca /* R--1R */
|
|
#define NV_CIO_INP0__WRITE_MONO 0x000003ba /* -W-1R */
|
|
#define NV_CIO_INP0__WRITE_COLOR 0x000003da /* -W-1R */
|
|
#define NV_CIO_ARX 0x000003c0 /* RW-1R */
|
|
#define NV_CIO_AR_PALETTE__WRITE 0x000003c0 /* -W-1R */
|
|
#define NV_CIO_AR_PALETTE__READ 0x000003c1 /* R--1R */
|
|
#define NV_CIO_AR_MODE__WRITE 0x000003c0 /* -W-1R */
|
|
#define NV_CIO_AR_MODE__READ 0x000003c1 /* R--1R */
|
|
#define NV_CIO_AR_MODE_INDEX 0x00000010 /* */
|
|
#define NV_CIO_AR_OSCAN__WRITE 0x000003c0 /* -W-1R */
|
|
#define NV_CIO_AR_OSCAN__READ 0x000003c1 /* R--1R */
|
|
#define NV_CIO_AR_OSCAN_INDEX 0x00000011 /* */
|
|
#define NV_CIO_AR_PLANE__WRITE 0x000003c0 /* -W-1R */
|
|
#define NV_CIO_AR_PLANE__READ 0x000003c1 /* R--1R */
|
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#define NV_CIO_AR_PLANE_INDEX 0x00000012 /* */
|
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#define NV_CIO_AR_HPP__WRITE 0x000003c0 /* -W-1R */
|
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#define NV_CIO_AR_HPP__READ 0x000003c1 /* R--1R */
|
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#define NV_CIO_AR_HPP_INDEX 0x00000013 /* */
|
|
#define NV_CIO_AR_CSEL__WRITE 0x000003c0 /* -W-1R */
|
|
#define NV_CIO_AR_CSEL__READ 0x000003c1 /* R--1R */
|
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#define NV_CIO_AR_CSEL_INDEX 0x00000014 /* */
|
|
#define NV_CIO_CRX__MONO 0x000003b4 /* RW-1R */
|
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#define NV_CIO_CRX__COLOR 0x000003d4 /* RW-1R */
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#define NV_CIO_CR__MONO 0x000003b5 /* RW-1R */
|
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#define NV_CIO_CR__COLOR 0x000003d5 /* RW-1R */
|
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#define NV_CIO_CR_HDT_INDEX 0x00000000 /* */
|
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#define NV_CIO_CR_HDE_INDEX 0x00000001 /* */
|
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#define NV_CIO_CR_HBS_INDEX 0x00000002 /* */
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#define NV_CIO_CR_HBE_INDEX 0x00000003 /* */
|
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#define NV_CIO_CR_HBE_4_0 4:0 /* RW--F */
|
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#define NV_CIO_CR_HRS_INDEX 0x00000004 /* */
|
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#define NV_CIO_CR_HRE_INDEX 0x00000005 /* */
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#define NV_CIO_CR_HRE_HBE_5 7:7 /* RW--F */
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#define NV_CIO_CR_HRE_4_0 4:0 /* RW--F */
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#define NV_CIO_CR_VDT_INDEX 0x00000006 /* */
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#define NV_CIO_CR_OVL_INDEX 0x00000007 /* */
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#define NV_CIO_CR_OVL_VDE_8 1:1 /* RW--F */
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#define NV_CIO_CR_OVL_VDE_9 6:6 /* RW--F */
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#define NV_CIO_CR_OVL_VDT_8 0:0 /* RW--F */
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#define NV_CIO_CR_OVL_VDT_9 5:5 /* RW--F */
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#define NV_CIO_CR_OVL_VBS_8 3:3 /* RW--F */
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#define NV_CIO_CR_OVL_VRS_8 2:2 /* RW--F */
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#define NV_CIO_CR_OVL_VRS_9 7:7 /* RW--F */
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#define NV_CIO_CR_RSAL_INDEX 0x00000008 /* */
|
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#define NV_CIO_CR_RSAL_PANNING 6:5 /* RW--F */
|
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#define NV_CIO_CR_CELL_HT_INDEX 0x00000009 /* */
|
|
#define NV_CIO_CR_CELL_HT_SCANDBL 7:7 /* RW--F */
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#define NV_CIO_CR_CELL_HT_VBS_9 5:5 /* RW--F */
|
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#define NV_CIO_CR_CURS_ST_INDEX 0x0000000A /* */
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#define NV_CIO_CR_CURS_END_INDEX 0x0000000B /* */
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#define NV_CIO_CR_SA_HI_INDEX 0x0000000C /* */
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#define NV_CIO_CR_SA_LO_INDEX 0x0000000D /* */
|
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#define NV_CIO_CR_TCOFF_HI_INDEX 0x0000000E /* */
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#define NV_CIO_CR_TCOFF_LO_INDEX 0x0000000F /* */
|
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#define NV_CIO_CR_VRS_INDEX 0x00000010 /* */
|
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#define NV_CIO_CR_VRE_INDEX 0x00000011 /* */
|
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#define NV_CIO_CR_VRE_3_0 3:0 /* RW--F */
|
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#define NV_CIO_CR_VDE_INDEX 0x00000012 /* */
|
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#define NV_CIO_CR_OFFSET_INDEX 0x00000013 /* */
|
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#define NV_CIO_CR_ULINE_INDEX 0x00000014 /* */
|
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#define NV_CIO_CR_VBS_INDEX 0x00000015 /* */
|
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#define NV_CIO_CR_VBE_INDEX 0x00000016 /* */
|
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#define NV_CIO_CR_MODE_INDEX 0x00000017 /* */
|
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#define NV_CIO_CR_LCOMP_INDEX 0x00000018 /* */
|
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#define NV_CIO_CR_GDATA_INDEX 0x00000022 /* */
|
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#define NV_CIO_CR_ARFF_INDEX 0x00000024 /* */
|
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#define NV_CIO_CR_ARX_INDEX 0x00000026 /* */
|
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#define NV_CIO_CRE__MONO 0x000003b5 /* RW-1R */
|
|
#define NV_CIO_CRE__COLOR 0x000003d5 /* RW-1R */
|
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#define NV_CIO_CRE_RPC0_INDEX 0x00000019 /* */
|
|
#define NV_CIO_CRE_RPC0_START 4:0 /* RW--F */
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|
#define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5 /* RW--F */
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|
#define NV_CIO_CRE_RPC1_INDEX 0x0000001A /* */
|
|
#define NV_CIO_CRE_RPC1_LARGE 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_FF_INDEX 0x0000001B /* */
|
|
#define NV_CIO_CRE_FF_BURST 2:0 /* RW--F */
|
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#define NV_CIO_CRE_FF_BURST_32 0x00000000 /* RW--V */
|
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#define NV_CIO_CRE_FF_BURST_64 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_FF_BURST_128 0x00000002 /* RW--V */
|
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#define NV_CIO_CRE_FF_BURST_256 0x00000003 /* RW--V */
|
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#define NV_CIO_CRE_FF_BURST_512 0x00000004 /* RW--V */
|
|
#define NV_CIO_CRE_FF_BURST_1024 0x00000005 /* RW--V */
|
|
#define NV_CIO_CRE_ENH_INDEX 0x0000001C /* */
|
|
#define NV_CIO_CRE_PAGE0_INDEX 0x0000001D /* */
|
|
#define NV_CIO_CRE_PAGE1_INDEX 0x0000001E /* */
|
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#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */
|
|
#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */
|
|
#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */
|
|
#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */
|
|
#define NV_CIO_CRE_FFLWM__INDEX 0x00000020 /* */
|
|
#define NV_CIO_CRE_FFLWM_LWM 7:0 /* RW--F */
|
|
#define NV_CIO_CRE_FABID_INDEX 0x00000025 /* */
|
|
#define NV_CIO_CRE_LSR_INDEX 0x00000025 /* */
|
|
#define NV_CIO_CRE_LSR_SA_27 7:7 /* RW--F */
|
|
#define NV_CIO_CRE_LSR_SA_26 6:6 /* RW--F */
|
|
#define NV_CIO_CRE_LSR_VDE_10 1:1 /* RW--F */
|
|
#define NV_CIO_CRE_LSR_VDT_10 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_LSR_HBE_6 4:4 /* RW--F */
|
|
#define NV_CIO_CRE_LSR_VBS_10 3:3 /* RW--F */
|
|
#define NV_CIO_CRE_LSR_VRS_10 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_CHIP_ID_INDEX 0x00000027 /* */
|
|
#define NV_CIO_CRE_PIXEL_INDEX 0x00000028 /* */
|
|
#define NV_CIO_CRE_PIXEL_TV_ADJ 5:3 /* RW--F */
|
|
#define NV_CIO_CRE_PIXEL_FORMAT 1:0 /* RW--F */
|
|
#define NV_CIO_CRE_PIXEL_FORMAT_VGA 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_PIXEL_FORMAT_8BPP 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_PIXEL_FORMAT_16BPP 0x00000002 /* RW--V */
|
|
#define NV_CIO_CRE_PIXEL_FORMAT_32BPP 0x00000003 /* RW--V */
|
|
#define NV_CIO_CRE_PAGE_OVFL__INDEX 0x00000029 /* */
|
|
#define NV_CIO_CRE_OSCOL__INDEX 0x0000002A /* */
|
|
#define NV_CIO_CRE_SCRATCH0__INDEX 0x0000002B /* */
|
|
#define NV_CIO_CRE_SCRATCH1__INDEX 0x0000002C /* */
|
|
#define NV_CIO_CRE_HEB__INDEX 0x0000002D /* */
|
|
#define NV_CIO_CRE_HEB_SA_25 7:7 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_SA_24 6:6 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_SA_23 5:5 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_ILC_8 4:4 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_HRS_8 3:3 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_HBS_8 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_HDE_8 1:1 /* RW--F */
|
|
#define NV_CIO_CRE_HEB_HDT_8 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x0000002f /* */
|
|
#define NV_CIO_CRE_HCUR_ADDR2_ADR 7:0 /* RW--F */
|
|
#define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x00000030 /* */
|
|
#define NV_CIO_CRE_HCUR_ASI 7:7 /* RW--F */
|
|
#define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0 /* RW--F */
|
|
#define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x00000031 /* */
|
|
#define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2 /* RW--F */
|
|
#define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1 /* RW--F */
|
|
#define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_VID_END0__INDEX 0x00000032 /* */
|
|
#define NV_CIO_CRE_LCD__INDEX 0x00000033 /* */
|
|
#define NV_CIO_CRE_LCD_LCD_SELECT 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_LCD_EXT_SELECT 4:4 /* RW--F */
|
|
#define NV_CIO_CRE_LCD_STEREO_ENABLE 7:7 /* RW--F */
|
|
#define NV_CIO_GPIO0__INDEX 0x00000034 /* */
|
|
#define NV_CIO_GPIO1__INDEX 0x00000035 /* */
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|
#define NV_CIO_CRE_DDC0_STATUS__INDEX 0x00000036 /* */
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#define NV_CIO_CRE_DDC0_WR__INDEX 0x00000037 /* */
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|
#define NV_CIO_CRE_RMA__INDEX 0x00000038 /* */
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|
#define NV_CIO_CRE_ILACE__INDEX 0x00000039 /* */
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|
#define NV_CIO_CRE_SCRATCH2__INDEX 0x0000003A /* */
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|
#define NV_CIO_CRE_SCRATCH3__INDEX 0x0000003B /* */
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|
#define NV_CIO_CRE_SCRATCH4__INDEX 0x0000003C /* */
|
|
#define NV_CIO_CRE_TREG__INDEX 0x0000003D /* */
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|
#define NV_CIO_CRE_TREG_HCNT 6:6 /* RW--F */
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#define NV_CIO_CRE_TREG_VCNT 4:4 /* RW--F */
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#define NV_CIO_CRE_TREG_SHADOW 0:0 /* RW--F */
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#define NV_CIO_CRE_TREG_HCNT_INDEX 0x00000000 /* */
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#define NV_CIO_CRE_TREG_VCNTA_INDEX 0x00000006 /* */
|
|
#define NV_CIO_CRE_TREG_VCNTB_INDEX 0x00000007 /* */
|
|
#define NV_CIO_CRE_DDC_STATUS__INDEX 0x0000003E /* */
|
|
#define NV_CIO_CRE_DDC_WR__INDEX 0x0000003F /* */
|
|
#define NV_CIO_CRE_PCI_TO__INDEX 0x00000040 /* */
|
|
#define NV_CIO_CRE_PCI_TO_DELAY 7:0 /* -W--F */
|
|
#define NV_CIO_CRE_EBR_INDEX 0x00000041 /* */
|
|
#define NV_CIO_CRE_EBR_VBS_11 6:6 /* RW--F */
|
|
#define NV_CIO_CRE_EBR_VRS_11 4:4 /* RW--F */
|
|
#define NV_CIO_CRE_EBR_VDE_11 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_EBR_VDT_11 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_USA_INDEX 0x00000042 /* */
|
|
#define NV_CIO_CRE_USA_SA__31 3:3 /* RW--F */
|
|
#define NV_CIO_CRE_USA_SA__30 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_USA_SA__29 1:1 /* RW--F */
|
|
#define NV_CIO_CRE_USA_SA__28 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_MBI 0x00000043 /* */
|
|
#define NV_CIO_CRE_MBI_EN 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_MBI_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_MBI_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_H2OWNS 0x00000044 /* */
|
|
#define NV_CIO_CRE_H2OWNS_VGA 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_H2OWNS_VGA_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_H2OWNS_VGA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_H2OWNS_VGA_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_H2OWNS_DAC 1:1 /* RW--F */
|
|
#define NV_CIO_CRE_H2OWNS_DAC_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_H2OWNS_DAC_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_H2OWNS_DAC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_H2OWNS_MIRROR 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_H2OWNS_MIRROR_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_H2OWNS_MIRROR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_H2OWNS_MIRROR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_CSB 0x00000045 /* */
|
|
#define NV_CIO_CRE_CSB_VAL 1:0 /* RW--F */
|
|
#define NV_CIO_CRE_CSB_VAL_NONE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_CSB_VAL_3BY16 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_CSB_VAL_3BY08 0x00000002 /* RW--V */
|
|
#define NV_CIO_CRE_CSB_VAL_3BY04 0x00000003 /* RW--V */
|
|
#define NV_CIO_CRE_RCR 0x00000046 /* */
|
|
#define NV_CIO_CRE_RCR_RNDM_REQ 1:0 /* RW--F */
|
|
#define NV_CIO_CRE_RCR_RNDM_REQ_NONE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_RCR_RNDM_REQ_08 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_RCR_RNDM_REQ_16 0x00000002 /* RW--V */
|
|
#define NV_CIO_CRE_RCR_RNDM_REQ_32 0x00000003 /* RW--V */
|
|
#define NV_CIO_CRE_RCR_ENDIAN 7:7 /* RW--F */
|
|
#define NV_CIO_CRE_RCR_ENDIAN_LITTLE 0x00000000 /* RW--V */
|
|
#define NV_CIO_CRE_RCR_ENDIAN_BIG 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_FFLWM_MSB_INDEX 0x00000047 /* */
|
|
#define NV_CIO_CRE_FFLWM_MSB_LWM 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_EXT_PIXEL_INDEX 0x00000048 /* */
|
|
#define NV_CIO_CRE_EXT_PIXEL_FORMAT 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_EXT_PIXEL_FORMAT_RGB 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_EXT_PIXEL_FORMAT_YUV 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_EXT_PIXEL_YUV_FMT 1:1 /* RW--F */
|
|
#define NV_CIO_CRE_EXT_PIXEL_YUV_FMT_YVYU 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_EXT_PIXEL_YUV_FMT_VYUY 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL 0x00000049 /* */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_GPIO 0:0 /* RW--F */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_GPIO_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_GPIO_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_I2C 2:2 /* RW--F */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_I2C_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_I2C_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_TV 4:4 /* RW--F */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_TV_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_TV_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_VS 6:6 /* RW--F */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_VS_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_CIO_CRE_ENGINE_CTRL_VS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_CIO_CRE_SCRATCH5__INDEX 0x0000004A /* */
|
|
#define NV_CIO_CRE_SCRATCH6__INDEX 0x0000004B /* */
|
|
#define NV_CIO_CRE_SCRATCH7__INDEX 0x0000004C /* */
|
|
#define NV_CIO_GPIO23_INDEX 0x0000004D /* */
|
|
#define NV_CIO_GPIO45_INDEX 0x0000004E /* */
|
|
#define NV_CIO_CRE_DDC2_STATUS__INDEX 0x00000050 /* */
|
|
#define NV_CIO_CRE_DDC2_WR__INDEX 0x00000051 /* */
|
|
#define NV_CIO_CRE_TVOUT_LATENCY 0x00000052 /* */
|
|
/* dev_vga.ref */
|
|
#define NV_VIO_MBEN 0x00000094 /* RW-1R */
|
|
#define NV_VIO_ADDEN 0x000046e8 /* RW-1R */
|
|
#define NV_VIO_VSE1 0x00000102 /* RW-1R */
|
|
#define NV_VIO_VSE2 0x000003c3 /* RW-1R */
|
|
#define NV_VIO_MISC__READ 0x000003cc /* R--1R */
|
|
#define NV_VIO_MISC__WRITE 0x000003c2 /* -W-1R */
|
|
#define NV_VIO_SRX 0x000003c4 /* RW-1R */
|
|
#define NV_VIO_SR_RESET 0x000003c5 /* RW-1R */
|
|
#define NV_VIO_SR_RESET_INDEX 0x00000000 /* V */
|
|
#define NV_VIO_SR_CLOCK 0x000003c5 /* RW-1R */
|
|
#define NV_VIO_SR_CLOCK_INDEX 0x00000001 /* V */
|
|
#define NV_VIO_SR_PLANE_MASK 0x000003c5 /* RW-1R */
|
|
#define NV_VIO_SR_PLANE_MASK_INDEX 0x00000002 /* V */
|
|
#define NV_VIO_SR_CHAR_MAP 0x000003c5 /* RW-1R */
|
|
#define NV_VIO_SR_CHAR_MAP_INDEX 0x00000003 /* */
|
|
#define NV_VIO_SR_MEM_MODE 0x000003c5 /* RW-1R */
|
|
#define NV_VIO_SR_MEM_MODE_INDEX 0x00000004 /* */
|
|
#define NV_VIO_GRX 0x000003ce /* RW-1R */
|
|
#define NV_VIO_GX_SR 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_SR_INDEX 0x00000000 /* */
|
|
#define NV_VIO_GX_SREN 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_SREN_INDEX 0x00000001 /* */
|
|
#define NV_VIO_GX_CCOMP 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_CCOMP_INDEX 0x00000002 /* */
|
|
#define NV_VIO_GX_ROP 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_ROP_INDEX 0x00000003 /* */
|
|
#define NV_VIO_GX_READ_MAP 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_READ_MAP_INDEX 0x00000004 /* */
|
|
#define NV_VIO_GX_MODE 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_MODE_INDEX 0x00000005 /* */
|
|
#define NV_VIO_GX_MISC 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_MISC_INDEX 0x00000006 /* */
|
|
#define NV_VIO_GX_DONT_CARE 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_DONT_CARE_INDEX 0x00000007 /* */
|
|
#define NV_VIO_GX_BIT_MASK 0x000003cf /* RW-1R */
|
|
#define NV_VIO_GX_BIT_MASK_INDEX 0x00000008 /* */
|
|
/* dev_vga.ref */
|
|
#define NV_PRMVIO 0x000C7FFF:0x000C0000 /* RW--D */
|
|
#define NV_PRMVIO_MBEN 0x000C0094 /* RW-1R */
|
|
#define NV_PRMVIO_ADDEN 0x000C46e8 /* RW-1R */
|
|
#define NV_PRMVIO_VSE1 0x000C0102 /* RW-1R */
|
|
#define NV_PRMVIO_VSE2 0x000C03c3 /* RW-1R */
|
|
#define NV_PRMVIO_MISC__READ 0x000C03cc /* R--1R */
|
|
#define NV_PRMVIO_MISC__WRITE 0x000C03c2 /* -W-1R */
|
|
#define NV_PRMVIO_SRX 0x000C03c4 /* RW-1R */
|
|
#define NV_PRMVIO_SR_RESET 0x000C03c5 /* RW-1R */
|
|
#define NV_PRMVIO_SR_RESET_INDEX 0x00000000 /* V */
|
|
#define NV_PRMVIO_SR_CLOCK 0x000C03c5 /* RW-1R */
|
|
#define NV_PRMVIO_SR_CLOCK_INDEX 0x00000001 /* V */
|
|
#define NV_PRMVIO_SR_PLANE_MASK 0x000C03c5 /* RW-1R */
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#define NV_PRMVIO_SR_PLANE_MASK_INDEX 0x00000002 /* V */
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#define NV_PRMVIO_SR_CHAR_MAP 0x000C03c5 /* RW-1R */
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#define NV_PRMVIO_SR_CHAR_MAP_INDEX 0x00000003 /* */
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#define NV_PRMVIO_SR_MEM_MODE 0x000C03c5 /* RW-1R */
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#define NV_PRMVIO_SR_MEM_MODE_INDEX 0x00000004 /* */
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#define NV_PRMVIO_GRX 0x000C03ce /* RW-1R */
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#define NV_PRMVIO_GX_SR 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_SR_INDEX 0x00000000 /* */
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#define NV_PRMVIO_GX_SREN 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_SREN_INDEX 0x00000001 /* */
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#define NV_PRMVIO_GX_CCOMP 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_CCOMP_INDEX 0x00000002 /* */
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#define NV_PRMVIO_GX_ROP 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_ROP_INDEX 0x00000003 /* */
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#define NV_PRMVIO_GX_READ_MAP 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_READ_MAP_INDEX 0x00000004 /* */
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#define NV_PRMVIO_GX_MODE 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_MODE_INDEX 0x00000005 /* */
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#define NV_PRMVIO_GX_MISC 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_MISC_INDEX 0x00000006 /* */
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#define NV_PRMVIO_GX_DONT_CARE 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_DONT_CARE_INDEX 0x00000007 /* */
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#define NV_PRMVIO_GX_BIT_MASK 0x000C03cf /* RW-1R */
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#define NV_PRMVIO_GX_BIT_MASK_INDEX 0x00000008 /* */
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/* dev_vga.ref */
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#define NV_PRMVGA 0x000BFFFF:0x000A0000 /* RW--D */
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/* dev_media.ref */
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#define NV_PME 0x00200FFF:0x00200000 /* RW--D */
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#define NV_PME_INTR_0 0x00200100 /* RWI4R */
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#define NV_PME_INTR_0_TASKA_NOTIFY 0:0 /* RWIVF */
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#define NV_PME_INTR_0_TASKA_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_TASKA_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_TASKA_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_TASKB_NOTIFY 4:4 /* RWIVF */
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#define NV_PME_INTR_0_TASKB_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_TASKB_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_TASKB_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_ANC_NOTIFY 8:8 /* RWIVF */
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#define NV_PME_INTR_0_ANC_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_ANC_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_ANC_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_FOUT_NOTIFY 12:12 /* RWIVF */
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#define NV_PME_INTR_0_FOUT_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_FOUT_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_FOUT_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_FIN_NOTIFY 16:16 /* RWIVF */
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#define NV_PME_INTR_0_FIN_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_FIN_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_FIN_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_FOUTTIMEOUT_NOTIFY 20:20 /* RWIVF */
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#define NV_PME_INTR_0_FOUTTIMEOUT_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_FOUTTIMEOUT_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_FOUTTIMEOUT_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_FINTIMEOUT_NOTIFY 24:24 /* RWIVF */
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#define NV_PME_INTR_0_FINTIMEOUT_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_FINTIMEOUT_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_FINTIMEOUT_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_0_REGTIMEOUT_NOTIFY 28:28 /* RWIVF */
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#define NV_PME_INTR_0_REGTIMEOUT_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PME_INTR_0_REGTIMEOUT_NOTIFY_PENDING 0x00000001 /* R---V */
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#define NV_PME_INTR_0_REGTIMEOUT_NOTIFY_RESET 0x00000001 /* -W--V */
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#define NV_PME_INTR_EN_0 0x00200140 /* RWI4R */
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#define NV_PME_INTR_EN_0_TASKA_NOTIFY 0:0 /* RWIVF */
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#define NV_PME_INTR_EN_0_TASKA_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_TASKA_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_TASKB_NOTIFY 4:4 /* RWIVF */
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#define NV_PME_INTR_EN_0_TASKB_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_TASKB_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_ANC_NOTIFY 8:8 /* RWIVF */
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#define NV_PME_INTR_EN_0_ANC_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_ANC_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_FOUT_NOTIFY 12:12 /* RWIVF */
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#define NV_PME_INTR_EN_0_FOUT_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_FOUT_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_FIN_NOTIFY 16:16 /* RWIVF */
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#define NV_PME_INTR_EN_0_FIN_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_FIN_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_FOUTTIMEOUT_NOTIFY 20:20 /* RWIVF */
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#define NV_PME_INTR_EN_0_FOUTTIMEOUT_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_FOUTTIMEOUT_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_FINTIMEOUT_NOTIFY 24:24 /* RWIVF */
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#define NV_PME_INTR_EN_0_FINTIMEOUT_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_FINTIMEOUT_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_INTR_EN_0_REGTIMEOUT_NOTIFY 28:28 /* RWIVF */
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#define NV_PME_INTR_EN_0_REGTIMEOUT_NOTIFY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PME_INTR_EN_0_REGTIMEOUT_NOTIFY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG 0x00200200 /* RWI4R */
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#define NV_PME_HOST_CONFIG_FIFOMAXTX 5:0 /* RWIVF */
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#define NV_PME_HOST_CONFIG_CLOCK_SELECT 7:7 /* RWIVF */
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#define NV_PME_HOST_CONFIG_CLOCK_SELECT_PCI_DIV_2 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_CLOCK_SELECT_PCI 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_TIMEOUT 11:8 /* RWIVF */
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#define NV_PME_HOST_CONFIG_SLAVE_NOTDETECTED 16:16 /* RWIVF */
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#define NV_PME_HOST_CONFIG_SLAVE_NOTDETECTED_FALSE 0x00000000 /* R---V */
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#define NV_PME_HOST_CONFIG_SLAVE_NOTDETECTED_TRUE 0x00000001 /* R---V */
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#define NV_PME_HOST_CONFIG_SLAVE_DETECTED 20:20 /* RWIVF */
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#define NV_PME_HOST_CONFIG_SLAVE_DETECTED_FALSE 0x00000000 /* R---V */
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#define NV_PME_HOST_CONFIG_SLAVE_DETECTED_TRUE 0x00000001 /* R---V */
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#define NV_PME_HOST_CONFIG_FOUT_SYSMEM 24:24 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FOUT_SYSMEM_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT_SYSMEM_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_SYSMEM 25:25 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FIN_SYSMEM_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_SYSMEM_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT_PAUSE 26:26 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FOUT_PAUSE_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT_PAUSE_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_PAUSE 27:27 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FIN_PAUSE_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_PAUSE_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_VIP_HOST_4X 28:28 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FIN_VIP_HOST_4X_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_VIP_HOST_4X_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT_VIP_HOST_4X 29:29 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FOUT_VIP_HOST_4X_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT_VIP_HOST_4X_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN 30:30 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FIN_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FIN_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT 31:31 /* RWIVF */
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#define NV_PME_HOST_CONFIG_FOUT_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_HOST_CONFIG_FOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_FOUT_ADDR 0x00200204 /* RWI4R */
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#define NV_PME_FOUT_ADDR_FIFO 3:0 /* RWIVF */
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#define NV_PME_FOUT_ADDR_DEVICE 9:8 /* RWIVF */
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#define NV_PME_FIN_ADDR 0x00200208 /* RWI4R */
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#define NV_PME_FIN_ADDR_FIFO 3:0 /* RWIVF */
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#define NV_PME_FIN_ADDR_DEVICE 9:8 /* RWIVF */
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#define NV_PME_656_CONFIG 0x00200400 /* RWI4R */
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#define NV_PME_656_CONFIG_TASKA_ENABLE 0:0 /* RWXUF */
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#define NV_PME_656_CONFIG_TASKB_ENABLE 4:4 /* RWXUF */
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#define NV_PME_656_CONFIG_TASKA_ONLY 6:6 /* RWXUF */
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#define NV_PME_656_CONFIG_TASKA_ONLY_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_TASKA_ONLY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_MODE 9:8 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_MODE_VBI1 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_MODE_VBI2 0x00000002 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_MODE_ANC 0x00000003 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_TASKB 10:10 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_TASKB_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_TASKB_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_TASKB_END 11:11 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_TASKB_END_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_TASKB_END_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_VBI_VERT 12:12 /* RWXUF */
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#define NV_PME_656_CONFIG_VBI_VERT_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_VBI_VERT_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_HNOTV 16:16 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_HNOTV_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_HNOTV_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_NOTHV 17:17 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_NOTHV_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_NOTHV_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_NOTHNOTV 18:18 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_NOTHNOTV_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_NOTHNOTV_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_HV 19:19 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_HV_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_HV_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_IGNORE_PITCH 20:20 /* RWXUF */
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#define NV_PME_656_CONFIG_ANC_IGNORE_PITCH_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_ANC_IGNORE_PITCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_SWAP_UYVY 29:29 /* RWXUF */
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#define NV_PME_656_CONFIG_SWAP_UYVY_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_SWAP_UYVY_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_INVERT_SIGN 30:30 /* RWXUF */
|
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#define NV_PME_656_CONFIG_INVERT_SIGN_DISABLED 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_INVERT_SIGN_ENABLED 0x00000001 /* RW--V */
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#define NV_PME_656_CONFIG_VIDEO 31:31 /* RWIVF */
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#define NV_PME_656_CONFIG_VIDEO_8 0x00000000 /* RW--V */
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#define NV_PME_656_CONFIG_VIDEO_16 0x00000001 /* RW--V */
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|
#define NV_PME_NULL_DATA 0x00200404 /* RWI4R */
|
|
#define NV_PME_NULL_DATA_COMPARE 0:0 /* RWIVF */
|
|
#define NV_PME_NULL_DATA_COMPARE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PME_NULL_DATA_COMPARE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PME_NULL_DATA_LINE_DETECT 4:4 /* RWIVF */
|
|
#define NV_PME_NULL_DATA_LINE_DETECT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PME_NULL_DATA_LINE_DETECT_ENABLED 0x00000001 /* RW--V */
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|
#define NV_PME_NULL_DATA_BYTE 31:24 /* RWXVF */
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#define NV_PME_VIPREG_NBYTES 0x00200300 /* RW-4R */
|
|
#define NV_PME_VIPREG_ADDR 0x00200304 /* RW-4R */
|
|
#define NV_PME_VIPREG_ADDR_LA 7:0 /* RW-VF */
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|
#define NV_PME_VIPREG_ADDR_UA 15:8 /* RW-VF */
|
|
#define NV_PME_VIPREG_DATA 0x00200308 /* RW-4R */
|
|
#define NV_PME_VIPREG_DATA_BITS 31:0 /* RW_VF */
|
|
#define NV_PME_VIPREG_CTRL 0x0020030c /* RW-4R */
|
|
#define NV_PME_VIPREG_CTRL_READ 0:0 /* RWIVF */
|
|
#define NV_PME_VIPREG_CTRL_READ_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PME_VIPREG_CTRL_READ_PENDING 0x00000001 /* R---V */
|
|
#define NV_PME_VIPREG_CTRL_READ_START 0x00000001 /* -WI-V */
|
|
#define NV_PME_VIPREG_CTRL_WRITE 8:8 /* RWIVF */
|
|
#define NV_PME_VIPREG_CTRL_WRITE_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PME_VIPREG_CTRL_WRITE_PENDING 0x00000001 /* R---V */
|
|
#define NV_PME_VIPREG_CTRL_WRITE_START 0x00000001 /* -WI-V */
|
|
#define NV_PME_FOUT_BUFF0_START 0x00200340 /* RWI4R */
|
|
#define NV_PME_FOUT_BUFF0_START_ADDRESS 31:4 /* RWXUF */
|
|
#define NV_PME_FOUT_BUFF1_START 0x00200344 /* RWI4R */
|
|
#define NV_PME_FOUT_BUFF1_START_ADDRESS 31:4 /* RWXUF */
|
|
#define NV_PME_FOUT_BUFF0_LENGTH 0x00200348 /* RWI4R */
|
|
#define NV_PME_FOUT_BUFF0_LENGTH_BITS 23:4 /* RWXUF */
|
|
#define NV_PME_FOUT_BUFF1_LENGTH 0x0020034c /* RWI4R */
|
|
#define NV_PME_FOUT_BUFF1_LENGTH_BITS 23:4 /* RWXUF */
|
|
#define NV_PME_FOUT_ME_STATE 0x00200350 /* RW-4R */
|
|
#define NV_PME_FOUT_ME_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWIVF */
|
|
#define NV_PME_FOUT_ME_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_FOUT_ME_STATE_BUFF0_IN_USE 8:8 /* RWXVF */
|
|
#define NV_PME_FOUT_ME_STATE_BUFF1_IN_USE 12:12 /* RWXVF */
|
|
#define NV_PME_FOUT_ME_STATE_CURRENT_BUFFER 16:16 /* RWXVF */
|
|
#define NV_PME_FOUT_ME_STATE_CURRENT_BUFFER_0 0x00000000 /* RW--V */
|
|
#define NV_PME_FOUT_ME_STATE_CURRENT_BUFFER_1 0x00000001 /* RW--V */
|
|
#define NV_PME_FOUT_SU_STATE 0x00200354 /* RW-4R */
|
|
#define NV_PME_FOUT_SU_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_FOUT_SU_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_FOUT_RM_STATE 0x00200358 /* RW-4R */
|
|
#define NV_PME_FOUT_RM_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_FOUT_RM_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_FOUT_CURRENT 0x0020035c /* R-I4R */
|
|
#define NV_PME_FOUT_CURRENT_POS 31:0 /* R-XUF */
|
|
#define NV_PME_FIN_BUFF0_START 0x00200380 /* RWI4R */
|
|
#define NV_PME_FIN_BUFF0_START_ADDRESS 31:4 /* RWXUF */
|
|
#define NV_PME_FIN_BUFF1_START 0x00200384 /* RWI4R */
|
|
#define NV_PME_FIN_BUFF1_START_ADDRESS 31:4 /* RWXUF */
|
|
#define NV_PME_FIN_BUFF0_LENGTH 0x00200388 /* RWI4R */
|
|
#define NV_PME_FIN_BUFF0_LENGTH_BITS 23:4 /* RWXUF */
|
|
#define NV_PME_FIN_BUFF1_LENGTH 0x0020038c /* RWI4R */
|
|
#define NV_PME_FIN_BUFF1_LENGTH_BITS 23:4 /* RWXUF */
|
|
#define NV_PME_FIN_ME_STATE 0x00200390 /* RW-4R */
|
|
#define NV_PME_FIN_ME_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWIVF */
|
|
#define NV_PME_FIN_ME_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_FIN_ME_STATE_BUFF0_IN_USE 8:8 /* RWXVF */
|
|
#define NV_PME_FIN_ME_STATE_BUFF1_IN_USE 12:12 /* RWXVF */
|
|
#define NV_PME_FIN_ME_STATE_CURRENT_BUFFER 16:16 /* RWXVF */
|
|
#define NV_PME_FIN_ME_STATE_CURRENT_BUFFER_0 0x00000000 /* RW--V */
|
|
#define NV_PME_FIN_ME_STATE_CURRENT_BUFFER_1 0x00000001 /* RW--V */
|
|
#define NV_PME_FIN_SU_STATE 0x00200394 /* RW-4R */
|
|
#define NV_PME_FIN_SU_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_FIN_SU_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_FIN_RM_STATE 0x00200398 /* RW-4R */
|
|
#define NV_PME_FIN_RM_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_FIN_RM_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_FIN_CURRENT 0x0020039c /* R-I4R */
|
|
#define NV_PME_FIN_CURRENT_POS 31:0 /* R-XUF */
|
|
#define NV_PME_VBI_REGION 0x00200408 /* RWI4R */
|
|
#define NV_PME_VBI_REGION_START_LINE 4:0 /* RWX-F */
|
|
#define NV_PME_VBI_REGION_NUM_LINES 20:16 /* RWX-F */
|
|
#define NV_PME_ANC_BUFF0_START 0x00200410 /* RWI4R */
|
|
#define NV_PME_ANC_BUFF0_START_ADDRESS 26:4 /* RWXUF */
|
|
#define NV_PME_ANC_BUFF1_START 0x00200414 /* RWI4R */
|
|
#define NV_PME_ANC_BUFF1_START_ADDRESS 26:4 /* RWXUF */
|
|
#define NV_PME_ANC_BUFF0_PITCH 0x00200418 /* RWI4R */
|
|
#define NV_PME_ANC_BUFF0_PITCH_VALUE 13:4 /* RWXUF */
|
|
#define NV_PME_ANC_BUFF1_PITCH 0x0020041c /* RWI4R */
|
|
#define NV_PME_ANC_BUFF1_PITCH_VALUE 13:4 /* RWXUF */
|
|
#define NV_PME_ANC_BUFF0_LENGTH 0x00200420 /* RWI4R */
|
|
#define NV_PME_ANC_BUFF0_LENGTH_VALUE 19:4 /* RWXUF */
|
|
#define NV_PME_ANC_BUFF1_LENGTH 0x00200424 /* RWI4R */
|
|
#define NV_PME_ANC_BUFF1_LENGTH_VALUE 19:4 /* RWXUF */
|
|
#define NV_PME_ANC_ME_STATE 0x00200428 /* RW-4R */
|
|
#define NV_PME_ANC_ME_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_BUFF0_ERROR_CODE 10:8 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_BUFF1_ERROR_CODE 14:12 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_CURRENT_BUFFER 24:24 /* RWXVF */
|
|
#define NV_PME_ANC_ME_STATE_CURRENT_BUFFER_0 0x00000000 /* RW--V */
|
|
#define NV_PME_ANC_ME_STATE_CURRENT_BUFFER_1 0x00000001 /* RW--V */
|
|
#define NV_PME_ANC_SU_STATE 0x0020042c /* RW-4R */
|
|
#define NV_PME_ANC_SU_STATE_BUFF0_FIELD 8:8 /* RWXVF */
|
|
#define NV_PME_ANC_SU_STATE_BUFF1_FIELD 12:12 /* RWXVF */
|
|
#define NV_PME_ANC_SU_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_ANC_SU_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_ANC_RM_STATE 0x00200430 /* RW-4R */
|
|
#define NV_PME_ANC_RM_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_ANC_RM_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_ANC_CURRENT 0x00200434 /* R--4R */
|
|
#define NV_PME_ANC_CURRENT_POS 27:0 /* R-XVF */
|
|
#define NV_PME_TASKA_BUFF0_START 0x00200440 /* RWI4R */
|
|
#define NV_PME_TASKA_BUFF0_START_ADDRESS 26:4 /* RWXUF */
|
|
#define NV_PME_TASKA_BUFF1_START 0x00200444 /* RWI4R */
|
|
#define NV_PME_TASKA_BUFF1_START_ADDRESS 26:4 /* RWXUF */
|
|
#define NV_PME_TASKA_BUFF0_PITCH 0x00200448 /* RWI4R */
|
|
#define NV_PME_TASKA_BUFF0_PITCH_VALUE 13:4 /* RWXUF */
|
|
#define NV_PME_TASKA_BUFF1_PITCH 0x0020044c /* RWI4R */
|
|
#define NV_PME_TASKA_BUFF1_PITCH_VALUE 13:4 /* RWXUF */
|
|
#define NV_PME_TASKA_BUFF0_LENGTH 0x00200450 /* RWI4R */
|
|
#define NV_PME_TASKA_BUFF0_LENGTH_VALUE 23:4 /* RWXUF */
|
|
#define NV_PME_TASKA_BUFF1_LENGTH 0x00200454 /* RWI4R */
|
|
#define NV_PME_TASKA_BUFF1_LENGTH_VALUE 23:4 /* RWXUF */
|
|
#define NV_PME_TASKA_LINE_LENGTH 0x002004f0 /* RWI4R */
|
|
#define NV_PME_TASKA_LINE_LENGTH_VALUE 13:2 /* RWXUF */
|
|
#define NV_PME_TASKA_ME_STATE 0x00200458 /* RW-4R */
|
|
#define NV_PME_TASKA_ME_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_RP_FLAGS_BUFF0 8:5 /* RW--- */
|
|
#define NV_PME_TASKA_ME_STATE_BUFF0_ERROR_CODE 11:9 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_BUFF1_ERROR_CODE 14:12 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_CURRENT_BUFFER 24:24 /* RWXVF */
|
|
#define NV_PME_TASKA_ME_STATE_CURRENT_BUFFER_0 0x00000000 /* RW--V */
|
|
#define NV_PME_TASKA_ME_STATE_CURRENT_BUFFER_1 0x00000001 /* RW--V */
|
|
#define NV_PME_TASKA_ME_STATE_RP_FLAGS_BUFF1 28:25 /* RW--- */
|
|
#define NV_PME_TASKA_SU_STATE 0x0020045c /* RW-4R */
|
|
#define NV_PME_TASKA_SU_STATE_BUFF0_FIELD 8:8 /* RWXVF */
|
|
#define NV_PME_TASKA_SU_STATE_BUFF1_FIELD 12:12 /* RWXVF */
|
|
#define NV_PME_TASKA_SU_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_TASKA_SU_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_TASKA_RM_STATE 0x00200460 /* RW-4R */
|
|
#define NV_PME_TASKA_RM_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_TASKA_RM_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_TASKA_Y_CROP 0x00200464 /* RW-4R */
|
|
#define NV_PME_TASKA_Y_CROP_STARTLINE 8:0 /* RWXVF */
|
|
#define NV_PME_TASKA_Y_SCALE 0x00200468 /* RW-4R */
|
|
#define NV_PME_TASKA_Y_SCALE_INCR 10:0 /* RWXVF */
|
|
#define NV_PME_TASKA_X_SCALE 0x0020046c /* RW-4R */
|
|
#define NV_PME_TASKA_X_SCALE_INCR 27:0 /* RWXVF */
|
|
#define NV_PME_TASKA_X_SCALE_FILTER 31:31 /* RWXVF */
|
|
#define NV_PME_TASKA_X_SCALE_FILTER_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PME_TASKA_X_SCALE_FILTER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PME_TASKB_BUFF0_START 0x00200470 /* RWI4R */
|
|
#define NV_PME_TASKB_BUFF0_START_ADDRESS 26:4 /* RWXUF */
|
|
#define NV_PME_TASKB_BUFF1_START 0x00200474 /* RWI4R */
|
|
#define NV_PME_TASKB_BUFF1_START_ADDRESS 26:4 /* RWXUF */
|
|
#define NV_PME_TASKB_BUFF0_PITCH 0x00200478 /* RWI4R */
|
|
#define NV_PME_TASKB_BUFF0_PITCH_VALUE 13:4 /* RWXUF */
|
|
#define NV_PME_TASKB_BUFF1_PITCH 0x0020047c /* RWI4R */
|
|
#define NV_PME_TASKB_BUFF1_PITCH_VALUE 13:4 /* RWXUF */
|
|
#define NV_PME_TASKB_BUFF0_LENGTH 0x00200480 /* RWI4R */
|
|
#define NV_PME_TASKB_BUFF0_LENGTH_VALUE 23:4 /* RWXUF */
|
|
#define NV_PME_TASKB_BUFF1_LENGTH 0x00200484 /* RWI4R */
|
|
#define NV_PME_TASKB_BUFF1_LENGTH_VALUE 23:4 /* RWXUF */
|
|
#define NV_PME_TASKB_LINE_LENGTH 0x002004f4 /* RWI4R */
|
|
#define NV_PME_TASKB_LINE_LENGTH_VALUE 13:2 /* RWXUF */
|
|
#define NV_PME_TASKB_ME_STATE 0x00200488 /* RW-4R */
|
|
#define NV_PME_TASKB_ME_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_RP_FLAGS_BUFF0 8:5 /* RW--- */
|
|
#define NV_PME_TASKB_ME_STATE_BUFF0_ERROR_CODE 11:9 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_BUFF1_ERROR_CODE 14:12 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_CURRENT_BUFFER 24:24 /* RWXVF */
|
|
#define NV_PME_TASKB_ME_STATE_CURRENT_BUFFER_0 0x00000000 /* RW--V */
|
|
#define NV_PME_TASKB_ME_STATE_CURRENT_BUFFER_1 0x00000001 /* RW--V */
|
|
#define NV_PME_TASKB_ME_STATE_RP_FLAGS_BUFF1 28:25 /* R---- */
|
|
#define NV_PME_TASKB_SU_STATE 0x0020048c /* RW-4R */
|
|
#define NV_PME_TASKB_SU_STATE_BUFF0_FIELD 8:8 /* RWXVF */
|
|
#define NV_PME_TASKB_SU_STATE_BUFF1_FIELD 12:12 /* RWXVF */
|
|
#define NV_PME_TASKB_SU_STATE_BUFF0_IN_USE 16:16 /* RWXVF */
|
|
#define NV_PME_TASKB_SU_STATE_BUFF1_IN_USE 20:20 /* RWXVF */
|
|
#define NV_PME_TASKB_RM_STATE 0x00200490 /* RW-4R */
|
|
#define NV_PME_TASKB_RM_STATE_BUFF0_INTR_NOTIFY 0:0 /* RWXVF */
|
|
#define NV_PME_TASKB_RM_STATE_BUFF1_INTR_NOTIFY 4:4 /* RWXVF */
|
|
#define NV_PME_TASKB_Y_CROP 0x00200494 /* RW-4R */
|
|
#define NV_PME_TASKB_Y_CROP_STARTLINE 8:0 /* RWXVF */
|
|
#define NV_PME_TASKB_Y_SCALE 0x00200498 /* RW-4R */
|
|
#define NV_PME_TASKB_Y_SCALE_INCR 10:0 /* RWXVF */
|
|
#define NV_PME_TASKB_X_SCALE 0x0020049c /* RW-4R */
|
|
#define NV_PME_TASKB_X_SCALE_INCR 27:0 /* RWXVF */
|
|
#define NV_PME_TASKB_X_SCALE_FILTER 31:31 /* RWXVF */
|
|
#define NV_PME_TASKB_X_SCALE_FILTER_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PME_TASKB_X_SCALE_FILTER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PME_TASK_CURRENT 0x002004a0 /* RW-4R */
|
|
#define NV_PME_TASK_CURRENT_POS 27:0 /* RWXVF */
|
|
#define NV_PME_TASK_CURRENT_TASK 31:31 /* RWXVF */
|
|
#define NV_PME_HORIZ_WGHTS_A(i) (0x002004b0+(i)*4) /* -W-4A */
|
|
#define NV_PME_HORIZ_WGHTS_A__SIZE_1 8 /* */
|
|
#define NV_PME_HORIZ_WGHTS_A_0 7:0 /* -WXVF */
|
|
#define NV_PME_HORIZ_WGHTS_A_1 15:8 /* -WXVF */
|
|
#define NV_PME_HORIZ_WGHTS_A_2 24:16 /* -WXVF */
|
|
#define NV_PME_HORIZ_WGHTS_B(i) (0x002004d0+(i)*4) /* -W-4A */
|
|
#define NV_PME_HORIZ_WGHTS_B__SIZE_1 8 /* */
|
|
#define NV_PME_HORIZ_WGHTS_B_3 7:0 /* -WXVF */
|
|
#define NV_PME_HORIZ_WGHTS_B_4 15:8 /* -WXVF */
|
|
/* usr_color_key.ref */
|
|
#define NV_IMAGE_COLOR_KEY 0x00000015 /* ----C */
|
|
#define NV_UIMAGEKEY 0x00591FFF:0x00590000 /* -W--D */
|
|
#define NV_UIMAGEKEY_CTX_SWITCH 0x00590000 /* -W-4R */
|
|
#define NV_UIMAGEKEY_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UIMAGEKEY_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UIMAGEKEY_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UIMAGEKEY_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UIMAGEKEY_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UIMAGEKEY_NOTIFY 0x00590104 /* -W-4R */
|
|
#define NV_UIMAGEKEY_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UIMAGEKEY_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UIMAGEKEY_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UIMAGEKEY_SET_CONTEXT_DMA_NOTIFY 0x00590180 /* -W-4R */
|
|
#define NV_UIMAGEKEY_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGEKEY_SET_IMAGE_OUTPUT 0x00590200 /* -W-4R */
|
|
#define NV_UIMAGEKEY_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGEKEY_SET_IMAGE_INPUT(i) (0x00590204+(i)*4) /* -W-4A */
|
|
#define NV_UIMAGEKEY_SET_IMAGE_INPUT__SIZE_1 2 /* */
|
|
#define NV_UIMAGEKEY_SET_IMAGE_INPUT_PARAMETER 31:0 /* -W-VF */
|
|
/* usr_beta_solid.ref */
|
|
#define NV_BETA_SOLID 0x00000012 /* ----C */
|
|
#define NV_UBETA 0x00411FFF:0x00410000 /* -W--D */
|
|
#define NV_UBETA_CTX_SWITCH 0x00410000 /* -W-4R */
|
|
#define NV_UBETA_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UBETA_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UBETA_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UBETA_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UBETA_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UBETA_NOTIFY 0x00410104 /* -W-4R */
|
|
#define NV_UBETA_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UBETA_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UBETA_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UBETA_SET_NOTIFY 0x00410104 /* -W-4R */
|
|
#define NV_UBETA_SET_NOTIFY__ALIAS_1 NV_UBETA_NOTIFY /* */
|
|
#define NV_UBETA_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBETA_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UBETA_SET_CONTEXT_DMA_NOTIFY 0x00410180 /* -W-4R */
|
|
#define NV_UBETA_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBETA_SET_BETA_OUTPUT 0x00410200 /* -W-4R */
|
|
#define NV_UBETA_SET_BETA_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBETA_SET_BETA1D31 0x00410300 /* -W-4R */
|
|
#define NV_UBETA_SET_BETA1D31_VALUE_FRACTION 30:21 /* -W-UF */
|
|
#define NV_UBETA_SET_BETA1D31_VALUE 31:31 /* -W-SF */
|
|
/* usr_rop_solid.ref */
|
|
#define NV_ROP5_SOLID 0x00000043 /* ----C */
|
|
#define NV_UROP 0x00421FFF:0x00420000 /* -W--D */
|
|
#define NV_UROP_CTX_SWITCH 0x00420000 /* -W-4R */
|
|
#define NV_UROP_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UROP_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UROP_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UROP_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UROP_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UROP_NOTIFY 0x00420104 /* -W-4R */
|
|
#define NV_UROP_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UROP_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UROP_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UROP_SET_NOTIFY 0x00420104 /* -W-4R */
|
|
#define NV_UROP_SET_NOTIFY__ALIAS_1 NV_UROP_NOTIFY /* */
|
|
#define NV_UROP_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UROP_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UROP_SET_CONTEXT_DMA_NOTIFY 0x00420180 /* -W-4R */
|
|
#define NV_UROP_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UROP_SET_ROP_OUTPUT 0x00420200 /* -W-4R */
|
|
#define NV_UROP_SET_ROP_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UROP_SET_ROP5 0x00420300 /* -W-4R */
|
|
#define NV_UROP_SET_ROP5_VALUE 7:0 /* -W-VF */
|
|
#define NV_UROP_SET_ROP 0x00420300 /* -W-4R */
|
|
#define NV_UROP_SET_ROP__ALIAS_1 NV_UROP_SET_ROP5 /* */
|
|
#define NV_UROP_SET_ROP_VALUE 7:0 /* -W-VF */
|
|
/* usr_nv4_image_solid.ref */
|
|
#define NV_IMAGE_SOLID 0x00000057 /* ----C */
|
|
#define NV4_CONTEXT_COLOR_KEY 0x00000057 /* ----C */
|
|
#define NV_UCHROMA 0x00431FFF:0x00430000 /* -W--D */
|
|
#define NV_UCHROMA_CTX_SWITCH 0x00430000 /* -W-4R */
|
|
#define NV_UCHROMA_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UCHROMA_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UCHROMA_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UCHROMA_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UCHROMA_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UCHROMA_NOP 0x00430100 /* -W-4R */
|
|
#define NV_UCHROMA_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UCHROMA_NOTIFY 0x00430104 /* -W-4R */
|
|
#define NV_UCHROMA_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UCHROMA_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UCHROMA_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UCHROMA_SET_NOTIFY 0x00430104 /* -W-4R */
|
|
#define NV_UCHROMA_SET_NOTIFY__ALIAS_1 NV_UCHROMA_NOTIFY /* */
|
|
#define NV_UCHROMA_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UCHROMA_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UCHROMA_SET_CONTEXT_DMA_NOTIFY 0x00430180 /* -W-4R */
|
|
#define NV_UCHROMA_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UCHROMA_SET_IMAGE_OUTPUT 0x00430200 /* -W-4R */
|
|
#define NV_UCHROMA_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
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#define NV_UCHROMA_SET_COLOR_FORMAT 0x00430300 /* -W-4R */
|
|
#define NV_UCHROMA_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_UCHROMA_SET_COLOR_FORMAT_LE_A16R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_UCHROMA_SET_COLOR_FORMAT_LE_X16A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_UCHROMA_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_UCHROMA_SET_COLOR 0x00430304 /* -W-4R */
|
|
#define NV_UCHROMA_SET_COLOR_VALUE 31:0 /* -W-VF */
|
|
/* usr_clipping.ref */
|
|
#define NV_IMAGE_BLACK_RECTANGLE 0x00000019 /* ----C */
|
|
#define NV_UCLIP 0x00451FFF:0x00450000 /* -W--D */
|
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#define NV_UCLIP_CTX_SWITCH 0x00450000 /* -W-4R */
|
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#define NV_UCLIP_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UCLIP_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UCLIP_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UCLIP_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UCLIP_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UCLIP_NOTIFY 0x00450104 /* -W-4R */
|
|
#define NV_UCLIP_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UCLIP_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UCLIP_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UCLIP_SET_NOTIFY 0x00450104 /* -W-4R */
|
|
#define NV_UCLIP_SET_NOTIFY__ALIAS_1 NV_UCLIP_NOTIFY /* */
|
|
#define NV_UCLIP_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UCLIP_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UCLIP_SET_CONTEXT_DMA_NOTIFY 0x00450180 /* -W-4R */
|
|
#define NV_UCLIP_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UCLIP_SET_IMAGE_OUTPUT 0x00450200 /* -W-4R */
|
|
#define NV_UCLIP_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UCLIP_SET_RECT_0 0x00450300 /* -W-4R */
|
|
#define NV_UCLIP_SET_RECT_0_X 15:0 /* -W-SF */
|
|
#define NV_UCLIP_SET_RECT_0_Y 31:16 /* -W-SF */
|
|
#define NV_UCLIP_SET_RECT_1 0x00450304 /* -W-4R */
|
|
#define NV_UCLIP_SET_RECT_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_UCLIP_SET_RECT_1_HEIGHT 31:16 /* -W-UF */
|
|
/* usr_d3d0_triangle_zeta.ref */
|
|
#define NV_RENDER_D3D0_TRIANGLE_ZETA 0x00000048 /* ----C */
|
|
#define NV_UD3D0Z 0x00571FFF:0x00570000 /* -W--D */
|
|
#define NV_UD3D0Z_CTX_SWITCH 0x00570000 /* -W-4R */
|
|
#define NV_UD3D0Z_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UD3D0Z_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UD3D0Z_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UD3D0Z_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UD3D0Z_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UD3D0Z_NOP 0x00570100 /* -W-4R */
|
|
#define NV_UD3D0Z_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_NOTIFY 0x00570104 /* -W-4R */
|
|
#define NV_UD3D0Z_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UD3D0Z_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UD3D0Z_NOTIFY_STYLE_NOT_PENDING 0x00000002 /* -W--V */
|
|
#define NV_UD3D0Z_SET_NOTIFY 0x00570104 /* -W-4R */
|
|
#define NV_UD3D0Z_SET_NOTIFY__ALIAS_1 NV_UD3D0Z_NOTIFY /* */
|
|
#define NV_UD3D0Z_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UD3D0Z_SET_PATCH 0x0057010C /* -W-4R */
|
|
#define NV_UD3D0Z_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_UD3D0Z_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_UD3D0Z_SET_CONTEXT_DMA_NOTIFY 0x00570180 /* -W-4R */
|
|
#define NV_UD3D0Z_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_CONTEXT_DMA_TEXTURE 0x00570184 /* -W-4R */
|
|
#define NV_UD3D0Z_SET_CONTEXT_DMA_TEXTURE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_IMAGE_COLOR_OUTPUT 0x00570200 /* -W-4R */
|
|
#define NV_UD3D0Z_SET_IMAGE_COLOR_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_IMAGE_COLOR_INPUT 0x00570204 /* -W-4R */
|
|
#define NV_UD3D0Z_SET_IMAGE_COLOR_INPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_IMAGE_ZETA_OUTPUT 0x00570208 /* -W-4R */
|
|
#define NV_UD3D0Z_SET_IMAGE_ZETA_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_SET_IMAGE_ZETA_INPUT 0x0057020C /* -W-4R */
|
|
#define NV_UD3D0Z_SET_IMAGE_ZETA_INPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UD3D0Z_TEXTURE_OFFSET 0x00570304 /* -W-4R */
|
|
#define NV_UD3D0Z_TEXTURE_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT 0x00570308 /* -W-4R */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_KEY_COLOR_MASK 15:0 /* -W-UF */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_KEY 19:16 /* -W-UF */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_KEY_DISABLED 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_KEY_ENABLED 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_FORMAT 23:20 /* -W-UF */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_FORMAT_A1R5G5B5 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_FORMAT_X1R5G5B5 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_FORMAT_A4R4G4B4 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_COLOR_FORMAT_R5G6B5 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN 27:24 /* -W-UF */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_4X4 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_8X8 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_16X16 0x00000004 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_32X32 0x00000005 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_64X64 0x00000006 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_128X128 0x00000007 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_256X256 0x00000008 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_512X512 0x00000009 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_1024X1024 0x0000000a /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MIN_2048X2048 0x0000000b /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX 31:28 /* -W-UF */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_4X4 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_8X8 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_16X16 0x00000004 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_32X32 0x00000005 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_64X64 0x00000006 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_128X128 0x00000007 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_256X256 0x00000008 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_512X512 0x00000009 /* -W-UV */
|
|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_1024X1024 0x0000000a /* -W-UV */
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|
#define NV_UD3D0Z_TEXTURE_FORMAT_SIZE_MAX_2048X2048 0x0000000b /* -W-UV */
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|
#define NV_UD3D0Z_FILTER 0x0057030C /* -W-4R */
|
|
#define NV_UD3D0Z_FILTER_SPREADX 4:0 /* -W-UF */
|
|
#define NV_UD3D0Z_FILTER_IGNORE0 7:5 /* -W-UF */
|
|
#define NV_UD3D0Z_FILTER_SPREADY 12:8 /* -W-UF */
|
|
#define NV_UD3D0Z_FILTER_IGNORE1 15:13 /* -W-UF */
|
|
#define NV_UD3D0Z_FILTER_SIZEADJ 23:16 /* -W-SF */
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|
#define NV_UD3D0Z_FILTER_IGNORE2 31:24 /* -W-SF */
|
|
#define NV_UD3D0Z_FOG_COLOR 0x00570310 /* -W-4R */
|
|
#define NV_UD3D0Z_FOG_COLOR_BLU 7:0 /* -W-UF */
|
|
#define NV_UD3D0Z_FOG_COLOR_GRN 15:8 /* -W-UF */
|
|
#define NV_UD3D0Z_FOG_COLOR_RED 23:16 /* -W-UF */
|
|
#define NV_UD3D0Z_FOG_COLOR_VALUE 31:0 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT 0x00570314 /* -W-4R */
|
|
#define NV_UD3D0Z_CONTROL_OUT_INTERPOLATOR 3:0 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_INTERPOLATOR_ZOH_MS 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_INTERPOLATOR_ZOH 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_INTERPOLATOR_FOH 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_U 5:4 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_U_CYLINDRICAL 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_U_WRAP 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_U_MIRROR 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_U_CLAMP 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_V 7:6 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_V_CYLINDRICAL 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_V_WRAP 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_V_MIRROR 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_WRAP_V_CLAMP 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_FORMAT 9:8 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_FORMAT_LE_X8R8G8B8 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_FORMAT_LE_A8R8G8B8 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_SRCCOLOR 11:10 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_SRCCOLOR_NORMAL 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_SRCCOLOR_COLOR_INVERSE 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_SRCCOLOR_ALPHA_INVERSE 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_SRCCOLOR_ALPHA_ONE 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_CULLING 14:12 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_CULLING_NONE 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_CULLING_COUNTERCLOCKWISE 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_CULLING_CLOCKWISE 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZBUFFER 15:15 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZBUFFER_SCREEN 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZBUFFER_LINEAR 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE 19:16 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_FALSE 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_LT 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_EQ 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_LE 0x00000004 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_GT 0x00000005 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_NE 0x00000006 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_GE 0x00000007 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_COMPARE_TRUE 0x00000008 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_WRITE 23:20 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_WRITE_NEVER 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_WRITE_ALPHA 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_WRITE_ALPHA_ZETA 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_WRITE_ZETA 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ZETA_WRITE_ALWAYS 0x00000004 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_WRITE 27:24 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_WRITE_NEVER 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_WRITE_ALPHA 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_WRITE_ALPHA_ZETA 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_WRITE_ZETA 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_COLOR_WRITE_ALWAYS 0x00000004 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ROP 28:28 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ROP_BLEND_AND 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_ROP_ADD_WITH_SATURATION 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_BETA 29:29 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_BETA_SRCALPHA 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_BETA_DESTCOLOR 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_INPUT0 30:30 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_INPUT0_DESTCOLOR 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_INPUT0_ZERO 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_INPUT1 31:31 /* -W-UF */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_INPUT1_SRCCOLOR 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_CONTROL_OUT_BLEND_INPUT1_ZERO 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL 0x00570318 /* -W-4R */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_KEY 7:0 /* -WXUF */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE 31:8 /* -W-UF */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_ILLEGAL 0x00000000 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_FALSE 0x00000001 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_LT 0x00000002 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_EQ 0x00000003 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_LE 0x00000004 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_GT 0x00000005 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_NE 0x00000006 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_GE 0x00000007 /* -W-UV */
|
|
#define NV_UD3D0Z_ALPHA_CONTROL_ALPHA_COMPARE_TRUE 0x00000008 /* -W-UV */
|
|
#define NV_UD3D0Z_SPECULAR(i) (0x00571000+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_SPECULAR__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_SPECULAR_I0 3:0 /* -W-UF */
|
|
#define NV_UD3D0Z_SPECULAR_I1 7:4 /* -W-UF */
|
|
#define NV_UD3D0Z_SPECULAR_I2 11:8 /* -W-UF */
|
|
#define NV_UD3D0Z_SPECULAR_I3 15:12 /* -W-UF */
|
|
#define NV_UD3D0Z_SPECULAR_I4 19:16 /* -W-UF */
|
|
#define NV_UD3D0Z_SPECULAR_I5 23:20 /* -W-UF */
|
|
#define NV_UD3D0Z_SPECULAR_FOG 31:24 /* -W-UF */
|
|
#define NV_UD3D0Z_COLOR(i) (0x00571004+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_COLOR__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_COLOR_B8 7:0 /* -W-UF */
|
|
#define NV_UD3D0Z_COLOR_G8 16:8 /* -W-UF */
|
|
#define NV_UD3D0Z_COLOR_R8 23:16 /* -W-UF */
|
|
#define NV_UD3D0Z_COLOR_A8 32:24 /* -W-UF */
|
|
#define NV_UD3D0Z_X(i) (0x00571008+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_X__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_X_VALUE 31:0 /* -W-FF */
|
|
#define NV_UD3D0Z_Y(i) (0x0057100C+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_Y__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_Y_VALUE 31:0 /* -W-FF */
|
|
#define NV_UD3D0Z_Z(i) (0x00571010+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_Z__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_Z_VALUE 31:0 /* -W-FF */
|
|
#define NV_UD3D0Z_M(i) (0x00571014+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_M__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_M_VALUE 31:0 /* -W-FF */
|
|
#define NV_UD3D0Z_U(i) (0x00571018+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_U__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_U_VALUE 31:0 /* -W-FF */
|
|
#define NV_UD3D0Z_V(i) (0x0057101c+(i)*32) /* -W-4A */
|
|
#define NV_UD3D0Z_V__SIZE_1 128 /* */
|
|
#define NV_UD3D0Z_V_VALUE 31:0 /* -W-FF */
|
|
/* usr_dx5_textured_triangle.ref */
|
|
#define NV4_DX5_TEXTURE_TRIANGLE 0x00000054 /* ----C */
|
|
#define NV_054 0x005e1FFF:0x005e0000 /* -W--D */
|
|
#define NV_054_NV4_DX5_TEXTURE_TRIANGLE 0x005e0000 /* -W-4R */
|
|
#define NV_054_NV4_DX5_TEXTURE_TRIANGLE_HANDLE 31:0 /* -WXVF */
|
|
#define NV_054_NOP 0x005e0100 /* -W-4R */
|
|
#define NV_054_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_054_NOTIFY 0x005e0104 /* -W-4R */
|
|
#define NV_054_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_054_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_054_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_054_NOTIFY__ALIAS_1 NV_054_SET NOTIFY /* */
|
|
#define NV_054_SET_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_054_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_054_SET_CONTEXT_DMA_NOTIFY 0x005e0180 /* -W-4R */
|
|
#define NV_054_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_054_SET_CONTEXT_DMA_A 0x005e0184 /* -W-4R */
|
|
#define NV_054_SET_CONTEXT_DMA_A_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_054_SET_CONTEXT_DMA_B 0x005e0188 /* -W-4R */
|
|
#define NV_054_SET_CONTEXT_DMA_B_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_054_SET_CONTEXT_SURFACES 0x005e018c /* -W-4R */
|
|
#define NV_054_SET_CONTEXT_SURFACES_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_054_COLORKEY 0x005e0300 /* -W-4R */
|
|
#define NV_054_COLORKEY_VALUE 31:0 /* -WXUF */
|
|
#define NV_054_OFFSET 0x005e0304 /* -W-4R */
|
|
#define NV_054_OFFSET_VALUE 31:0 /* -WXUF */
|
|
#define NV_054_FORMAT 0x005e0308 /* -W-4R */
|
|
#define NV_054_FORMAT_CONTEXT_DMA 1:0 /* -WXUF */
|
|
#define NV_054_FORMAT_CONTEXT_DMA_A 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_CONTEXT_DMA_B 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_COLORKEYENABLE 3:2 /* -WXUF */
|
|
#define NV_054_FORMAT_COLORKEYENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_FORMAT_COLORKEYENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_ORIGIN_ZOH 5:4 /* -WXUF */
|
|
#define NV_054_FORMAT_ORIGIN_ZOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_ORIGIN_ZOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_ORIGIN_FOH 7:6 /* -WXUF */
|
|
#define NV_054_FORMAT_ORIGIN_FOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_ORIGIN_FOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR 11:8 /* -WXUF */
|
|
#define NV_054_FORMAT_COLOR_LE_Y8 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR_LE_A4R4G4B4 0x00000004 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR_LE_R5G6B5 0x00000005 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR_LE_A8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_054_FORMAT_COLOR_LE_X8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_054_FORMAT_MIPMAP_LEVELS 15:12 /* -WXUF */
|
|
#define NV_054_FORMAT_BASE_SIZE_U 19:16 /* -WXUF */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_1X1 0x00000000 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_2X2 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_4X4 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_8X8 0x00000003 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_16X16 0x00000004 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_32X32 0x00000005 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_64X64 0x00000006 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_128X128 0x00000007 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_256X256 0x00000008 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_512X512 0x00000009 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_U_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V 23:20 /* -WXUF */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_1X1 0x00000000 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_2X2 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_4X4 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_8X8 0x00000003 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_16X16 0x00000004 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_32X32 0x00000005 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_64X64 0x00000006 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_128X128 0x00000007 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_256X256 0x00000008 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_512X512 0x00000009 /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_054_FORMAT_BASE_SIZE_V_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSU 26:24 /* -WXUF */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSU_WRAP 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSU_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSU_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSU_BORDER 0x00000004 /* -W--V */
|
|
#define NV_054_FORMAT_WRAPU 27:27 /* -WXUF */
|
|
#define NV_054_FORMAT_WRAPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_FORMAT_WRAPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSV 30:28 /* -WXUF */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSV_WRAP 0x00000001 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSV_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSV_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_054_FORMAT_TEXTUREADDRESSV_BORDER 0x00000004 /* -W--V */
|
|
#define NV_054_FORMAT_WRAPV 31:31 /* -WXUF */
|
|
#define NV_054_FORMAT_WRAPV_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_FORMAT_WRAPV_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_FILTER 0x005e030c /* -W-4R */
|
|
#define NV_054_FILTER_KERNEL_SIZE_X 7:0 /* -WXUF */
|
|
#define NV_054_FILTER_KERNEL_SIZE_Y 14:8 /* -WXUF */
|
|
#define NV_054_FILTER_MIPMAP_DITHER_ENABLE 15:15 /* -WXUF */
|
|
#define NV_054_FILTER_MIPMAP_DITHER_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_FILTER_MIPMAP_DITHER_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_FILTER_MIPMAPLODBIAS 23:16 /* -WXUF */
|
|
#define NV_054_FILTER_TEXTUREMIN 26:24 /* -WXUF */
|
|
#define NV_054_FILTER_TEXTUREMIN_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMIN_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMIN_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMIN_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_054_FILTER_ANISOTROPIC_MIN_ENABLE 27:27 /* -WXUF */
|
|
#define NV_054_FILTER_ANISOTROPIC_MIN_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_FILTER_ANISOTROPIC_MIN_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMAG 30:28 /* -WXUF */
|
|
#define NV_054_FILTER_TEXTUREMAG_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMAG_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMAG_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMAG_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMAG_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_054_FILTER_TEXTUREMAG_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_054_FILTER_ANISOTROPIC_MAG_ENABLE 31:31 /* -WXUF */
|
|
#define NV_054_FILTER_ANISOTROPIC_MAG_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_FILTER_ANISOTROPIC_MAG_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND 0x005e0310 /* -W-4R */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND 3:0 /* -WXVF */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_DECAL 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_MODULATE 0x00000002 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x00000003 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x00000004 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_DECALMASK 0x00000005 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x00000006 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_COPY 0x00000007 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREMAPBLEND_ADD 0x00000008 /* -W--V */
|
|
#define NV_054_BLEND_OPERATION 5:4 /* -WXVF */
|
|
#define NV_054_BLEND_OPERATION_MUX_TALPHALSB 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_OPERATION_MUX_TALPHAMSB 0x00000002 /* -W--V */
|
|
#define NV_054_BLEND_SHADEMODE 7:6 /* -WXVF */
|
|
#define NV_054_BLEND_SHADEMODE_FLAT 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_SHADEMODE_GOURAUD 0x00000002 /* -W--V */
|
|
#define NV_054_BLEND_SHADEMODE_PHONG 0x00000003 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREPERSPECTIVE 11:8 /* -WXVF */
|
|
#define NV_054_BLEND_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_BLEND_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_SPECULARENABLE 15:12 /* -WXVF */
|
|
#define NV_054_BLEND_SPECULARENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_BLEND_SPECULARENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_FOGENABLE 19:16 /* -WXVF */
|
|
#define NV_054_BLEND_FOGENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_BLEND_FOGENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_ALPHABLENDENABLE 23:20 /* -WXVF */
|
|
#define NV_054_BLEND_ALPHABLENDENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_BLEND_ALPHABLENDENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND 27:24 /* -WXVF */
|
|
#define NV_054_BLEND_SRCBLEND_ZERO 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_ONE 0x00000002 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_SRCCOLOR 0x00000003 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_SRCALPHA 0x00000005 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_INVSRCALPHA 0x00000006 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_DESTALPHA 0x00000007 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_INVDESTALPHA 0x00000008 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_DESTCOLOR 0x00000009 /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
|
|
#define NV_054_BLEND_SRCBLEND_SRCALPHASAT 0x0000000B /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND 31:28 /* -WXVF */
|
|
#define NV_054_BLEND_DESTBLEND_ZERO 0x00000001 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_ONE 0x00000002 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_SRCCOLOR 0x00000003 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_SRCALPHA 0x00000005 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_INVSRCALPHA 0x00000006 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_DESTALPHA 0x00000007 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_INVDESTALPHA 0x00000008 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_DESTCOLOR 0x00000009 /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
|
|
#define NV_054_BLEND_DESTBLEND_SRCALPHASAT 0x0000000B /* -W--V */
|
|
#define NV_054_CONTROL 0x005e0314 /* -W-4R */
|
|
#define NV_054_CONTROL_ALPHAREF 7:0 /* -WXUF */
|
|
#define NV_054_CONTROL_ALPHAFUNC 11:8 /* -WXVF */
|
|
#define NV_054_CONTROL_ALPHAFUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHAFUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHATESTENABLE 12:12 /* -WXVF */
|
|
#define NV_054_CONTROL_ALPHATESTENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_CONTROL_ALPHATESTENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_ORIGIN 13:13 /* -WXVF */
|
|
#define NV_054_CONTROL_ORIGIN_CENTER 0x00000000 /* -W--V */
|
|
#define NV_054_CONTROL_ORIGIN_CORNER 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_ZENABLE 15:14 /* -WXVF */
|
|
#define NV_054_CONTROL_ZENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_CONTROL_ZENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC 19:16 /* -WXVF */
|
|
#define NV_054_CONTROL_ZFUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_054_CONTROL_ZFUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_054_CONTROL_CULLMODE 21:20 /* -WXVF */
|
|
#define NV_054_CONTROL_CULLMODE_NONE 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_CULLMODE_CW 0x00000002 /* -W--V */
|
|
#define NV_054_CONTROL_CULLMODE_CCW 0x00000003 /* -W--V */
|
|
#define NV_054_CONTROL_DITHERENABLE 22:22 /* -WXVF */
|
|
#define NV_054_CONTROL_DITHERENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_CONTROL_DITHERENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_Z_PERSPECTIVE_ENABLE 23:23 /* -WXVF */
|
|
#define NV_054_CONTROL_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_CONTROL_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_ZWRITEENABLE 29:24 /* -WXVF */
|
|
#define NV_054_CONTROL_ZWRITEENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_054_CONTROL_ZWRITEENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_Z_FORMAT 31:30 /* -WXVF */
|
|
#define NV_054_CONTROL_Z_FORMAT_FIXED 0x00000001 /* -W--V */
|
|
#define NV_054_CONTROL_Z_FORMAT_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_054_FOGCOLOR 0x005e0318 /* -W-4R */
|
|
#define NV_054_FOGCOLOR_VALUE 31:0 /* -WXUF */
|
|
#define NV_054_TLVERTEX_SX(i) (0x005e0400+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_SX__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_SX_VALUE 31:0 /* -WXFF */
|
|
#define NV_054_TLVERTEX_SY(i) (0x005e0404+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_SY__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_SY_VALUE 31:0 /* -WXFF */
|
|
#define NV_054_TLVERTEX_SZ(i) (0x005e0408+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_SZ__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_SZ_VALUE 31:0 /* -WXFF */
|
|
#define NV_054_TLVERTEX_RHW(i) (0x005e040c+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_RHW__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_RHW_VALUE 31:0 /* -WXFF */
|
|
#define NV_054_TLVERTEX_COLOR(i) (0x005e0410+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_COLOR__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_COLOR_VALUE 31:0 /* -WXUF */
|
|
#define NV_054_TLVERTEX_COLOR_BLUE 7:0 /* -WXUF */
|
|
#define NV_054_TLVERTEX_COLOR_GREEN 15:8 /* -WXUF */
|
|
#define NV_054_TLVERTEX_COLOR_RED 23:16 /* -WXUF */
|
|
#define NV_054_TLVERTEX_COLOR_ALPHA 31:24 /* -WXUF */
|
|
#define NV_054_TLVERTEX_SPECULAR(i) (0x005e0414+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_SPECULAR__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_SPECULAR_VALUE 31:0 /* -WXUF */
|
|
#define NV_054_TLVERTEX_SPECULAR_BLUE 7:0 /* -WXUF */
|
|
#define NV_054_TLVERTEX_SPECULAR_GREEN 15:8 /* -WXUF */
|
|
#define NV_054_TLVERTEX_SPECULAR_RED 23:16 /* -WXUF */
|
|
#define NV_054_TLVERTEX_SPECULAR_FOG 31:24 /* -WXUF */
|
|
#define NV_054_TLVERTEX_TU(i) (0x005e0418+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_TU__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_TU_VALUE 31:0 /* -WXFF */
|
|
#define NV_054_TLVERTEX_TV(i) (0x005e041c+(i)*32) /* -W-4A */
|
|
#define NV_054_TLVERTEX_TV__SIZE_1 16 /* */
|
|
#define NV_054_TLVERTEX_TV_VALUE 31:0 /* -WXFF */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE(i) (0x005e0600+(i)*4) /* -W-4A */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE__SIZE_1 64 /* */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE_I0 3:0 /* -WXUF */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE_I1 7:4 /* -WXUF */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE_I2 11:8 /* -WXUF */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE_I3 15:12 /* -WXUF */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE_I4 19:16 /* -WXUF */
|
|
#define NV_054_TLVERTEX_DRAWPRIMITIVE_I5 31:20 /* -WXUF */
|
|
/* usr_dx6_multitextured_triangle.ref */
|
|
#define NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x00000055 /* ----C */
|
|
#define NV_055 0x005f1FFF:0x005f0000 /* -W--D */
|
|
#define NV_055_NV4_DX6_MULTI_TEXTURE_TRIANGLE 0x005f0000 /* -W-4R */
|
|
#define NV_055_NV4_DX6_MULTI_TEXTURE_TRIANGLE_HANDLE 31:0 /* -WXVF */
|
|
#define NV_055_NOP 0x005f0100 /* -W-4R */
|
|
#define NV_055_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_055_NOTIFY 0x005f0104 /* -W-4R */
|
|
#define NV_055_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_055_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_055_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_055_NOTIFY_STYLE_NOT_PENDING 0x00000002 /* -W--V */
|
|
#define NV_055_SET_CONTEXT_DMA_NOTIFY 0x005f0180 /* -W-4R */
|
|
#define NV_055_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_055_SET_CONTEXT_DMA_A 0x005f0184 /* -W-4R */
|
|
#define NV_055_SET_CONTEXT_DMA_A_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_055_SET_CONTEXT_DMA_B 0x005f0188 /* -W-4R */
|
|
#define NV_055_SET_CONTEXT_DMA_B_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_055_SET_CONTEXT_SURFACES 0x005f018c /* -W-4R */
|
|
#define NV_055_SET_CONTEXT_SURFACES_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_055_OFFSET(i) (0x005f0308+(i)*4) /* -W-4A */
|
|
#define NV_055_OFFSET__SIZE_1 2 /* */
|
|
#define NV_055_OFFSET_VALUE 31:0 /* -WXUF */
|
|
#define NV_055_FORMAT(i) (0x005f0310+(i)*4) /* -W-4A */
|
|
#define NV_055_FORMAT__SIZE_1 2 /* */
|
|
#define NV_055_FORMAT_CONTEXT_DMA 3:0 /* -WXUF */
|
|
#define NV_055_FORMAT_CONTEXT_DMA_A 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_CONTEXT_DMA_B 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_ORIGIN_ZOH 5:4 /* -WXUF */
|
|
#define NV_055_FORMAT_ORIGIN_ZOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_ORIGIN_ZOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_ORIGIN_FOH 7:6 /* -WXUF */
|
|
#define NV_055_FORMAT_ORIGIN_FOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_ORIGIN_FOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR 11:8 /* -WXUF */
|
|
#define NV_055_FORMAT_COLOR_LE_AY8 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR_LE_A4R4G4G4 0x00000004 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR_LE_R5G6B5 0x00000005 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR_LE_A8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_055_FORMAT_COLOR_LE_X8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS 15:12 /* -WXUF */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_1 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_2 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_3 0x00000003 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_4 0x00000004 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_5 0x00000005 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_6 0x00000006 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_7 0x00000007 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_8 0x00000008 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_9 0x00000009 /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_10 0x0000000A /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_11 0x0000000B /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_12 0x0000000C /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_13 0x0000000D /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_14 0x0000000E /* -W--V */
|
|
#define NV_055_FORMAT_MIPMAP_LEVELS_15 0x0000000F /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U 19:16 /* -WXUF */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_1X1 0x00000000 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_2X2 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_4X4 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_8X8 0x00000003 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_16X16 0x00000004 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_32X32 0x00000005 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_64X64 0x00000006 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_128X128 0x00000007 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_256X256 0x00000008 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_512X512 0x00000009 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_U_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V 23:20 /* -WXUF */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_1X1 0x00000000 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_2X2 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_4X4 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_8X8 0x00000003 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_16X16 0x00000004 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_32X32 0x00000005 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_64X64 0x00000006 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_128X128 0x00000007 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_256X256 0x00000008 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_512X512 0x00000009 /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_055_FORMAT_BASE_SIZE_V_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSU 26:24 /* -WXUF */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSU_WRAP 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSU_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSU_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSU_BORDER 0x00000004 /* -W--V */
|
|
#define NV_055_FORMAT_WRAPU 27:27 /* -WXUF */
|
|
#define NV_055_FORMAT_WRAPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_FORMAT_WRAPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSV 30:28 /* -WXUF */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSV_WRAP 0x00000001 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSV_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSV_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_055_FORMAT_TEXTUREADDRESSV_BORDER 0x00000004 /* -W--V */
|
|
#define NV_055_FORMAT_WRAPV 31:31 /* -WXUF */
|
|
#define NV_055_FORMAT_WRAPV_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_FORMAT_WRAPV_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_FILTER(i) (0x005f0318+(i)*4) /* -W-4A */
|
|
#define NV_055_FILTER__SIZE_1 2 /* */
|
|
#define NV_055_FILTER_KERNEL_SIZE_X 7:0 /* -WXUF */
|
|
#define NV_055_FILTER_KERNEL_SIZE_Y 14:8 /* -WXUF */
|
|
#define NV_055_FILTER_MIPMAP_DITHER_ENABLE 15:15 /* -WXUF */
|
|
#define NV_055_FILTER_MIPMAP_DITHER_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_FILTER_MIPMAP_DITHER_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_FILTER_MIPMAPLODBIAS 23:16 /* -WXUF */
|
|
#define NV_055_FILTER_TEXTUREMIN 26:24 /* -WXUF */
|
|
#define NV_055_FILTER_TEXTUREMIN_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMIN_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMIN_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMIN_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_055_FILTER_ANISOTROPIC_MIN_ENABLE 27:27 /* -WXUF */
|
|
#define NV_055_FILTER_ANISOTROPIC_MIN_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_FILTER_ANISOTROPIC_MIN_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMAG 30:28 /* -WXUF */
|
|
#define NV_055_FILTER_TEXTUREMAG_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMAG_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMAG_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMAG_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMAG_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_055_FILTER_TEXTUREMAG_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_055_FILTER_ANISOTROPIC_MAG_ENABLE 31:31 /* -WXUF */
|
|
#define NV_055_FILTER_ANISOTROPIC_MAG_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_FILTER_ANISOTROPIC_MAG_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA 0x005f0320 /* -W-4R */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_0 0:0 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_0_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_0_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ALPHA_0 1:1 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0 7:2 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_0_TEXTURELOD 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_1 8:8 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_1_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_1_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ALPHA_1 9:9 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1 15:10 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_1_TEXTURELOD 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_2 16:16 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_2_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_2_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ALPHA_2 17:17 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2 23:18 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_2_TEXTURELOD 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_3 24:24 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_3_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_INVERSE_3_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ALPHA_3 25:25 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3 28:26 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_ARGUMENT_3_TEXTURELOD 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION 31:29 /* -WXVF */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_ADD 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_ADD2 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_ADD4 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_MUX 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_ALPHA_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR 0x005f0324 /* -W-4R */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_0 0:0 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_0_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_0_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_0 1:1 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_0_COLOR 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_0_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0 7:2 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_0_TEXTURELOD 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_1 8:8 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_1_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_1_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_1 9:9 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_1_COLOR 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_1_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1 15:10 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_1_TEXTURELOD 0x00000007 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_2 16:16 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_2_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_2_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_2 17:17 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_2_COLOR 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ALPHA_2_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_2 23:18 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
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|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_2_TEXTURELOD 0x00000007 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_INVERSE_3 24:24 /* -WXVF */
|
|
#define NV_055_COMBINE_0_COLOR_INVERSE_3_NORMAL 0x00000000 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_INVERSE_3_INVERSE 0x00000001 /* -W--V */
|
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#define NV_055_COMBINE_0_COLOR_ALPHA_3 25:25 /* -WXVF */
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|
#define NV_055_COMBINE_0_COLOR_ALPHA_3_COLOR 0x00000000 /* -W--V */
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|
#define NV_055_COMBINE_0_COLOR_ALPHA_3_ALPHA 0x00000001 /* -W--V */
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|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_3 28:26 /* -WXVF */
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|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
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|
#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_ARGUMENT_3_TEXTURELOD 0x00000007 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION 31:29 /* -WXVF */
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#define NV_055_COMBINE_0_COLOR_OPERATION_ADD 0x00000001 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION_ADD2 0x00000002 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION_ADD4 0x00000003 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION_MUX 0x00000005 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
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#define NV_055_COMBINE_0_COLOR_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA 0x005f032C /* -W-4R */
|
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#define NV_055_COMBINE_1_ALPHA_INVERSE_0 0:0 /* -WXVF */
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#define NV_055_COMBINE_1_ALPHA_INVERSE_0_NORMAL 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_INVERSE_0_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ALPHA_0 1:1 /* -WXVF */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0 7:2 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_INVERSE_1 8:8 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_INVERSE_1_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_INVERSE_1_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ALPHA_1 9:9 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1 15:10 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_INVERSE_2 16:16 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_INVERSE_2_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_INVERSE_2_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ALPHA_2 17:17 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2 23:18 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_INVERSE_3 24:24 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_INVERSE_3_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_INVERSE_3_INVERSE 0x00000001 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ALPHA_3 25:25 /* -WXVF */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3 28:26 /* -WXVF */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_OPERATION 31:29 /* -WXVF */
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|
#define NV_055_COMBINE_1_ALPHA_OPERATION_ADD 0x00000001 /* -W--V */
|
|
#define NV_055_COMBINE_1_ALPHA_OPERATION_ADD2 0x00000002 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_OPERATION_ADD4 0x00000003 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_OPERATION_MUX 0x00000005 /* -W--V */
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|
#define NV_055_COMBINE_1_ALPHA_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_ALPHA_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
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|
#define NV_055_COMBINE_1_COLOR 0x005f0330 /* -W-4R */
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#define NV_055_COMBINE_1_COLOR_INVERSE_0 0:0 /* -WXVF */
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|
#define NV_055_COMBINE_1_COLOR_INVERSE_0_NORMAL 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_0_INVERSE 0x00000001 /* -W--V */
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|
#define NV_055_COMBINE_1_COLOR_ALPHA_0 1:1 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ALPHA_0_COLOR 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_0_ALPHA 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0 7:2 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_1 8:8 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_INVERSE_1_NORMAL 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_1_INVERSE 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_1 9:9 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ALPHA_1_COLOR 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_1_ALPHA 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1 15:10 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_2 16:16 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_INVERSE_2_NORMAL 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_2_INVERSE 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_2 17:17 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ALPHA_2_COLOR 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_2_ALPHA 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2 23:18 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_3 24:24 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_INVERSE_3_NORMAL 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_INVERSE_3_INVERSE 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_3 25:25 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ALPHA_3_COLOR 0x00000000 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ALPHA_3_ALPHA 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3 28:26 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION 31:29 /* -WXVF */
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#define NV_055_COMBINE_1_COLOR_OPERATION_ADD 0x00000001 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION_ADD2 0x00000002 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION_ADD4 0x00000003 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION_MUX 0x00000005 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
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#define NV_055_COMBINE_1_COLOR_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
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#define NV_055_COMBINE_FACTOR 0x005f0334 /* -W-4R */
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#define NV_055_COMBINE_FACTOR_BLUE 7:0 /* -WXVF */
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#define NV_055_COMBINE_FACTOR_GREEN 15:8 /* -WXVF */
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#define NV_055_COMBINE_FACTOR_RED 23:16 /* -WXVF */
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#define NV_055_COMBINE_FACTOR_ALPHA 31:24 /* -WXVF */
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#define NV_055_BLEND 0x005f0338 /* -W-4R */
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#define NV_055_BLEND_MASK_BIT 5:0 /* -WXVF */
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#define NV_055_BLEND_MASK_BIT_LSB 0x00000010 /* -W--V */
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#define NV_055_BLEND_MASK_BIT_MSB 0x00000020 /* -W--V */
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#define NV_055_BLEND_SHADEMODE 7:6 /* -WXVF */
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#define NV_055_BLEND_SHADEMODE_FLAT 0x00000001 /* -W--V */
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#define NV_055_BLEND_SHADEMODE_GOURAUD 0x00000002 /* -W--V */
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#define NV_055_BLEND_SHADEMODE_PHONG 0x00000003 /* -W--V */
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#define NV_055_BLEND_TEXTUREPERSPECTIVE 11:8 /* -WXVF */
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#define NV_055_BLEND_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* -W--V */
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#define NV_055_BLEND_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* -W--V */
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#define NV_055_BLEND_SPECULARENABLE 15:12 /* -WXVF */
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#define NV_055_BLEND_SPECULARENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_055_BLEND_SPECULARENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_055_BLEND_FOGENABLE 19:16 /* -WXVF */
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#define NV_055_BLEND_FOGENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_055_BLEND_FOGENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_055_BLEND_ALPHABLENDENABLE 23:20 /* -WXVF */
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|
#define NV_055_BLEND_ALPHABLENDENABLE_FALSE 0x00000000 /* -W--V */
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|
#define NV_055_BLEND_ALPHABLENDENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_055_BLEND_SRCBLEND 27:24 /* -WXVF */
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#define NV_055_BLEND_SRCBLEND_ZERO 0x00000001 /* -W--V */
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|
#define NV_055_BLEND_SRCBLEND_ONE 0x00000002 /* -W--V */
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|
#define NV_055_BLEND_SRCBLEND_SRCCOLOR 0x00000003 /* -W--V */
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#define NV_055_BLEND_SRCBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
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#define NV_055_BLEND_SRCBLEND_SRCALPHA 0x00000005 /* -W--V */
|
|
#define NV_055_BLEND_SRCBLEND_INVSRCALPHA 0x00000006 /* -W--V */
|
|
#define NV_055_BLEND_SRCBLEND_DESTALPHA 0x00000007 /* -W--V */
|
|
#define NV_055_BLEND_SRCBLEND_INVDESTALPHA 0x00000008 /* -W--V */
|
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#define NV_055_BLEND_SRCBLEND_DESTCOLOR 0x00000009 /* -W--V */
|
|
#define NV_055_BLEND_SRCBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
|
|
#define NV_055_BLEND_SRCBLEND_SRCALPHASAT 0x0000000B /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND 31:28 /* -WXVF */
|
|
#define NV_055_BLEND_DESTBLEND_ZERO 0x00000001 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_ONE 0x00000002 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_SRCCOLOR 0x00000003 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_SRCALPHA 0x00000005 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_INVSRCALPHA 0x00000006 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_DESTALPHA 0x00000007 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_INVDESTALPHA 0x00000008 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_DESTCOLOR 0x00000009 /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
|
|
#define NV_055_BLEND_DESTBLEND_SRCALPHASAT 0x0000000B /* -W--V */
|
|
#define NV_055_CONTROL0 0x005f033C /* -W-4R */
|
|
#define NV_055_CONTROL0_ALPHAREF 7:0 /* -WXUF */
|
|
#define NV_055_CONTROL0_ALPHAFUNC 11:8 /* -WXVF */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHAFUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHATESTENABLE 12:12 /* -WXVF */
|
|
#define NV_055_CONTROL0_ALPHATESTENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHATESTENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ORIGIN 13:13 /* -WXVF */
|
|
#define NV_055_CONTROL0_ORIGIN_CENTER 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_ORIGIN_CORNER 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ZENABLE 15:14 /* -WXVF */
|
|
#define NV_055_CONTROL0_ZENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_ZENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC 19:16 /* -WXVF */
|
|
#define NV_055_CONTROL0_ZFUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_055_CONTROL0_ZFUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_055_CONTROL0_CULLMODE 21:20 /* -WXVF */
|
|
#define NV_055_CONTROL0_CULLMODE_NONE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_CULLMODE_CW 0x00000002 /* -W--V */
|
|
#define NV_055_CONTROL0_CULLMODE_CCW 0x00000003 /* -W--V */
|
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#define NV_055_CONTROL0_DITHERENABLE 22:22 /* -WXVF */
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|
#define NV_055_CONTROL0_DITHERENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_DITHERENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_055_CONTROL0_Z_PERSPECTIVE_ENABLE 23:23 /* -WXVF */
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|
#define NV_055_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ZWRITEENABLE 24:24 /* -WXVF */
|
|
#define NV_055_CONTROL0_ZWRITEENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_ZWRITEENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_STENCIL_WRITE_ENABLE 25:25 /* -WXVF */
|
|
#define NV_055_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHA_WRITE_ENABLE 26:26 /* -WXVF */
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|
#define NV_055_CONTROL0_ALPHA_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_ALPHA_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_RED_WRITE_ENABLE 27:27 /* -WXVF */
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|
#define NV_055_CONTROL0_RED_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_055_CONTROL0_RED_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_GREEN_WRITE_ENABLE 28:28 /* -WXVF */
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|
#define NV_055_CONTROL0_GREEN_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_055_CONTROL0_GREEN_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
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#define NV_055_CONTROL0_BLUE_WRITE_ENABLE 29:29 /* -WXVF */
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|
#define NV_055_CONTROL0_BLUE_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
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#define NV_055_CONTROL0_BLUE_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_Z_FORMAT 31:30 /* -WXVF */
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|
#define NV_055_CONTROL0_Z_FORMAT_FIXED 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL0_Z_FORMAT_FLOAT 0x00000002 /* -W--V */
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#define NV_055_CONTROL1 0x005f0340 /* -W-4R */
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#define NV_055_CONTROL1_STENCIL_TEST_ENABLE 3:0 /* -WXVF */
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#define NV_055_CONTROL1_STENCIL_TEST_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_055_CONTROL1_STENCIL_TEST_ENABLE_TRUE 0x00000001 /* -W--V */
|
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#define NV_055_CONTROL1_STENCIL_FUNC 7:4 /* -WXVF */
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#define NV_055_CONTROL1_STENCIL_FUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL1_STENCIL_FUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_055_CONTROL1_STENCIL_FUNC_EQUAL 0x00000003 /* -W--V */
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#define NV_055_CONTROL1_STENCIL_FUNC_LESSEQUAL 0x00000004 /* -W--V */
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#define NV_055_CONTROL1_STENCIL_FUNC_GREATER 0x00000005 /* -W--V */
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#define NV_055_CONTROL1_STENCIL_FUNC_NOTEQUAL 0x00000006 /* -W--V */
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|
#define NV_055_CONTROL1_STENCIL_FUNC_GREATEREQUAL 0x00000007 /* -W--V */
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#define NV_055_CONTROL1_STENCIL_FUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_055_CONTROL1_STENCIL_REF 15:8 /* -WXUF */
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#define NV_055_CONTROL1_STENCIL_MASK_READ 23:16 /* -WXUF */
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#define NV_055_CONTROL1_STENCIL_MASK_WRITE 31:24 /* -WXUF */
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#define NV_055_CONTROL2 0x005f0344 /* -W-4R */
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#define NV_055_CONTROL2_STENCIL_OP_FAIL 3:0 /* -WXVF */
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|
#define NV_055_CONTROL2_STENCIL_OP_FAIL_KEEP 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_FAIL_ZERO 0x00000002 /* -W--V */
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#define NV_055_CONTROL2_STENCIL_OP_FAIL_REPLACE 0x00000003 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_FAIL_INCRSAT 0x00000004 /* -W--V */
|
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#define NV_055_CONTROL2_STENCIL_OP_FAIL_DECRSAT 0x00000005 /* -W--V */
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#define NV_055_CONTROL2_STENCIL_OP_FAIL_INVERT 0x00000006 /* -W--V */
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|
#define NV_055_CONTROL2_STENCIL_OP_FAIL_INCR 0x00000007 /* -W--V */
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|
#define NV_055_CONTROL2_STENCIL_OP_FAIL_DECR 0x00000008 /* -W--V */
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#define NV_055_CONTROL2_STENCIL_OP_ZFAIL 7:4 /* -WXVF */
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|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_KEEP 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_ZERO 0x00000002 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_REPLACE 0x00000003 /* -W--V */
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|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_INCRSAT 0x00000004 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_DECRSAT 0x00000005 /* -W--V */
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|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_INVERT 0x00000006 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_INCR 0x00000007 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZFAIL_DECR 0x00000008 /* -W--V */
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|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS 31:8 /* -WXVF */
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|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_KEEP 0x00000001 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_ZERO 0x00000002 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_REPLACE 0x00000003 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_INCRSAT 0x00000004 /* -W--V */
|
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#define NV_055_CONTROL2_STENCIL_OP_ZPASS_DECRSAT 0x00000005 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_INVERT 0x00000006 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_INCR 0x00000007 /* -W--V */
|
|
#define NV_055_CONTROL2_STENCIL_OP_ZPASS_DECR 0x00000008 /* -W--V */
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|
#define NV_055_FOGCOLOR 0x005f0348 /* -W-4R */
|
|
#define NV_055_FOGCOLOR_VALUE 31:0 /* -WXUF */
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|
#define NV_055_TLMTVERTEX_SX(i) (0x005f0400+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_SX__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_SX_VALUE 31:0 /* -WXFF */
|
|
#define NV_055_TLMTVERTEX_SY(i) (0x005f0404+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_SY__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_SY_VALUE 31:0 /* -WXFF */
|
|
#define NV_055_TLMTVERTEX_SZ(i) (0x005f0408+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_SZ__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_SZ_VALUE 31:0 /* -WXFF */
|
|
#define NV_055_TLMTVERTEX_RHW(i) (0x005f040c+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_RHW__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_RHW_VALUE 31:0 /* -WXFF */
|
|
#define NV_055_TLMTVERTEX_COLOR(i) (0x005f0410+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_COLOR__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_COLOR_VALUE 31:0 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_COLOR_BLUE 7:0 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_COLOR_GREEN 15:8 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_COLOR_RED 23:16 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_COLOR_ALPHA 31:24 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_SPECULAR(i) (0x005f0414+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_SPECULAR__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_SPECULAR_VALUE 31:0 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_SPECULAR_BLUE 7:0 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_SPECULAR_GREEN 15:8 /* -WXUF */
|
|
#define NV_055_TLMTVERTEX_SPECULAR_RED 23:16 /* -WXUF */
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#define NV_055_TLMTVERTEX_SPECULAR_FOG 31:24 /* -WXUF */
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#define NV_055_TLMTVERTEX_TU0(i) (0x005f0418+(i)*40) /* -W-4A */
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|
#define NV_055_TLMTVERTEX_TU0__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_TU0_VALUE 31:0 /* -WXFF */
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|
#define NV_055_TLMTVERTEX_TV0(i) (0x005f041c+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_TV0__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_TV0_VALUE 31:0 /* -WXFF */
|
|
#define NV_055_TLMTVERTEX_TU1(i) (0x005f0420+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_TU1__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_TU1_VALUE 31:0 /* -WXFF */
|
|
#define NV_055_TLMTVERTEX_TV1(i) (0x005f0424+(i)*40) /* -W-4A */
|
|
#define NV_055_TLMTVERTEX_TV1__SIZE_1 8 /* */
|
|
#define NV_055_TLMTVERTEX_TV1_VALUE 31:0 /* -WXFF */
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|
#define NV_055_TLMTVERTEX_DRAWPRIMITIVE(i) (0x005f0540+(i)*4) /* -W-4A */
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|
#define NV_055_TLMTVERTEX_DRAWPRIMITIVE__SIZE_1 48 /* */
|
|
#define NV_055_TLMTVERTEX_DRAWPRIMITIVE_I0 3:0 /* -WXUF */
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|
#define NV_055_TLMTVERTEX_DRAWPRIMITIVE_I1 7:4 /* -WXUF */
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#define NV_055_TLMTVERTEX_DRAWPRIMITIVE_I2 11:8 /* -WXUF */
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#define NV_055_TLMTVERTEX_DRAWPRIMITIVE_I3 15:12 /* -WXUF */
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#define NV_055_TLMTVERTEX_DRAWPRIMITIVE_I4 19:16 /* -WXUF */
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#define NV_055_TLMTVERTEX_DRAWPRIMITIVE_I5 31:20 /* -WXUF */
|
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/* usr_nv10_dx5_textured_triangle.ref */
|
|
#define NV10_DX5_TEXTURE_TRIANGLE 0x00000094 /* ----C */
|
|
#define NV_094 0x00591FFF:0x00590000 /* -W--D */
|
|
#define NV_094_NV10_DX5_TEXTURE_TRIANGLE 0x00590000 /* -W-4R */
|
|
#define NV_094_NV10_DX5_TEXTURE_TRIANGLE_HANDLE 31:0 /* -WXVF */
|
|
#define NV_094_NOP 0x00590100 /* -W-4R */
|
|
#define NV_094_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_094_NOTIFY 0x00590104 /* -W-4R */
|
|
#define NV_094_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_094_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_094_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_094_NOTIFY__ALIAS_1 NV_094_SET NOTIFY /* */
|
|
#define NV_094_SET_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_094_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_094_SET_CONTEXT_DMA_NOTIFY 0x00590180 /* -W-4R */
|
|
#define NV_094_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_094_SET_CONTEXT_DMA_A 0x00590184 /* -W-4R */
|
|
#define NV_094_SET_CONTEXT_DMA_A_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_094_SET_CONTEXT_DMA_B 0x00590188 /* -W-4R */
|
|
#define NV_094_SET_CONTEXT_DMA_B_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_094_SET_CONTEXT_SURFACES 0x0059018c /* -W-4R */
|
|
#define NV_094_SET_CONTEXT_SURFACES_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_094_COLORKEY 0x00590300 /* -W-4R */
|
|
#define NV_094_COLORKEY_VALUE 31:0 /* -WXUF */
|
|
#define NV_094_OFFSET 0x00590304 /* -W-4R */
|
|
#define NV_094_OFFSET_VALUE 31:0 /* -WXUF */
|
|
#define NV_094_FORMAT 0x00590308 /* -W-4R */
|
|
#define NV_094_FORMAT_CONTEXT_DMA 1:0 /* -WXUF */
|
|
#define NV_094_FORMAT_CONTEXT_DMA_A 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_CONTEXT_DMA_B 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_COLORKEYENABLE 3:2 /* -WXUF */
|
|
#define NV_094_FORMAT_COLORKEYENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_094_FORMAT_COLORKEYENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_ORIGIN_ZOH 5:4 /* -WXUF */
|
|
#define NV_094_FORMAT_ORIGIN_ZOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_ORIGIN_ZOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_ORIGIN_FOH 7:6 /* -WXUF */
|
|
#define NV_094_FORMAT_ORIGIN_FOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_ORIGIN_FOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR 11:8 /* -WXUF */
|
|
#define NV_094_FORMAT_COLOR_LE_Y8 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR_LE_A4R4G4B4 0x00000004 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR_LE_R5G6B5 0x00000005 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR_LE_A8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_094_FORMAT_COLOR_LE_X8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_094_FORMAT_MIPMAP_LEVELS 15:12 /* -WXUF */
|
|
#define NV_094_FORMAT_BASE_SIZE_U 19:16 /* -WXUF */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_1X1 0x00000000 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_2X2 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_4X4 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_8X8 0x00000003 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_16X16 0x00000004 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_32X32 0x00000005 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_64X64 0x00000006 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_128X128 0x00000007 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_256X256 0x00000008 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_512X512 0x00000009 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_U_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V 23:20 /* -WXUF */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_1X1 0x00000000 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_2X2 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_4X4 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_8X8 0x00000003 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_16X16 0x00000004 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_32X32 0x00000005 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_64X64 0x00000006 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_128X128 0x00000007 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_256X256 0x00000008 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_512X512 0x00000009 /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_094_FORMAT_BASE_SIZE_V_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSU 26:24 /* -WXUF */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSU_WRAP 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSU_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSU_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSU_BORDER 0x00000004 /* -W--V */
|
|
#define NV_094_FORMAT_WRAPU 27:27 /* -WXUF */
|
|
#define NV_094_FORMAT_WRAPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_094_FORMAT_WRAPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSV 30:28 /* -WXUF */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSV_WRAP 0x00000001 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSV_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSV_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_094_FORMAT_TEXTUREADDRESSV_BORDER 0x00000004 /* -W--V */
|
|
#define NV_094_FORMAT_WRAPV 31:31 /* -WXUF */
|
|
#define NV_094_FORMAT_WRAPV_FALSE 0x00000000 /* -W--V */
|
|
#define NV_094_FORMAT_WRAPV_TRUE 0x00000001 /* -W--V */
|
|
#define NV_094_FILTER 0x0059030c /* -W-4R */
|
|
#define NV_094_FILTER_KERNEL_SIZE_X 7:0 /* -WXUF */
|
|
#define NV_094_FILTER_KERNEL_SIZE_Y 14:8 /* -WXUF */
|
|
#define NV_094_FILTER_MIPMAP_DITHER_ENABLE 15:15 /* -WXUF */
|
|
#define NV_094_FILTER_MIPMAP_DITHER_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_094_FILTER_MIPMAP_DITHER_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_094_FILTER_MIPMAPLODBIAS 23:16 /* -WXUF */
|
|
#define NV_094_FILTER_TEXTUREMIN 26:24 /* -WXUF */
|
|
#define NV_094_FILTER_TEXTUREMIN_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMIN_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMIN_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMIN_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_094_FILTER_ANISOTROPIC_MIN_ENABLE 27:27 /* -WXUF */
|
|
#define NV_094_FILTER_ANISOTROPIC_MIN_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_094_FILTER_ANISOTROPIC_MIN_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMAG 30:28 /* -WXUF */
|
|
#define NV_094_FILTER_TEXTUREMAG_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMAG_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMAG_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMAG_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMAG_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_094_FILTER_TEXTUREMAG_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_094_FILTER_ANISOTROPIC_MAG_ENABLE 31:31 /* -WXUF */
|
|
#define NV_094_FILTER_ANISOTROPIC_MAG_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_094_FILTER_ANISOTROPIC_MAG_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_094_BLEND 0x00590310 /* -W-4R */
|
|
#define NV_094_BLEND_TEXTUREMAPBLEND 3:0 /* -WXVF */
|
|
#define NV_094_BLEND_TEXTUREMAPBLEND_DECAL 0x00000001 /* -W--V */
|
|
#define NV_094_BLEND_TEXTUREMAPBLEND_MODULATE 0x00000002 /* -W--V */
|
|
#define NV_094_BLEND_TEXTUREMAPBLEND_DECALALPHA 0x00000003 /* -W--V */
|
|
#define NV_094_BLEND_TEXTUREMAPBLEND_MODULATEALPHA 0x00000004 /* -W--V */
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#define NV_094_BLEND_TEXTUREMAPBLEND_DECALMASK 0x00000005 /* -W--V */
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#define NV_094_BLEND_TEXTUREMAPBLEND_MODULATEMASK 0x00000006 /* -W--V */
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#define NV_094_BLEND_TEXTUREMAPBLEND_COPY 0x00000007 /* -W--V */
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|
#define NV_094_BLEND_TEXTUREMAPBLEND_ADD 0x00000008 /* -W--V */
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|
#define NV_094_BLEND_OPERATION 5:4 /* -WXVF */
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#define NV_094_BLEND_OPERATION_MUX_TALPHALSB 0x00000001 /* -W--V */
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#define NV_094_BLEND_OPERATION_MUX_TALPHAMSB 0x00000002 /* -W--V */
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#define NV_094_BLEND_SHADEMODE 7:6 /* -WXVF */
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|
#define NV_094_BLEND_SHADEMODE_FLAT 0x00000001 /* -W--V */
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|
#define NV_094_BLEND_SHADEMODE_GOURAUD 0x00000002 /* -W--V */
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|
#define NV_094_BLEND_SHADEMODE_PHONG 0x00000003 /* -W--V */
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#define NV_094_BLEND_TEXTUREPERSPECTIVE 11:8 /* -WXVF */
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#define NV_094_BLEND_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* -W--V */
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#define NV_094_BLEND_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* -W--V */
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#define NV_094_BLEND_SPECULARENABLE 15:12 /* -WXVF */
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#define NV_094_BLEND_SPECULARENABLE_FALSE 0x00000000 /* -W--V */
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|
#define NV_094_BLEND_SPECULARENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_094_BLEND_FOGENABLE 19:16 /* -WXVF */
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#define NV_094_BLEND_FOGENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_094_BLEND_FOGENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_094_BLEND_ALPHABLENDENABLE 23:20 /* -WXVF */
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#define NV_094_BLEND_ALPHABLENDENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_094_BLEND_ALPHABLENDENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_094_BLEND_SRCBLEND 27:24 /* -WXVF */
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#define NV_094_BLEND_SRCBLEND_ZERO 0x00000001 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_ONE 0x00000002 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_SRCCOLOR 0x00000003 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_SRCALPHA 0x00000005 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_INVSRCALPHA 0x00000006 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_DESTALPHA 0x00000007 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_INVDESTALPHA 0x00000008 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_DESTCOLOR 0x00000009 /* -W--V */
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#define NV_094_BLEND_SRCBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
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#define NV_094_BLEND_SRCBLEND_SRCALPHASAT 0x0000000B /* -W--V */
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#define NV_094_BLEND_DESTBLEND 31:28 /* -WXVF */
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#define NV_094_BLEND_DESTBLEND_ZERO 0x00000001 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_ONE 0x00000002 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_SRCCOLOR 0x00000003 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_SRCALPHA 0x00000005 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_INVSRCALPHA 0x00000006 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_DESTALPHA 0x00000007 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_INVDESTALPHA 0x00000008 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_DESTCOLOR 0x00000009 /* -W--V */
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#define NV_094_BLEND_DESTBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
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#define NV_094_BLEND_DESTBLEND_SRCALPHASAT 0x0000000B /* -W--V */
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#define NV_094_CONTROL 0x00590314 /* -W-4R */
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#define NV_094_CONTROL_ALPHAREF 7:0 /* -WXUF */
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#define NV_094_CONTROL_ALPHAFUNC 11:8 /* -WXVF */
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#define NV_094_CONTROL_ALPHAFUNC_NEVER 0x00000001 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_LESS 0x00000002 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_EQUAL 0x00000003 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_LESSEQUAL 0x00000004 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_GREATER 0x00000005 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_NOTEQUAL 0x00000006 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_GREATEREQUAL 0x00000007 /* -W--V */
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#define NV_094_CONTROL_ALPHAFUNC_ALWAYS 0x00000008 /* -W--V */
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#define NV_094_CONTROL_ALPHATESTENABLE 12:12 /* -WXVF */
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#define NV_094_CONTROL_ALPHATESTENABLE_FALSE 0x00000000 /* -W--V */
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|
#define NV_094_CONTROL_ALPHATESTENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_094_CONTROL_ORIGIN 13:13 /* -WXVF */
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#define NV_094_CONTROL_ORIGIN_CENTER 0x00000000 /* -W--V */
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#define NV_094_CONTROL_ORIGIN_CORNER 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_ZENABLE 15:14 /* -WXVF */
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|
#define NV_094_CONTROL_ZENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_094_CONTROL_ZENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC 19:16 /* -WXVF */
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|
#define NV_094_CONTROL_ZFUNC_NEVER 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC_LESS 0x00000002 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC_EQUAL 0x00000003 /* -W--V */
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#define NV_094_CONTROL_ZFUNC_LESSEQUAL 0x00000004 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC_GREATER 0x00000005 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC_NOTEQUAL 0x00000006 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC_GREATEREQUAL 0x00000007 /* -W--V */
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|
#define NV_094_CONTROL_ZFUNC_ALWAYS 0x00000008 /* -W--V */
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|
#define NV_094_CONTROL_CULLMODE 21:20 /* -WXVF */
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|
#define NV_094_CONTROL_CULLMODE_NONE 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_CULLMODE_CW 0x00000002 /* -W--V */
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|
#define NV_094_CONTROL_CULLMODE_CCW 0x00000003 /* -W--V */
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#define NV_094_CONTROL_DITHERENABLE 22:22 /* -WXVF */
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|
#define NV_094_CONTROL_DITHERENABLE_FALSE 0x00000000 /* -W--V */
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|
#define NV_094_CONTROL_DITHERENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_Z_PERSPECTIVE_ENABLE 23:23 /* -WXVF */
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|
#define NV_094_CONTROL_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* -W--V */
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|
#define NV_094_CONTROL_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_ZWRITEENABLE 29:24 /* -WXVF */
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|
#define NV_094_CONTROL_ZWRITEENABLE_FALSE 0x00000000 /* -W--V */
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|
#define NV_094_CONTROL_ZWRITEENABLE_TRUE 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_Z_FORMAT 31:30 /* -WXVF */
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#define NV_094_CONTROL_Z_FORMAT_FIXED 0x00000001 /* -W--V */
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|
#define NV_094_CONTROL_Z_FORMAT_FLOAT 0x00000002 /* -W--V */
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|
#define NV_094_FOGCOLOR 0x00590318 /* -W-4R */
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|
#define NV_094_FOGCOLOR_VALUE 31:0 /* -WXUF */
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|
#define NV_094_TLVERTEX_SX(i) (0x00590400+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_SX__SIZE_1 16 /* */
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|
#define NV_094_TLVERTEX_SX_VALUE 31:0 /* -WXFF */
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#define NV_094_TLVERTEX_SY(i) (0x00590404+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_SY__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_SY_VALUE 31:0 /* -WXFF */
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#define NV_094_TLVERTEX_SZ(i) (0x00590408+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_SZ__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_SZ_VALUE 31:0 /* -WXFF */
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#define NV_094_TLVERTEX_RHW(i) (0x0059040c+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_RHW__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_RHW_VALUE 31:0 /* -WXFF */
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#define NV_094_TLVERTEX_COLOR(i) (0x00590410+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_COLOR__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_COLOR_VALUE 31:0 /* -WXUF */
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#define NV_094_TLVERTEX_COLOR_BLUE 7:0 /* -WXUF */
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#define NV_094_TLVERTEX_COLOR_GREEN 15:8 /* -WXUF */
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#define NV_094_TLVERTEX_COLOR_RED 23:16 /* -WXUF */
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#define NV_094_TLVERTEX_COLOR_ALPHA 31:24 /* -WXUF */
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#define NV_094_TLVERTEX_SPECULAR(i) (0x00590414+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_SPECULAR__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_SPECULAR_VALUE 31:0 /* -WXUF */
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#define NV_094_TLVERTEX_SPECULAR_BLUE 7:0 /* -WXUF */
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#define NV_094_TLVERTEX_SPECULAR_GREEN 15:8 /* -WXUF */
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#define NV_094_TLVERTEX_SPECULAR_RED 23:16 /* -WXUF */
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#define NV_094_TLVERTEX_SPECULAR_FOG 31:24 /* -WXUF */
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#define NV_094_TLVERTEX_TU(i) (0x00590418+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_TU__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_TU_VALUE 31:0 /* -WXFF */
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#define NV_094_TLVERTEX_TV(i) (0x0059041c+(i)*32) /* -W-4A */
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#define NV_094_TLVERTEX_TV__SIZE_1 16 /* */
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#define NV_094_TLVERTEX_TV_VALUE 31:0 /* -WXFF */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE(i) (0x00590600+(i)*4) /* -W-4A */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE__SIZE_1 64 /* */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE_I0 3:0 /* -WXUF */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE_I1 7:4 /* -WXUF */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE_I2 11:8 /* -WXUF */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE_I3 15:12 /* -WXUF */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE_I4 19:16 /* -WXUF */
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#define NV_094_TLVERTEX_DRAWPRIMITIVE_I5 31:20 /* -WXUF */
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|
/* usr_nv10_dx6_multitextured_triangle.ref */
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#define NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x00000095 /* ----C */
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#define NV_095 0x005a1FFF:0x005a0000 /* -W--D */
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#define NV_095_NV10_DX6_MULTI_TEXTURE_TRIANGLE 0x005a0000 /* -W-4R */
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#define NV_095_NV10_DX6_MULTI_TEXTURE_TRIANGLE_HANDLE 31:0 /* -WXVF */
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#define NV_095_NOP 0x005a0100 /* -W-4R */
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#define NV_095_NOP_PARAMETER 31:0 /* -WXVF */
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|
#define NV_095_NOTIFY 0x005a0104 /* -W-4R */
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|
#define NV_095_NOTIFY_STYLE 31:0 /* -WXVF */
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|
#define NV_095_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
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|
#define NV_095_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
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|
#define NV_095_SET_CONTEXT_DMA_NOTIFY 0x005a0180 /* -W-4R */
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|
#define NV_095_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
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|
#define NV_095_SET_CONTEXT_DMA_A 0x005a0184 /* -W-4R */
|
|
#define NV_095_SET_CONTEXT_DMA_A_PARAMETER 31:0 /* -WXVF */
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|
#define NV_095_SET_CONTEXT_DMA_B 0x005a0188 /* -W-4R */
|
|
#define NV_095_SET_CONTEXT_DMA_B_PARAMETER 31:0 /* -WXVF */
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|
#define NV_095_SET_CONTEXT_SURFACES 0x005a018c /* -W-4R */
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|
#define NV_095_SET_CONTEXT_SURFACES_PARAMETER 31:0 /* -WXVF */
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|
#define NV_095_OFFSET(i) (0x005a0308+(i)*4) /* -W-4A */
|
|
#define NV_095_OFFSET__SIZE_1 2 /* */
|
|
#define NV_095_OFFSET_VALUE 31:0 /* -WXUF */
|
|
#define NV_095_FORMAT(i) (0x005a0310+(i)*4) /* -W-4A */
|
|
#define NV_095_FORMAT__SIZE_1 2 /* */
|
|
#define NV_095_FORMAT_CONTEXT_DMA 3:0 /* -WXUF */
|
|
#define NV_095_FORMAT_CONTEXT_DMA_A 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_CONTEXT_DMA_B 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_ORIGIN_ZOH 5:4 /* -WXUF */
|
|
#define NV_095_FORMAT_ORIGIN_ZOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_ORIGIN_ZOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_ORIGIN_FOH 7:6 /* -WXUF */
|
|
#define NV_095_FORMAT_ORIGIN_FOH_CENTER 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_ORIGIN_FOH_CORNER 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR 11:8 /* -WXUF */
|
|
#define NV_095_FORMAT_COLOR_LE_AY8 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR_LE_A4R4G4G4 0x00000004 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR_LE_R5G6B5 0x00000005 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR_LE_A8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_095_FORMAT_COLOR_LE_X8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS 15:12 /* -WXUF */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_1 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_2 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_3 0x00000003 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_4 0x00000004 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_5 0x00000005 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_6 0x00000006 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_7 0x00000007 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_8 0x00000008 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_9 0x00000009 /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_10 0x0000000A /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_11 0x0000000B /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_12 0x0000000C /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_13 0x0000000D /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_14 0x0000000E /* -W--V */
|
|
#define NV_095_FORMAT_MIPMAP_LEVELS_15 0x0000000F /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U 19:16 /* -WXUF */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_1X1 0x00000000 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_2X2 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_4X4 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_8X8 0x00000003 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_16X16 0x00000004 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_32X32 0x00000005 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_64X64 0x00000006 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_128X128 0x00000007 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_256X256 0x00000008 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_512X512 0x00000009 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_U_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V 23:20 /* -WXUF */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_1X1 0x00000000 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_2X2 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_4X4 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_8X8 0x00000003 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_16X16 0x00000004 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_32X32 0x00000005 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_64X64 0x00000006 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_128X128 0x00000007 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_256X256 0x00000008 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_512X512 0x00000009 /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_1024X1024 0x0000000A /* -W--V */
|
|
#define NV_095_FORMAT_BASE_SIZE_V_2048X2048 0x0000000B /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSU 26:24 /* -WXUF */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSU_WRAP 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSU_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSU_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSU_BORDER 0x00000004 /* -W--V */
|
|
#define NV_095_FORMAT_WRAPU 27:27 /* -WXUF */
|
|
#define NV_095_FORMAT_WRAPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_FORMAT_WRAPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSV 30:28 /* -WXUF */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSV_WRAP 0x00000001 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSV_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSV_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_095_FORMAT_TEXTUREADDRESSV_BORDER 0x00000004 /* -W--V */
|
|
#define NV_095_FORMAT_WRAPV 31:31 /* -WXUF */
|
|
#define NV_095_FORMAT_WRAPV_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_FORMAT_WRAPV_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_FILTER(i) (0x005a0318+(i)*4) /* -W-4A */
|
|
#define NV_095_FILTER__SIZE_1 2 /* */
|
|
#define NV_095_FILTER_KERNEL_SIZE_X 7:0 /* -WXUF */
|
|
#define NV_095_FILTER_KERNEL_SIZE_Y 14:8 /* -WXUF */
|
|
#define NV_095_FILTER_MIPMAP_DITHER_ENABLE 15:15 /* -WXUF */
|
|
#define NV_095_FILTER_MIPMAP_DITHER_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_FILTER_MIPMAP_DITHER_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_FILTER_MIPMAPLODBIAS 23:16 /* -WXUF */
|
|
#define NV_095_FILTER_TEXTUREMIN 26:24 /* -WXUF */
|
|
#define NV_095_FILTER_TEXTUREMIN_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_095_FILTER_TEXTUREMIN_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_095_FILTER_TEXTUREMIN_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_095_FILTER_TEXTUREMIN_MIPLINEAR 0x00000004 /* -W--V */
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#define NV_095_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x00000005 /* -W--V */
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#define NV_095_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x00000006 /* -W--V */
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#define NV_095_FILTER_ANISOTROPIC_MIN_ENABLE 27:27 /* -WXUF */
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#define NV_095_FILTER_ANISOTROPIC_MIN_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_095_FILTER_ANISOTROPIC_MIN_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_095_FILTER_TEXTUREMAG 30:28 /* -WXUF */
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#define NV_095_FILTER_TEXTUREMAG_NEAREST 0x00000001 /* -W--V */
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#define NV_095_FILTER_TEXTUREMAG_LINEAR 0x00000002 /* -W--V */
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#define NV_095_FILTER_TEXTUREMAG_MIPNEAREST 0x00000003 /* -W--V */
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#define NV_095_FILTER_TEXTUREMAG_MIPLINEAR 0x00000004 /* -W--V */
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#define NV_095_FILTER_TEXTUREMAG_LINEARMIPNEAREST 0x00000005 /* -W--V */
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#define NV_095_FILTER_TEXTUREMAG_LINEARMIPLINEAR 0x00000006 /* -W--V */
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#define NV_095_FILTER_ANISOTROPIC_MAG_ENABLE 31:31 /* -WXUF */
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#define NV_095_FILTER_ANISOTROPIC_MAG_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_095_FILTER_ANISOTROPIC_MAG_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA 0x005a0320 /* -W-4R */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_0 0:0 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_0_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_0_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ALPHA_0 1:1 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0 7:2 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_1 8:8 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_1_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_1_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ALPHA_1 9:9 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1 15:10 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_2 16:16 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_2_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_2_INVERSE 0x00000001 /* -W--V */
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|
#define NV_095_COMBINE_0_ALPHA_ALPHA_2 17:17 /* -WXVF */
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|
#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2 23:18 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
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|
#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_3 24:24 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_3_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_INVERSE_3_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ALPHA_3 25:25 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3 28:26 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
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|
#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_OPERATION 31:29 /* -WXVF */
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#define NV_095_COMBINE_0_ALPHA_OPERATION_ADD 0x00000001 /* -W--V */
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|
#define NV_095_COMBINE_0_ALPHA_OPERATION_ADD2 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_OPERATION_ADD4 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_OPERATION_MUX 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_ALPHA_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
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#define NV_095_COMBINE_0_COLOR 0x005a0324 /* -W-4R */
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|
#define NV_095_COMBINE_0_COLOR_INVERSE_0 0:0 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_INVERSE_0_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_0_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_0 1:1 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ALPHA_0_COLOR 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_0_ALPHA 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0 7:2 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_1 8:8 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_INVERSE_1_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_1_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_1 9:9 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ALPHA_1_COLOR 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_1_ALPHA 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1 15:10 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_2 16:16 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_INVERSE_2_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_2_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_2 17:17 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ALPHA_2_COLOR 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_2_ALPHA 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2 23:18 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_3 24:24 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_INVERSE_3_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_INVERSE_3_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_3 25:25 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ALPHA_3_COLOR 0x00000000 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ALPHA_3_ALPHA 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3 28:26 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION 31:29 /* -WXVF */
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#define NV_095_COMBINE_0_COLOR_OPERATION_ADD 0x00000001 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION_ADD2 0x00000002 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION_ADD4 0x00000003 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION_MUX 0x00000005 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
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#define NV_095_COMBINE_0_COLOR_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA 0x005a032C /* -W-4R */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_0 0:0 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_0_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_0_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ALPHA_0 1:1 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0 7:2 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_1 8:8 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_1_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_1_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ALPHA_1 9:9 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1 15:10 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_2 16:16 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_2_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_2_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ALPHA_2 17:17 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2 23:18 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_3 24:24 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_3_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_INVERSE_3_INVERSE 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ALPHA_3 25:25 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3 28:26 /* -WXVF */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_OPERATION 31:29 /* -WXVF */
|
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#define NV_095_COMBINE_1_ALPHA_OPERATION_ADD 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_ALPHA_OPERATION_ADD2 0x00000002 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_OPERATION_ADD4 0x00000003 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_OPERATION_MUX 0x00000005 /* -W--V */
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#define NV_095_COMBINE_1_ALPHA_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
|
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#define NV_095_COMBINE_1_ALPHA_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR 0x005a0330 /* -W-4R */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_0 0:0 /* -WXVF */
|
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#define NV_095_COMBINE_1_COLOR_INVERSE_0_NORMAL 0x00000000 /* -W--V */
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#define NV_095_COMBINE_1_COLOR_INVERSE_0_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_0 1:1 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_0_COLOR 0x00000000 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_0_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0 7:2 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0_ZERO 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0_INPUT 0x00000004 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_0_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_1 8:8 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_1_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_1_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_1 9:9 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_1_COLOR 0x00000000 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_1_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1 15:10 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1_ZERO 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1_INPUT 0x00000004 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_1_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_2 16:16 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_2_NORMAL 0x00000000 /* -W--V */
|
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#define NV_095_COMBINE_1_COLOR_INVERSE_2_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_2 17:17 /* -WXVF */
|
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#define NV_095_COMBINE_1_COLOR_ALPHA_2_COLOR 0x00000000 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_2_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2 23:18 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2_ZERO 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2_INPUT 0x00000004 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_2_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_3 24:24 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_3_NORMAL 0x00000000 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_INVERSE_3_INVERSE 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_3 25:25 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_3_COLOR 0x00000000 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ALPHA_3_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3 28:26 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3_ZERO 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3_FACTOR 0x00000002 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3_DIFFUSE 0x00000003 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3_INPUT 0x00000004 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3_TEXTURE0 0x00000005 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_ARGUMENT_3_TEXTURE1 0x00000006 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION 31:29 /* -WXVF */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_ADD 0x00000001 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_ADD2 0x00000002 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_ADD4 0x00000003 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_ADDSIGNED 0x00000004 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_MUX 0x00000005 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_ADDCOMPLEMENT 0x00000006 /* -W--V */
|
|
#define NV_095_COMBINE_1_COLOR_OPERATION_ADDSIGNED2 0x00000007 /* -W--V */
|
|
#define NV_095_COMBINE_FACTOR 0x005a0334 /* -W-4R */
|
|
#define NV_095_COMBINE_FACTOR_BLUE 7:0 /* -WXVF */
|
|
#define NV_095_COMBINE_FACTOR_GREEN 15:8 /* -WXVF */
|
|
#define NV_095_COMBINE_FACTOR_RED 23:16 /* -WXVF */
|
|
#define NV_095_COMBINE_FACTOR_ALPHA 31:24 /* -WXVF */
|
|
#define NV_095_BLEND 0x005a0338 /* -W-4R */
|
|
#define NV_095_BLEND_MASK_BIT 5:0 /* -WXVF */
|
|
#define NV_095_BLEND_MASK_BIT_LSB 0x00000010 /* -W--V */
|
|
#define NV_095_BLEND_MASK_BIT_MSB 0x00000020 /* -W--V */
|
|
#define NV_095_BLEND_SHADEMODE 7:6 /* -WXVF */
|
|
#define NV_095_BLEND_SHADEMODE_FLAT 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_SHADEMODE_GOURAUD 0x00000002 /* -W--V */
|
|
#define NV_095_BLEND_SHADEMODE_PHONG 0x00000003 /* -W--V */
|
|
#define NV_095_BLEND_TEXTUREPERSPECTIVE 11:8 /* -WXVF */
|
|
#define NV_095_BLEND_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_BLEND_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_SPECULARENABLE 15:12 /* -WXVF */
|
|
#define NV_095_BLEND_SPECULARENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_BLEND_SPECULARENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_FOGENABLE 19:16 /* -WXVF */
|
|
#define NV_095_BLEND_FOGENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_BLEND_FOGENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_ALPHABLENDENABLE 23:20 /* -WXVF */
|
|
#define NV_095_BLEND_ALPHABLENDENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_BLEND_ALPHABLENDENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND 27:24 /* -WXVF */
|
|
#define NV_095_BLEND_SRCBLEND_ZERO 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_ONE 0x00000002 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_SRCCOLOR 0x00000003 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_SRCALPHA 0x00000005 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_INVSRCALPHA 0x00000006 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_DESTALPHA 0x00000007 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_INVDESTALPHA 0x00000008 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_DESTCOLOR 0x00000009 /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
|
|
#define NV_095_BLEND_SRCBLEND_SRCALPHASAT 0x0000000B /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND 31:28 /* -WXVF */
|
|
#define NV_095_BLEND_DESTBLEND_ZERO 0x00000001 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_ONE 0x00000002 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_SRCCOLOR 0x00000003 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_INVSRCCOLOR 0x00000004 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_SRCALPHA 0x00000005 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_INVSRCALPHA 0x00000006 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_DESTALPHA 0x00000007 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_INVDESTALPHA 0x00000008 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_DESTCOLOR 0x00000009 /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_INVDESTCOLOR 0x0000000A /* -W--V */
|
|
#define NV_095_BLEND_DESTBLEND_SRCALPHASAT 0x0000000B /* -W--V */
|
|
#define NV_095_CONTROL0 0x005a033C /* -W-4R */
|
|
#define NV_095_CONTROL0_ALPHAREF 7:0 /* -WXUF */
|
|
#define NV_095_CONTROL0_ALPHAFUNC 11:8 /* -WXVF */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHAFUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHATESTENABLE 12:12 /* -WXVF */
|
|
#define NV_095_CONTROL0_ALPHATESTENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHATESTENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ORIGIN 13:13 /* -WXVF */
|
|
#define NV_095_CONTROL0_ORIGIN_CENTER 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_ORIGIN_CORNER 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ZENABLE 15:14 /* -WXVF */
|
|
#define NV_095_CONTROL0_ZENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_ZENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC 19:16 /* -WXVF */
|
|
#define NV_095_CONTROL0_ZFUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_095_CONTROL0_ZFUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_095_CONTROL0_CULLMODE 21:20 /* -WXVF */
|
|
#define NV_095_CONTROL0_CULLMODE_NONE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_CULLMODE_CW 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL0_CULLMODE_CCW 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL0_DITHERENABLE 22:22 /* -WXVF */
|
|
#define NV_095_CONTROL0_DITHERENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_DITHERENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_Z_PERSPECTIVE_ENABLE 23:23 /* -WXVF */
|
|
#define NV_095_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ZWRITEENABLE 24:24 /* -WXVF */
|
|
#define NV_095_CONTROL0_ZWRITEENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_ZWRITEENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_STENCIL_WRITE_ENABLE 25:25 /* -WXVF */
|
|
#define NV_095_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHA_WRITE_ENABLE 26:26 /* -WXVF */
|
|
#define NV_095_CONTROL0_ALPHA_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_ALPHA_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_RED_WRITE_ENABLE 27:27 /* -WXVF */
|
|
#define NV_095_CONTROL0_RED_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_RED_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_GREEN_WRITE_ENABLE 28:28 /* -WXVF */
|
|
#define NV_095_CONTROL0_GREEN_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_GREEN_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_BLUE_WRITE_ENABLE 29:29 /* -WXVF */
|
|
#define NV_095_CONTROL0_BLUE_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL0_BLUE_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_Z_FORMAT 31:30 /* -WXVF */
|
|
#define NV_095_CONTROL0_Z_FORMAT_FIXED 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL0_Z_FORMAT_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL1 0x005a0340 /* -W-4R */
|
|
#define NV_095_CONTROL1_STENCIL_TEST_ENABLE 3:0 /* -WXVF */
|
|
#define NV_095_CONTROL1_STENCIL_TEST_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_TEST_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC 7:4 /* -WXVF */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_NEVER 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_LESS 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_EQUAL 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_LESSEQUAL 0x00000004 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_GREATER 0x00000005 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_NOTEQUAL 0x00000006 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_GREATEREQUAL 0x00000007 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_FUNC_ALWAYS 0x00000008 /* -W--V */
|
|
#define NV_095_CONTROL1_STENCIL_REF 15:8 /* -WXUF */
|
|
#define NV_095_CONTROL1_STENCIL_MASK_READ 23:16 /* -WXUF */
|
|
#define NV_095_CONTROL1_STENCIL_MASK_WRITE 31:24 /* -WXUF */
|
|
#define NV_095_CONTROL2 0x005a0344 /* -W-4R */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL 3:0 /* -WXVF */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_KEEP 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_ZERO 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_REPLACE 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_INCRSAT 0x00000004 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_DECRSAT 0x00000005 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_INVERT 0x00000006 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_INCR 0x00000007 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_FAIL_DECR 0x00000008 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL 7:4 /* -WXVF */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_KEEP 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_ZERO 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_REPLACE 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_INCRSAT 0x00000004 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_DECRSAT 0x00000005 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_INVERT 0x00000006 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_INCR 0x00000007 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZFAIL_DECR 0x00000008 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS 31:8 /* -WXVF */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_KEEP 0x00000001 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_ZERO 0x00000002 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_REPLACE 0x00000003 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_INCRSAT 0x00000004 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_DECRSAT 0x00000005 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_INVERT 0x00000006 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_INCR 0x00000007 /* -W--V */
|
|
#define NV_095_CONTROL2_STENCIL_OP_ZPASS_DECR 0x00000008 /* -W--V */
|
|
#define NV_095_FOGCOLOR 0x005a0348 /* -W-4R */
|
|
#define NV_095_FOGCOLOR_VALUE 31:0 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_SX(i) (0x005a0400+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_SX__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_SX_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_SY(i) (0x005a0404+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_SY__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_SY_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_SZ(i) (0x005a0408+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_SZ__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_SZ_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_RHW(i) (0x005a040c+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_RHW__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_RHW_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_COLOR(i) (0x005a0410+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_COLOR__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_COLOR_VALUE 31:0 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_COLOR_BLUE 7:0 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_COLOR_GREEN 15:8 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_COLOR_RED 23:16 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_COLOR_ALPHA 31:24 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_SPECULAR(i) (0x005a0414+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_SPECULAR__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_SPECULAR_VALUE 31:0 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_SPECULAR_BLUE 7:0 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_SPECULAR_GREEN 15:8 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_SPECULAR_RED 23:16 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_SPECULAR_FOG 31:24 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_TU0(i) (0x005a0418+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_TU0__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_TU0_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_TV0(i) (0x005a041c+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_TV0__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_TV0_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_TU1(i) (0x005a0420+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_TU1__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_TU1_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_TV1(i) (0x005a0424+(i)*40) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_TV1__SIZE_1 8 /* */
|
|
#define NV_095_TLMTVERTEX_TV1_VALUE 31:0 /* -WXFF */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE(i) (0x005a0540+(i)*4) /* -W-4A */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE__SIZE_1 48 /* */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE_I0 3:0 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE_I1 7:4 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE_I2 11:8 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE_I3 15:12 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE_I4 19:16 /* -WXUF */
|
|
#define NV_095_TLMTVERTEX_DRAWPRIMITIVE_I5 31:20 /* -WXUF */
|
|
/* usr_nv10_celsius_primitive.ref */
|
|
#define NV10_CELSIUS_PRIMITIVE 0x00000056 /* ----C */
|
|
#define NV10_CELSIUS_PRIMITIVE_HWCLASS 0x00000056 /* ----C */
|
|
#define NV_056 0x006c1fff:0x006c0000 /* -W--D */
|
|
#define NV_056_NV10_CELSIUS_PRIMITIVE 0x006c0000 /* -W-4R */
|
|
#define NV_056_NV10_CELSIUS_PRIMITIVE_HANDLE 31:0 /* -WXVF */
|
|
#define NV_056_NO_OPERATION 0x006c0100 /* -W-4R */
|
|
#define NV_056_NO_OPERATION_V 31:0 /* -WXUF */
|
|
#define NV_056_NOTIFY 0x006c0104 /* -W-4R */
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#define NV_056_NOTIFY_TYPE 31:0 /* -WXUF */
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#define NV_056_NOTIFY_TYPE_WRITE_ONLY 0x00000000 /* -W--V */
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#define NV_056_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
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#define NV_056_SET_WARNING_ENABLE 0x006c0108 /* -W-4R */
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#define NV_056_SET_WARNING_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_WARNING_ENABLE_V_STOP 0x00000000 /* -W--V */
|
|
#define NV_056_SET_WARNING_ENABLE_V_WRITE_ONLY 0x00000001 /* -W--V */
|
|
#define NV_056_SET_WARNING_ENABLE_V_WRITE_THEN_AWAKEN 0x00000002 /* -W--V */
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#define NV_056_GET_STATE 0x006c010c /* -W-4R */
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#define NV_056_GET_STATE_GETSTATE 31:0 /* -WXUF */
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|
#define NV_056_GET_STATE_GETSTATE_ALL_STATE 0x00000001 /* -W--V */
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#define NV_056_GET_STATE_GETSTATE_PUT_ALL_STATE 0x00000002 /* -W--V */
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#define NV_056_GET_STATE_GETSTATE_SNAPSHOT_PRIM_ASSM 0x00000006 /* -W--V */
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#define NV_056_GET_STATE_GETSTATE_RELOAD_PRIM_ASSM 0x00000007 /* -W--V */
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#define NV_056_WAIT_FOR_IDLE 0x006c0110 /* -W-4R */
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#define NV_056_WAIT_FOR_IDLE_V 31:0 /* -WXUF */
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#define NV_056_PM_TRIGGER 0x006c0140 /* -W-4R */
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#define NV_056_PM_TRIGGER_V 31:0 /* -WXUF */
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#define NV_056_PM_TRIGGER_V_NOP 0x00000000 /* -W--V */
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#define NV_056_PM_TRIGGER_V_TRIGGER 0x00000001 /* -W--V */
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#define NV_056_SET_CONTEXT_DMA_NOTIFIES 0x006c0180 /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_NOTIFIES_V 31:0 /* -WXUF */
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#define NV_056_SET_CONTEXT_DMA_A 0x006c0184 /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_A_V 31:0 /* -WXUF */
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#define NV_056_SET_CONTEXT_DMA_B 0x006c0188 /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_B_V 31:0 /* -WXUF */
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#define NV_056_SET_CONTEXT_DMA_VERTEX 0x006c018c /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_VERTEX_V 31:0 /* -WXUF */
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#define NV_056_SET_CONTEXT_DMA_STATE 0x006c0190 /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_STATE_V 31:0 /* -WXUF */
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#define NV_056_SET_CONTEXT_DMA_COLOR 0x006c0194 /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_COLOR_V 31:0 /* -WXUF */
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#define NV_056_SET_CONTEXT_DMA_ZETA 0x006c0198 /* -W-4R */
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#define NV_056_SET_CONTEXT_DMA_ZETA_V 31:0 /* -WXUF */
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#define NV_056_SET_SURFACE_CLIP_HORIZONTAL 0x006c0200 /* -W-4R */
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#define NV_056_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 /* -WXUF */
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#define NV_056_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 /* -WXUF */
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#define NV_056_SET_SURFACE_CLIP_VERTICAL 0x006c0204 /* -W-4R */
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#define NV_056_SET_SURFACE_CLIP_VERTICAL_Y 15:0 /* -WXUF */
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#define NV_056_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 /* -WXUF */
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#define NV_056_SET_SURFACE_FORMAT 0x006c0208 /* -W-4R */
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#define NV_056_SET_SURFACE_FORMAT_COLOR 7:0 /* -WXUF */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x00000001 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x00000002 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_R5G6B5 0x00000003 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x00000004 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x00000005 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000006 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000007 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_A8R8G8B8 0x00000008 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_B8 0x00000009 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_COLOR_LE_G8B8 0x0000000A /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_TYPE 15:8 /* -WXUF */
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#define NV_056_SET_SURFACE_FORMAT_TYPE_PITCH 0x00000001 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_TYPE_SWIZZLE 0x00000002 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH 23:16 /* -WXUF */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_1 0x00000000 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_2 0x00000001 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_4 0x00000002 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_8 0x00000003 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_16 0x00000004 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_32 0x00000005 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_WIDTH_64 0x00000006 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_128 0x00000007 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_256 0x00000008 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_WIDTH_512 0x00000009 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_WIDTH_1024 0x0000000A /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_WIDTH_2048 0x0000000B /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT 31:24 /* -WXUF */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT_1 0x00000000 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_HEIGHT_2 0x00000001 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_HEIGHT_4 0x00000002 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_HEIGHT_8 0x00000003 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_HEIGHT_16 0x00000004 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_HEIGHT_32 0x00000005 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT_64 0x00000006 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT_128 0x00000007 /* -W--V */
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#define NV_056_SET_SURFACE_FORMAT_HEIGHT_256 0x00000008 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT_512 0x00000009 /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT_1024 0x0000000A /* -W--V */
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|
#define NV_056_SET_SURFACE_FORMAT_HEIGHT_2048 0x0000000B /* -W--V */
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#define NV_056_SET_SURFACE_PITCH 0x006c020c /* -W-4R */
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#define NV_056_SET_SURFACE_PITCH_COLOR 15:0 /* -WXUF */
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#define NV_056_SET_SURFACE_PITCH_ZETA 31:16 /* -WXUF */
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#define NV_056_SET_SURFACE_COLOR_OFFSET 0x006c0210 /* -W-4R */
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#define NV_056_SET_SURFACE_COLOR_OFFSET_V 31:0 /* -WXUF */
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#define NV_056_SET_SURFACE_ZETA_OFFSET 0x006c0214 /* -W-4R */
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#define NV_056_SET_SURFACE_ZETA_OFFSET_V 31:0 /* -WXUF */
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#define NV_056_SET_TEXTURE_OFFSET(i) (0x006c0218+(i)*4) /* -W-4A */
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#define NV_056_SET_TEXTURE_OFFSET__SIZE_1 2 /* */
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#define NV_056_SET_TEXTURE_OFFSET_V 31:0 /* -WXUF */
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#define NV_056_SET_TEXTURE_FORMAT(i) (0x006c0220+(i)*4) /* -W-4A */
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#define NV_056_SET_TEXTURE_FORMAT__SIZE_1 2 /* */
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#define NV_056_SET_TEXTURE_FORMAT_CONTEXT_DMA 1:0 /* -WXUF */
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#define NV_056_SET_TEXTURE_FORMAT_CONTEXT_DMA_A 0x00000001 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_CONTEXT_DMA_B 0x00000002 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE 2:2 /* -WXUF */
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#define NV_056_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_ORIGIN_ZOH 4:3 /* -WXUF */
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#define NV_056_SET_TEXTURE_FORMAT_ORIGIN_ZOH_CENTER 0x00000001 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_ORIGIN_ZOH_CORNER 0x00000002 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_ORIGIN_FOH 6:5 /* -WXUF */
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#define NV_056_SET_TEXTURE_FORMAT_ORIGIN_FOH_CENTER 0x00000001 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_ORIGIN_FOH_CORNER 0x00000002 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR 11:7 /* -WXUF */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_Y8 0x00000000 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_AY8 0x00000001 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_A1R5G5B5 0x00000002 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_X1R5G5B5 0x00000003 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_A4R4G4B4 0x00000004 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_R5G6B5 0x00000005 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_A8R8G8B8 0x00000006 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_X8R8G8B8 0x00000007 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_I8_A1R5G5B5 0x00000008 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_I8_R5G6B5 0x00000009 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_I8_A4R4G4B4 0x0000000A /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_I8_A8R8G8B8 0x0000000B /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_DXT1_A1R5G5B5 0x0000000C /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_DXT23_A8R8G8B8 0x0000000E /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_DXT45_A8R8G8B8 0x0000000F /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_A1R5G5B5 0x00000010 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_R5G6B5 0x00000011 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_A8R8G8B8 0x00000012 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_Y8 0x00000013 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_SY8 0x00000014 /* -W--V */
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|
#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_X7SY9 0x00000015 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_R8B8 0x00000016 /* -W--V */
|
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_G8B8 0x00000017 /* -W--V */
|
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#define NV_056_SET_TEXTURE_FORMAT_COLOR_LE_IMAGE_SG8SB8 0x00000018 /* -W--V */
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#define NV_056_SET_TEXTURE_FORMAT_MIPMAP_LEVELS 15:12 /* -WXUF */
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|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U 19:16 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_1 0x00000000 /* -W--V */
|
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#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_2 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_4 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_8 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_16 0x00000004 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_32 0x00000005 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_64 0x00000006 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_128 0x00000007 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_256 0x00000008 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_512 0x00000009 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_1024 0x0000000A /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_U_2048 0x0000000B /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V 23:20 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_1 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_2 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_4 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_8 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_16 0x00000004 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_32 0x00000005 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_64 0x00000006 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_128 0x00000007 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_256 0x00000008 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_512 0x00000009 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_1024 0x0000000A /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_BASE_SIZE_V_2048 0x0000000B /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSU 26:24 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSU_WRAP 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSU_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSU_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_WRAPU 27:27 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FORMAT_WRAPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_WRAPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSV 30:28 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSV_WRAP 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSV_MIRROR 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_TEXTUREADDRESSV_CLAMP 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_WRAPV 31:31 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FORMAT_WRAPV_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FORMAT_WRAPV_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0(i) (0x006c0228+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_CONTROL0__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_ENABLE 31:30 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_MIN_LOD_CLAMP 29:18 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_MAX_LOD_CLAMP 17:6 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO 5:4 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO_1 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_IMAGE_FIELD_ENABLE 3:3 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_IMAGE_FIELD_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_IMAGE_FIELD_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_ALPHA_KILL_ENABLE 2:2 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_ALPHA_KILL_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_ALPHA_KILL_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION 1:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_ALPHA 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_RGBA 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_KILL 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_CONTROL1(i) (0x006c0230+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_CONTROL1__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXTURE_CONTROL1_IMAGE_PITCH 31:16 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL2(i) (0x006c0238+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_CONTROL2__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXTURE_CONTROL2_PERTURB_DU 11:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL2_PERTURB_DV 23:12 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_CONTROL2_IMAGE_LODF 31:24 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_IMAGE_RECT(i) (0x006c0240+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_IMAGE_RECT__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXTURE_IMAGE_RECT_WIDTH 31:16 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_IMAGE_RECT_HEIGHT 15:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FILTER(i) (0x006c0248+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_FILTER__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXTURE_FILTER_MIPMAPLODBIAS 12:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN 27:24 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN_MIPNEAREST 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN_MIPLINEAR 0x00000004 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN_LINEARMIPNEAREST 0x00000005 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMIN_LINEARMIPLINEAR 0x00000006 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMAG 31:28 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMAG_NEAREST 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_FILTER_TEXTUREMAG_LINEAR 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_PALETTE(i) (0x006c0250+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_PALETTE__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXTURE_PALETTE_CONTEXT_DMA 5:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_PALETTE_CONTEXT_DMA_A 0x00000000 /* -W--V */
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#define NV_056_SET_TEXTURE_PALETTE_CONTEXT_DMA_B 0x00000001 /* -W--V */
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#define NV_056_SET_TEXTURE_PALETTE_PALETTE_OFFSET 31:6 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW(i) (0x006c0260+(i)*4) /* -W-4A */
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#define NV_056_SET_COMBINER_ALPHA_ICW__SIZE_1 2 /* */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP 31:29 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_ALPHA 28:28 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE 27:24 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP 23:21 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_ALPHA 20:20 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE 19:16 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP 15:13 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_ALPHA 12:12 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP 7:5 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_ALPHA 4:4 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE 3:0 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW(i) (0x006c0268+(i)*4) /* -W-4A */
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#define NV_056_SET_COMBINER_COLOR_ICW__SIZE_1 2 /* */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP 31:29 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_ALPHA 28:28 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE 27:24 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP 23:21 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_ALPHA 20:20 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE 19:16 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP 15:13 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_ALPHA 12:12 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP 7:5 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_ALPHA 4:4 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE 3:0 /* -WXUF */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINE_FACTOR(i) (0x006c0270+(i)*4) /* -W-4A */
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#define NV_056_SET_COMBINE_FACTOR__SIZE_1 2 /* */
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#define NV_056_SET_COMBINE_FACTOR_BLUE 7:0 /* -WXUF */
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#define NV_056_SET_COMBINE_FACTOR_GREEN 15:8 /* -WXUF */
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#define NV_056_SET_COMBINE_FACTOR_RED 23:16 /* -WXUF */
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#define NV_056_SET_COMBINE_FACTOR_ALPHA 31:24 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_OCW(i) (0x006c0278+(i)*4) /* -W-4A */
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#define NV_056_SET_COMBINER_ALPHA_OCW__SIZE_1 2 /* */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION 31:15 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION_NOSHIFT 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION_NOSHIFT_BIAS 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTLEFTBY1 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTLEFTBY1_BIAS 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTLEFTBY2 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTRIGHTBY1 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_MUX_ENABLE 14:14 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_OCW_MUX_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_MUX_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST 7:4 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_AB_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST 3:0 /* -WXUF */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_ALPHA_OCW_CD_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW 0x006c0280 /* -W-4R */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION 31:15 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION_NOSHIFT 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION_NOSHIFT_BIAS 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION_SHIFTLEFTBY1 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION_SHIFTLEFTBY1_BIAS 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION_SHIFTLEFTBY2 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_OPERATION_SHIFTRIGHTBY1 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_MUX_ENABLE 14:14 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_MUX_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_MUX_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DOT_ENABLE 13:13 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DOT_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DOT_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DOT_ENABLE 12:12 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DOT_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DOT_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_SUM_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST 7:4 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_AB_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST 3:0 /* -WXUF */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER0_COLOR_OCW_CD_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW 0x006c0284 /* -W-4R */
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#define NV_056_SET_COMBINER1_COLOR_OCW_ITERATION_COUNT 31:28 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_ITERATION_COUNT_ONE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_ITERATION_COUNT_TWO 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_MUX_SELECT 27:27 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_MUX_SELECT_LSB 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_MUX_SELECT_MSB 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION 26:15 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION_NOSHIFT 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION_NOSHIFT_BIAS 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION_SHIFTLEFTBY1 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION_SHIFTLEFTBY1_BIAS 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION_SHIFTLEFTBY2 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_OPERATION_SHIFTRIGHTBY1 0x00000006 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_MUX_ENABLE 14:14 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_MUX_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_MUX_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DOT_ENABLE 13:13 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DOT_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DOT_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DOT_ENABLE 12:12 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DOT_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DOT_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_SUM_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST 7:4 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_AB_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST 3:0 /* -WXUF */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER1_COLOR_OCW_CD_DST_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0 0x006c0288 /* -W-4R */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE 31:29 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA 28:28 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE 27:24 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE 23:21 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA 20:20 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE 19:16 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE 15:13 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA 12:12 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE 7:5 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA 4:4 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE 3:0 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1 0x006c028c /* -W-4R */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE 31:29 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA 28:28 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE 27:24 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE 23:21 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA 20:20 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE 19:16 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE 15:13 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA 12:12 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE 11:8 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP 7:7 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5 6:6 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12 5:0 /* -WXUF */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12_TRUE 0x00000020 /* -W--V */
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#define NV_056_SET_CONTROL0 0x006c0290 /* -W-4R */
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#define NV_056_SET_CONTROL0_PREMULTIPLIEDALPHA 31:24 /* -WXUF */
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#define NV_056_SET_CONTROL0_PREMULTIPLIEDALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_CONTROL0_PREMULTIPLIEDALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_CONTROL0_TEXTUREPERSPECTIVE 23:20 /* -WXUF */
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#define NV_056_SET_CONTROL0_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_CONTROL0_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_CONTROL0_Z_PERSPECTIVE_ENABLE 19:16 /* -WXUF */
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#define NV_056_SET_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_CONTROL0_Z_FORMAT 15:12 /* -WXUF */
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#define NV_056_SET_CONTROL0_Z_FORMAT_FIXED 0x00000000 /* -W--V */
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#define NV_056_SET_CONTROL0_Z_FORMAT_FLOAT 0x00000001 /* -W--V */
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#define NV_056_SET_CONTROL0_WBUFFER_SELECT 11:8 /* -WXUF */
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#define NV_056_SET_CONTROL0_WBUFFER_SELECT_0 0x00000000 /* -W--V */
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#define NV_056_SET_CONTROL0_WBUFFER_SELECT_1 0x00000001 /* -W--V */
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#define NV_056_SET_CONTROL0_STENCIL_WRITE_ENABLE 7:0 /* -WXUF */
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#define NV_056_SET_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL 0x006c0294 /* -W-4R */
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#define NV_056_SET_LIGHT_CONTROL_LOCALEYE 31:16 /* -WXUF */
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#define NV_056_SET_LIGHT_CONTROL_LOCALEYE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_LOCALEYE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_ATTENUATION_MODE 15:2 /* -WXUF */
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#define NV_056_SET_LIGHT_CONTROL_ATTENUATION_MODE_INVERT 0x00000000 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_ATTENUATION_MODE_NOT_INVERT 0x00000001 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_SEPARATE_SPECULAR_EN 1:1 /* -WXUF */
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#define NV_056_SET_LIGHT_CONTROL_SEPARATE_SPECULAR_EN_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_SEPARATE_SPECULAR_EN_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_SECONDARY_COLOR_EN 0:0 /* -WXUF */
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#define NV_056_SET_LIGHT_CONTROL_SECONDARY_COLOR_EN_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_LIGHT_CONTROL_SECONDARY_COLOR_EN_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL 0x006c0298 /* -W-4R */
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#define NV_056_SET_COLOR_MATERIAL_V 31:0 /* -WXUF */
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#define NV_056_SET_COLOR_MATERIAL_V_DISABLED 0x00000000 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION 0x00000001 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_AMBIENT 0x00000002 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_AMBIENT 0x00000003 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_DIFFUSE 0x00000004 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_DIFFUSE 0x00000005 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_AMBIENT_DIFFUSE 0x00000006 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_AMBIENT_DIFFUSE 0x00000007 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_SPECULAR 0x00000008 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_SPECULAR 0x00000009 /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_AMBIENT_SPECULAR 0x0000000A /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_AMBIENT_SPECULAR 0x0000000B /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_DIFFUSE_SPECULAR 0x0000000C /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_DIFFUSE_SPECULAR 0x0000000D /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_AMBIENT_DIFFUSE_SPECULAR 0x0000000E /* -W--V */
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#define NV_056_SET_COLOR_MATERIAL_V_EMISSION_AMBIENT_DIFFUSE_SPECULAR 0x0000000F /* -W--V */
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#define NV_056_SET_FOG_MODE 0x006c029c /* -W-4R */
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#define NV_056_SET_FOG_MODE_FOG_MODE 31:0 /* -WXUF */
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#define NV_056_SET_FOG_MODE_FOG_MODE_LINEAR 0x00002601 /* -W--V */
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#define NV_056_SET_FOG_MODE_FOG_MODE_EXP 0x00000800 /* -W--V */
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#define NV_056_SET_FOG_MODE_FOG_MODE_EXP2 0x00000801 /* -W--V */
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#define NV_056_SET_FOG_MODE_FOG_MODE_EXP_ABS 0x00000802 /* -W--V */
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#define NV_056_SET_FOG_MODE_FOG_MODE_EXP2_ABS 0x00000803 /* -W--V */
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#define NV_056_SET_FOG_GEN_MODE 0x006c02a0 /* -W-4R */
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#define NV_056_SET_FOG_GEN_MODE_FOG_GEN_MODE 31:0 /* -WXUF */
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#define NV_056_SET_FOG_GEN_MODE_FOG_GEN_MODE_USE_INPUT 0x00000000 /* -W--V */
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#define NV_056_SET_FOG_GEN_MODE_FOG_GEN_MODE_RADIAL 0x00000001 /* -W--V */
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#define NV_056_SET_FOG_GEN_MODE_FOG_GEN_MODE_PLANAR 0x00000002 /* -W--V */
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#define NV_056_SET_FOG_GEN_MODE_FOG_GEN_MODE_ABS_PLANAR 0x00000003 /* -W--V */
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#define NV_056_SET_FOG_ENABLE 0x006c02a4 /* -W-4R */
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#define NV_056_SET_FOG_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_FOG_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_FOG_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_FOG_COLOR 0x006c02a8 /* -W-4R */
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#define NV_056_SET_FOG_COLOR_FOG_COLOR_RED 7:0 /* -WXUF */
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#define NV_056_SET_FOG_COLOR_FOG_COLOR_GREEN 15:8 /* -WXUF */
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#define NV_056_SET_FOG_COLOR_FOG_COLOR_BLUE 23:16 /* -WXUF */
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#define NV_056_SET_FOG_COLOR_FOG_COLOR_ALPHA 31:24 /* -WXUF */
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#define NV_056_SET_COLOR_KEY_COLOR(i) (0x006c02ac+(i)*4) /* -W-4A */
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#define NV_056_SET_COLOR_KEY_COLOR__SIZE_1 2 /* */
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#define NV_056_SET_COLOR_KEY_COLOR_V 31:0 /* -WXUF */
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#define NV_056_SET_WINDOW_CLIP_TYPE 0x006c02b4 /* -W-4R */
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#define NV_056_SET_WINDOW_CLIP_TYPE_V 31:0 /* -WXUF */
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#define NV_056_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 /* -W--V */
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#define NV_056_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 /* -W--V */
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#define NV_056_SET_WINDOW_CLIP_HORIZONTAL(i) (0x006c02c0+(i)*4) /* -W-4A */
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#define NV_056_SET_WINDOW_CLIP_HORIZONTAL__SIZE_1 8 /* */
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#define NV_056_SET_WINDOW_CLIP_HORIZONTAL_XMIN 11:0 /* -WXUF */
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#define NV_056_SET_WINDOW_CLIP_HORIZONTAL_XMAX 27:16 /* -WXUF */
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#define NV_056_SET_WINDOW_CLIP_VERTICAL(i) (0x006c02e0+(i)*4) /* -W-4A */
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#define NV_056_SET_WINDOW_CLIP_VERTICAL__SIZE_1 8 /* */
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#define NV_056_SET_WINDOW_CLIP_VERTICAL_YMIN 11:0 /* -WXUF */
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#define NV_056_SET_WINDOW_CLIP_VERTICAL_YMAX 27:16 /* -WXUF */
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#define NV_056_SET_ALPHA_TEST_ENABLE 0x006c0300 /* -W-4R */
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#define NV_056_SET_ALPHA_TEST_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_ALPHA_TEST_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_ALPHA_TEST_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_BLEND_ENABLE 0x006c0304 /* -W-4R */
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#define NV_056_SET_BLEND_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_BLEND_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_BLEND_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_CULL_FACE_ENABLE 0x006c0308 /* -W-4R */
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#define NV_056_SET_CULL_FACE_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_CULL_FACE_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_CULL_FACE_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_DEPTH_TEST_ENABLE 0x006c030c /* -W-4R */
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#define NV_056_SET_DEPTH_TEST_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_DEPTH_TEST_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_DEPTH_TEST_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_DITHER_ENABLE 0x006c0310 /* -W-4R */
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#define NV_056_SET_DITHER_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_DITHER_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_DITHER_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_LIGHTING_ENABLE 0x006c0314 /* -W-4R */
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#define NV_056_SET_LIGHTING_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_LIGHTING_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_LIGHTING_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_POINT_PARAMS_ENABLE 0x006c0318 /* -W-4R */
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#define NV_056_SET_POINT_PARAMS_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_POINT_PARAMS_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_POINT_PARAMS_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_POINT_SMOOTH_ENABLE 0x006c031c /* -W-4R */
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#define NV_056_SET_POINT_SMOOTH_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_POINT_SMOOTH_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_POINT_SMOOTH_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_LINE_SMOOTH_ENABLE 0x006c0320 /* -W-4R */
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#define NV_056_SET_LINE_SMOOTH_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_LINE_SMOOTH_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_LINE_SMOOTH_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_POLY_SMOOTH_ENABLE 0x006c0324 /* -W-4R */
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#define NV_056_SET_POLY_SMOOTH_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_POLY_SMOOTH_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_POLY_SMOOTH_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_SKIN_ENABLE 0x006c0328 /* -W-4R */
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#define NV_056_SET_SKIN_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_SKIN_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_SKIN_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_STENCIL_TEST_ENABLE 0x006c032c /* -W-4R */
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#define NV_056_SET_STENCIL_TEST_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_TEST_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_STENCIL_TEST_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_POLY_OFFSET_POINT_ENABLE 0x006c0330 /* -W-4R */
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#define NV_056_SET_POLY_OFFSET_POINT_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_POLY_OFFSET_POINT_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_POLY_OFFSET_POINT_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_POLY_OFFSET_LINE_ENABLE 0x006c0334 /* -W-4R */
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#define NV_056_SET_POLY_OFFSET_LINE_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_POLY_OFFSET_LINE_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_POLY_OFFSET_LINE_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_POLY_OFFSET_FILL_ENABLE 0x006c0338 /* -W-4R */
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#define NV_056_SET_POLY_OFFSET_FILL_ENABLE_V 31:0 /* -WXUF */
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#define NV_056_SET_POLY_OFFSET_FILL_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_POLY_OFFSET_FILL_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC 0x006c033c /* -W-4R */
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#define NV_056_SET_ALPHA_FUNC_V 31:0 /* -WXUF */
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#define NV_056_SET_ALPHA_FUNC_V_NEVER 0x00000200 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_LESS 0x00000201 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_EQUAL 0x00000202 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_LEQUAL 0x00000203 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_GREATER 0x00000204 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_NOTEQUAL 0x00000205 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_GEQUAL 0x00000206 /* -W--V */
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#define NV_056_SET_ALPHA_FUNC_V_ALWAYS 0x00000207 /* -W--V */
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#define NV_056_SET_ALPHA_REF 0x006c0340 /* -W-4R */
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#define NV_056_SET_ALPHA_REF_V 31:0 /* -WXUF */
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#define NV_056_SET_BLEND_FUNC_SFACTOR 0x006c0344 /* -W-4R */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V 31:0 /* -WXUF */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ZERO 0x00000000 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE 0x00000001 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_SRC_COLOR 0x00000300 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_COLOR 0x00000301 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA 0x00000302 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_ALPHA 0x00000303 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_DST_ALPHA 0x00000304 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_ALPHA 0x00000305 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_DST_COLOR 0x00000306 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_COLOR 0x00000307 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA_SATURATE 0x00000308 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_COLOR 0x00008001 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x00008002 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_ALPHA 0x00008003 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x00008004 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR 0x006c0348 /* -W-4R */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V 31:0 /* -WXUF */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ZERO 0x00000000 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE 0x00000001 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_SRC_COLOR 0x00000300 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_COLOR 0x00000301 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA 0x00000302 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_ALPHA 0x00000303 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_DST_ALPHA 0x00000304 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_ALPHA 0x00000305 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_DST_COLOR 0x00000306 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_COLOR 0x00000307 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA_SATURATE 0x00000308 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_COLOR 0x00008001 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x00008002 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_ALPHA 0x00008003 /* -W--V */
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#define NV_056_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x00008004 /* -W--V */
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#define NV_056_SET_BLEND_COLOR 0x006c034c /* -W-4R */
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#define NV_056_SET_BLEND_COLOR_V 31:0 /* -WXUF */
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#define NV_056_SET_BLEND_EQUATION 0x006c0350 /* -W-4R */
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#define NV_056_SET_BLEND_EQUATION_V 31:0 /* -WXUF */
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#define NV_056_SET_BLEND_EQUATION_V_FUNC_SUBTRACT 0x0000800A /* -W--V */
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#define NV_056_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT 0x0000800B /* -W--V */
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#define NV_056_SET_BLEND_EQUATION_V_FUNC_ADD 0x00008006 /* -W--V */
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#define NV_056_SET_BLEND_EQUATION_V_MIN 0x00008007 /* -W--V */
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#define NV_056_SET_BLEND_EQUATION_V_MAX 0x00008008 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC 0x006c0354 /* -W-4R */
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#define NV_056_SET_DEPTH_FUNC_V 31:0 /* -WXUF */
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#define NV_056_SET_DEPTH_FUNC_V_NEVER 0x00000200 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_LESS 0x00000201 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_EQUAL 0x00000202 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_LEQUAL 0x00000203 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_GREATER 0x00000204 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_NOTEQUAL 0x00000205 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_GEQUAL 0x00000206 /* -W--V */
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#define NV_056_SET_DEPTH_FUNC_V_ALWAYS 0x00000207 /* -W--V */
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#define NV_056_SET_COLOR_MASK 0x006c0358 /* -W-4R */
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#define NV_056_SET_COLOR_MASK_ALPHA_WRITE_ENABLE 31:24 /* -WXUF */
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#define NV_056_SET_COLOR_MASK_ALPHA_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COLOR_MASK_ALPHA_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COLOR_MASK_RED_WRITE_ENABLE 23:16 /* -WXUF */
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#define NV_056_SET_COLOR_MASK_RED_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COLOR_MASK_RED_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COLOR_MASK_GREEN_WRITE_ENABLE 15:8 /* -WXUF */
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#define NV_056_SET_COLOR_MASK_GREEN_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COLOR_MASK_GREEN_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_COLOR_MASK_BLUE_WRITE_ENABLE 7:0 /* -WXUF */
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#define NV_056_SET_COLOR_MASK_BLUE_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_COLOR_MASK_BLUE_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_DEPTH_MASK 0x006c035c /* -W-4R */
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#define NV_056_SET_DEPTH_MASK_V 31:0 /* -WXUF */
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#define NV_056_SET_DEPTH_MASK_V_FALSE 0x00000000 /* -W--V */
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#define NV_056_SET_DEPTH_MASK_V_TRUE 0x00000001 /* -W--V */
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#define NV_056_SET_STENCIL_MASK 0x006c0360 /* -W-4R */
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#define NV_056_SET_STENCIL_MASK_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_FUNC 0x006c0364 /* -W-4R */
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#define NV_056_SET_STENCIL_FUNC_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_FUNC_V_NEVER 0x00000200 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_LESS 0x00000201 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_EQUAL 0x00000202 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_LEQUAL 0x00000203 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_GREATER 0x00000204 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_NOTEQUAL 0x00000205 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_GEQUAL 0x00000206 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_V_ALWAYS 0x00000207 /* -W--V */
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#define NV_056_SET_STENCIL_FUNC_REF 0x006c0368 /* -W-4R */
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#define NV_056_SET_STENCIL_FUNC_REF_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_FUNC_MASK 0x006c036c /* -W-4R */
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#define NV_056_SET_STENCIL_FUNC_MASK_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_OP_FAIL 0x006c0370 /* -W-4R */
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#define NV_056_SET_STENCIL_OP_FAIL_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_OP_FAIL_V_KEEP 0x00001E00 /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_ZERO 0x00000000 /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_REPLACE 0x00001E01 /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_INCRSAT 0x00001E02 /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_DECRSAT 0x00001E03 /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_INVERT 0x0000150A /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_INCR 0x00008507 /* -W--V */
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#define NV_056_SET_STENCIL_OP_FAIL_V_DECR 0x00008508 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL 0x006c0374 /* -W-4R */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_KEEP 0x00001E00 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_ZERO 0x00000000 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_REPLACE 0x00001E01 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_INCRSAT 0x00001E02 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_DECRSAT 0x00001E03 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_INVERT 0x0000150A /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_INCR 0x00008507 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZFAIL_V_DECR 0x00008508 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS 0x006c0378 /* -W-4R */
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#define NV_056_SET_STENCIL_OP_ZPASS_V 31:0 /* -WXUF */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_KEEP 0x00001E00 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_ZERO 0x00000000 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_REPLACE 0x00001E01 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_INCRSAT 0x00001E02 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_DECRSAT 0x00001E03 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_INVERT 0x0000150A /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_INCR 0x00008507 /* -W--V */
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#define NV_056_SET_STENCIL_OP_ZPASS_V_DECR 0x00008508 /* -W--V */
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#define NV_056_SET_SHADE_MODE 0x006c037c /* -W-4R */
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#define NV_056_SET_SHADE_MODE_V 31:0 /* -WXUF */
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#define NV_056_SET_SHADE_MODE_V_FLAT 0x00001D00 /* -W--V */
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#define NV_056_SET_SHADE_MODE_V_SMOOTH 0x00001D01 /* -W--V */
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#define NV_056_SET_LINE_WIDTH 0x006c0380 /* -W-4R */
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#define NV_056_SET_LINE_WIDTH_V 31:0 /* -WXUF */
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#define NV_056_SET_POLYGON_OFFSET_SCALE_FACTOR 0x006c0384 /* -W-4R */
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#define NV_056_SET_POLYGON_OFFSET_SCALE_FACTOR_V 31:0 /* -WXUF */
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#define NV_056_SET_POLYGON_OFFSET_BIAS 0x006c0388 /* -W-4R */
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#define NV_056_SET_POLYGON_OFFSET_BIAS_V 31:0 /* -WXUF */
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#define NV_056_SET_FRONT_POLYGON_MODE 0x006c038c /* -W-4R */
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#define NV_056_SET_FRONT_POLYGON_MODE_V 31:0 /* -WXUF */
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#define NV_056_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 /* -W--V */
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#define NV_056_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 /* -W--V */
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#define NV_056_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 /* -W--V */
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#define NV_056_SET_BACK_POLYGON_MODE 0x006c0390 /* -W-4R */
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#define NV_056_SET_BACK_POLYGON_MODE_V 31:0 /* -WXUF */
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#define NV_056_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 /* -W--V */
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#define NV_056_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 /* -W--V */
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#define NV_056_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 /* -W--V */
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#define NV_056_SET_CLIP_MIN 0x006c0394 /* -W-4R */
|
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#define NV_056_SET_CLIP_MIN_V 31:0 /* -WXUF */
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#define NV_056_SET_CLIP_MAX 0x006c0398 /* -W-4R */
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#define NV_056_SET_CLIP_MAX_V 31:0 /* -WXUF */
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#define NV_056_SET_CULL_FACE 0x006c039c /* -W-4R */
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#define NV_056_SET_CULL_FACE_V 31:0 /* -WXUF */
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#define NV_056_SET_CULL_FACE_V_FRONT 0x00000404 /* -W--V */
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#define NV_056_SET_CULL_FACE_V_BACK 0x00000405 /* -W--V */
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#define NV_056_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 /* -W--V */
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#define NV_056_SET_FRONT_FACE 0x006c03a0 /* -W-4R */
|
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#define NV_056_SET_FRONT_FACE_V 31:0 /* -WXUF */
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#define NV_056_SET_FRONT_FACE_V_CW 0x00000900 /* -W--V */
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#define NV_056_SET_FRONT_FACE_V_CCW 0x00000901 /* -W--V */
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#define NV_056_SET_NORMALIZATION_ENABLE 0x006c03a4 /* -W-4R */
|
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#define NV_056_SET_NORMALIZATION_ENABLE_V 31:0 /* -WXUF */
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|
#define NV_056_SET_NORMALIZATION_ENABLE_V_FALSE 0x00000000 /* -W--V */
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|
#define NV_056_SET_NORMALIZATION_ENABLE_V_TRUE 0x00000001 /* -W--V */
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|
#define NV_056_SET_MATERIAL_EMISSION(i) (0x006c03a8+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_MATERIAL_EMISSION__SIZE_1 3 /* */
|
|
#define NV_056_SET_MATERIAL_EMISSION_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_MATERIAL_EMISSION_SW(i) (0x006c1628+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_MATERIAL_EMISSION_SW__SIZE_1 3 /* */
|
|
#define NV_056_SET_MATERIAL_EMISSION_SW_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_MATERIAL_ALPHA 0x006c03b4 /* -W-4R */
|
|
#define NV_056_SET_MATERIAL_ALPHA_V 31:0 /* -WXUF */
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|
#define NV_056_SET_SPECULAR_ENABLE 0x006c03b8 /* -W-4R */
|
|
#define NV_056_SET_SPECULAR_ENABLE_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_ENABLE_V_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ENABLE_V_TRUE 0x00000001 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK 0x006c03bc /* -W-4R */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT0 1:0 /* -WXUF */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT0_OFF 0x00000000 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT0_INFINITE 0x00000001 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT0_LOCAL 0x00000002 /* -W--V */
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#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT0_SPOT 0x00000003 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT1 3:2 /* -WXUF */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT1_OFF 0x00000000 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT1_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT1_LOCAL 0x00000002 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT1_SPOT 0x00000003 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT2 5:4 /* -WXUF */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT2_OFF 0x00000000 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT2_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT2_LOCAL 0x00000002 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT2_SPOT 0x00000003 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT3 7:6 /* -WXUF */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT3_OFF 0x00000000 /* -W--V */
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|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT3_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT3_LOCAL 0x00000002 /* -W--V */
|
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#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT3_SPOT 0x00000003 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT4 9:8 /* -WXUF */
|
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#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT4_OFF 0x00000000 /* -W--V */
|
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#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT4_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT4_LOCAL 0x00000002 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT4_SPOT 0x00000003 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT5 11:10 /* -WXUF */
|
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#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT5_OFF 0x00000000 /* -W--V */
|
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#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT5_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT5_LOCAL 0x00000002 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT5_SPOT 0x00000003 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT6 13:12 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT6_OFF 0x00000000 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT6_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT6_LOCAL 0x00000002 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT6_SPOT 0x00000003 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT7 15:14 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT7_OFF 0x00000000 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT7_INFINITE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT7_LOCAL 0x00000002 /* -W--V */
|
|
#define NV_056_SET_LIGHT_ENABLE_MASK_LIGHT7_SPOT 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_S(i) (0x006c03c0+(i)*16) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_S__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXGEN_S_V 31:0 /* -WXUF */
|
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#define NV_056_SET_TEXGEN_S_V_DISABLE 0x00000000 /* -W--V */
|
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#define NV_056_SET_TEXGEN_S_V_NORMAL_MAP 0x00008511 /* -W--V */
|
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#define NV_056_SET_TEXGEN_S_V_REFLECTION_MAP 0x00008512 /* -W--V */
|
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#define NV_056_SET_TEXGEN_S_V_EYE_LINEAR 0x00002400 /* -W--V */
|
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#define NV_056_SET_TEXGEN_S_V_OBJECT_LINEAR 0x00002401 /* -W--V */
|
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#define NV_056_SET_TEXGEN_S_V_SPHERE_MAP 0x00002402 /* -W--V */
|
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#define NV_056_SET_TEXGEN_S_V_EMBOSS 0x0000855F /* -W--V */
|
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#define NV_056_SET_TEXGEN_T(i) (0x006c03c4+(i)*16) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_T__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXGEN_T_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_T_V_DISABLE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_T_V_NORMAL_MAP 0x00008511 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_T_V_REFLECTION_MAP 0x00008512 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_T_V_EYE_LINEAR 0x00002400 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_T_V_OBJECT_LINEAR 0x00002401 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_T_V_SPHERE_MAP 0x00002402 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_T_V_EMBOSS 0x0000855F /* -W--V */
|
|
#define NV_056_SET_TEXGEN_R(i) (0x006c03c8+(i)*16) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_R__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXGEN_R_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_R_V_DISABLE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_R_V_NORMAL_MAP 0x00008511 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_R_V_REFLECTION_MAP 0x00008512 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_R_V_EYE_LINEAR 0x00002400 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_R_V_OBJECT_LINEAR 0x00002401 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_R_V_EMBOSS 0x0000855F /* -W--V */
|
|
#define NV_056_SET_TEXGEN_Q(i) (0x006c03cc+(i)*16) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_Q__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXGEN_Q_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_Q_V_DISABLE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_Q_V_EYE_LINEAR 0x00002400 /* -W--V */
|
|
#define NV_056_SET_TEXGEN_Q_V_OBJECT_LINEAR 0x00002401 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_MATRIX0_ENABLE 0x006c03e0 /* -W-4R */
|
|
#define NV_056_SET_TEXTURE_MATRIX0_ENABLE_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_MATRIX0_ENABLE_V_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_MATRIX0_ENABLE_V_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_MATRIX1_ENABLE 0x006c03e4 /* -W-4R */
|
|
#define NV_056_SET_TEXTURE_MATRIX1_ENABLE_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_MATRIX1_ENABLE_V_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEXTURE_MATRIX1_ENABLE_V_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TLMODE 0x006c03e8 /* -W-4R */
|
|
#define NV_056_SET_TLMODE_PASSTHROUGH 0:0 /* -WXUF */
|
|
#define NV_056_SET_TLMODE_PASSTHROUGH_TRUE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TLMODE_PASSTHROUGH_FALSE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TLMODE_W_DIVIDE_0 1:1 /* -WXUF */
|
|
#define NV_056_SET_TLMODE_W_DIVIDE_0_DISABLE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TLMODE_W_DIVIDE_0_ENABLE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TLMODE_W_DIVIDE_1 2:2 /* -WXUF */
|
|
#define NV_056_SET_TLMODE_W_DIVIDE_1_DISABLE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TLMODE_W_DIVIDE_1_ENABLE 0x00000001 /* -W--V */
|
|
#define NV_056_SET_POINT_SIZE 0x006c03ec /* -W-4R */
|
|
#define NV_056_SET_POINT_SIZE_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SWATH_WIDTH 0x006c03f0 /* -W-4R */
|
|
#define NV_056_SET_SWATH_WIDTH_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SWATH_WIDTH_V_8 0x00000000 /* -W--V */
|
|
#define NV_056_SET_SWATH_WIDTH_V_16 0x00000001 /* -W--V */
|
|
#define NV_056_SET_SWATH_WIDTH_V_32 0x00000002 /* -W--V */
|
|
#define NV_056_SET_SWATH_WIDTH_V_64 0x00000003 /* -W--V */
|
|
#define NV_056_SET_FLAT_SHADE_OP 0x006c03f4 /* -W-4R */
|
|
#define NV_056_SET_FLAT_SHADE_OP_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_FLAT_SHADE_OP_V_LAST_VTX 0x00000000 /* -W--V */
|
|
#define NV_056_SET_FLAT_SHADE_OP_V_FIRST_VTX 0x00000001 /* -W--V */
|
|
#define NV_056_SET_MODEL_VIEW_MATRIX0(i) (0x006c0400+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_MODEL_VIEW_MATRIX0__SIZE_1 16 /* */
|
|
#define NV_056_SET_MODEL_VIEW_MATRIX0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_MODEL_VIEW_MATRIX1(i) (0x006c0440+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_MODEL_VIEW_MATRIX1__SIZE_1 16 /* */
|
|
#define NV_056_SET_MODEL_VIEW_MATRIX1_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_INVERSE_MODEL_VIEW_MATRIX0(i) (0x006c0480+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_INVERSE_MODEL_VIEW_MATRIX0__SIZE_1 16 /* */
|
|
#define NV_056_SET_INVERSE_MODEL_VIEW_MATRIX0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_INVERSE_MODEL_VIEW_MATRIX1(i) (0x006c04c0+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_INVERSE_MODEL_VIEW_MATRIX1__SIZE_1 16 /* */
|
|
#define NV_056_SET_INVERSE_MODEL_VIEW_MATRIX1_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_COMPOSITE_MATRIX(i) (0x006c0500+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_COMPOSITE_MATRIX__SIZE_1 16 /* */
|
|
#define NV_056_SET_COMPOSITE_MATRIX_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_MATRIX0(i) (0x006c0540+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_MATRIX0__SIZE_1 16 /* */
|
|
#define NV_056_SET_TEXTURE_MATRIX0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXTURE_MATRIX1(i) (0x006c0580+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXTURE_MATRIX1__SIZE_1 16 /* */
|
|
#define NV_056_SET_TEXTURE_MATRIX1_V 31:0 /* -WXUF */
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#define NV_056_SET_TEXGEN_SPLANE0(i) (0x006c0600+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_SPLANE0__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_SPLANE0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_TPLANE0(i) (0x006c0610+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_TPLANE0__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_TPLANE0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_RPLANE0(i) (0x006c0620+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_RPLANE0__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_RPLANE0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_QPLANE0(i) (0x006c0630+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_QPLANE0__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_QPLANE0_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_SPLANE1(i) (0x006c0640+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_SPLANE1__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_SPLANE1_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_TPLANE1(i) (0x006c0650+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_TPLANE1__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_TPLANE1_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_RPLANE1(i) (0x006c0660+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_RPLANE1__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_RPLANE1_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXGEN_QPLANE1(i) (0x006c0670+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXGEN_QPLANE1__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXGEN_QPLANE1_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_FOG_PARAMS(i) (0x006c0680+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_FOG_PARAMS__SIZE_1 3 /* */
|
|
#define NV_056_SET_FOG_PARAMS_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_FOG_PLANE(i) (0x006c068c+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_FOG_PLANE__SIZE_1 4 /* */
|
|
#define NV_056_SET_FOG_PLANE_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_PARAMS(i) (0x006c06a0+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_SPECULAR_PARAMS__SIZE_1 6 /* */
|
|
#define NV_056_SET_SPECULAR_PARAMS_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SCENE_AMBIENT_COLOR(i) (0x006c06c4+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_SCENE_AMBIENT_COLOR__SIZE_1 3 /* */
|
|
#define NV_056_SET_SCENE_AMBIENT_COLOR_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_VIEWPORT_OFFSET(i) (0x006c06e8+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_VIEWPORT_OFFSET__SIZE_1 4 /* */
|
|
#define NV_056_SET_VIEWPORT_OFFSET_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_POINT_PARAMS(i) (0x006c06f8+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_POINT_PARAMS__SIZE_1 8 /* */
|
|
#define NV_056_SET_POINT_PARAMS_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_EYE_POSITION(i) (0x006c0718+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_EYE_POSITION__SIZE_1 4 /* */
|
|
#define NV_056_SET_EYE_POSITION_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_AMBIENT_COLOR(i,j) (0x006c0800+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_AMBIENT_COLOR__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_AMBIENT_COLOR__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_AMBIENT_COLOR_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_DIFFUSE_COLOR(i,j) (0x006c080c+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_DIFFUSE_COLOR__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_DIFFUSE_COLOR__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_DIFFUSE_COLOR_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_SPECULAR_COLOR(i,j) (0x006c0818+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_SPECULAR_COLOR__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_SPECULAR_COLOR__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_SPECULAR_COLOR_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_LOCAL_RANGE(i) (0x006c0824+(i)*128) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_LOCAL_RANGE__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_LOCAL_RANGE_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_INFINITE_HALF_VECTOR(i,j) (0x006c0828+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_INFINITE_HALF_VECTOR__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_INFINITE_HALF_VECTOR__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_INFINITE_HALF_VECTOR_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_INFINITE_DIRECTION(i,j) (0x006c0834+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_INFINITE_DIRECTION__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_INFINITE_DIRECTION__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_INFINITE_DIRECTION_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_SPOT_FALLOFF(i,j) (0x006c0840+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_SPOT_FALLOFF__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_SPOT_FALLOFF__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_SPOT_FALLOFF_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_SPOT_DIRECTION(i,j) (0x006c084c+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_SPOT_DIRECTION__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_SPOT_DIRECTION__SIZE_2 4 /* */
|
|
#define NV_056_SET_LIGHT_SPOT_DIRECTION_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_LOCAL_POSITION(i,j) (0x006c085c+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_LOCAL_POSITION__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_LOCAL_POSITION__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_LOCAL_POSITION_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_LIGHT_LOCAL_ATTENUATION(i,j) (0x006c0868+(i)*128+(j)*4) /* -W-4A */
|
|
#define NV_056_SET_LIGHT_LOCAL_ATTENUATION__SIZE_1 8 /* */
|
|
#define NV_056_SET_LIGHT_LOCAL_ATTENUATION__SIZE_2 3 /* */
|
|
#define NV_056_SET_LIGHT_LOCAL_ATTENUATION_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_VERTEX3F(i) (0x006c0c00+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_VERTEX3F__SIZE_1 3 /* */
|
|
#define NV_056_SET_VERTEX3F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_VERTEX4F(i) (0x006c0c18+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_VERTEX4F__SIZE_1 4 /* */
|
|
#define NV_056_SET_VERTEX4F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_VERTEX4S(i) (0x006c0c28+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_VERTEX4S__SIZE_1 2 /* */
|
|
#define NV_056_SET_VERTEX4S_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_NORMAL3F(i) (0x006c0c30+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_NORMAL3F__SIZE_1 3 /* */
|
|
#define NV_056_SET_NORMAL3F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_NORMAL3S(i) (0x006c0c40+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_NORMAL3S__SIZE_1 2 /* */
|
|
#define NV_056_SET_NORMAL3S_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_COLOR4F(i) (0x006c0c50+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_DIFFUSE_COLOR4F__SIZE_1 4 /* */
|
|
#define NV_056_SET_DIFFUSE_COLOR4F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_COLOR3F(i) (0x006c0c60+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_DIFFUSE_COLOR3F__SIZE_1 3 /* */
|
|
#define NV_056_SET_DIFFUSE_COLOR3F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_COLOR4UB 0x006c0c6c /* -W-4R */
|
|
#define NV_056_SET_DIFFUSE_COLOR4UB_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_COLOR4F(i) (0x006c0c70+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_SPECULAR_COLOR4F__SIZE_1 4 /* */
|
|
#define NV_056_SET_SPECULAR_COLOR4F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_COLOR3F(i) (0x006c0c80+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_SPECULAR_COLOR3F__SIZE_1 3 /* */
|
|
#define NV_056_SET_SPECULAR_COLOR3F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_COLOR4UB 0x006c0c8c /* -W-4R */
|
|
#define NV_056_SET_SPECULAR_COLOR4UB_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD0_2F(i) (0x006c0c90+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXCOORD0_2F__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXCOORD0_2F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD0_2S 0x006c0c98 /* -W-4R */
|
|
#define NV_056_SET_TEXCOORD0_2S_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD0_4F(i) (0x006c0ca0+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXCOORD0_4F__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXCOORD0_4F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD0_4S(i) (0x006c0cb0+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXCOORD0_4S__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXCOORD0_4S_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD1_2F(i) (0x006c0cb8+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXCOORD1_2F__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXCOORD1_2F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD1_2S 0x006c0cc0 /* -W-4R */
|
|
#define NV_056_SET_TEXCOORD1_2S_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD1_4F(i) (0x006c0cc8+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXCOORD1_4F__SIZE_1 4 /* */
|
|
#define NV_056_SET_TEXCOORD1_4F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEXCOORD1_4S(i) (0x006c0cd8+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_TEXCOORD1_4S__SIZE_1 2 /* */
|
|
#define NV_056_SET_TEXCOORD1_4S_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_FOG1F 0x006c0ce0 /* -W-4R */
|
|
#define NV_056_SET_FOG1F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_WEIGHT1F 0x006c0ce4 /* -W-4R */
|
|
#define NV_056_SET_WEIGHT1F_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_EDGE_FLAG 0x006c0cec /* -W-4R */
|
|
#define NV_056_SET_EDGE_FLAG_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_EYE_DIRECTION_SW(i) (0x006c072c+(i)*4) /* -W-4A */
|
|
#define NV_056_SET_EYE_DIRECTION_SW__SIZE_1 3 /* */
|
|
#define NV_056_SET_EYE_DIRECTION_SW_V 31:0 /* -WXUF */
|
|
#define NV_056_INVALIDATE_VERTEX_CACHE_FILE 0x006c0cf0 /* -W-4R */
|
|
#define NV_056_INVALIDATE_VERTEX_CACHE_FILE_V 31:0 /* -WXUF */
|
|
#define NV_056_INVALIDATE_VERTEX_FILE 0x006c0cf4 /* -W-4R */
|
|
#define NV_056_INVALIDATE_VERTEX_FILE_V 31:0 /* -WXUF */
|
|
#define NV_056_TL_NOP 0x006c0cf8 /* -W-4R */
|
|
#define NV_056_TL_NOP_V 31:0 /* -WXUF */
|
|
#define NV_056_TL_SYNC 0x006c0cfc /* -W-4R */
|
|
#define NV_056_TL_SYNC_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_VERTEX_ARRAY_OFFSET 0x006c0d00 /* -W-4R */
|
|
#define NV_056_SET_VERTEX_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_OFFSET 0x006c0d08 /* -W-4R */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_ARRAY_OFFSET 0x006c0d10 /* -W-4R */
|
|
#define NV_056_SET_SPECULAR_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_OFFSET 0x006c0d18 /* -W-4R */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_OFFSET 0x006c0d20 /* -W-4R */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_NORMAL_ARRAY_OFFSET 0x006c0d28 /* -W-4R */
|
|
#define NV_056_SET_NORMAL_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_WEIGHT_ARRAY_OFFSET 0x006c0d30 /* -W-4R */
|
|
#define NV_056_SET_WEIGHT_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_FOG_ARRAY_OFFSET 0x006c0d38 /* -W-4R */
|
|
#define NV_056_SET_FOG_ARRAY_OFFSET_OFFSET 31:0 /* -WXUF */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT 0x006c0d04 /* -W-4R */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_W 31:24 /* -WXUF */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_W_NONE 0x00000000 /* -W--V */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_W_PRESENT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_STRIDE 23:8 /* -WXUF */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_SIZE_2 0x00000002 /* -W--V */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_SIZE_4 0x00000004 /* -W--V */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_TYPE_SHORT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_VERTEX_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT 0x006c0d0c /* -W-4R */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_SIZE_4 0x00000004 /* -W--V */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_TYPE_UNSIGNED_BYTE_BGRA 0x00000000 /* -W--V */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_DIFFUSE_ARRAY_FORMAT_TYPE_UNSIGNED_BYTE_RGBA 0x00000004 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT 0x006c0d14 /* -W-4R */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_SIZE_4 0x00000004 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_TYPE_UNSIGNED_BYTE_BGRA 0x00000000 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_SPECULAR_ARRAY_FORMAT_TYPE_UNSIGNED_BYTE_RGBA 0x00000004 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT 0x006c0d1c /* -W-4R */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_SIZE_1 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_SIZE_2 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_SIZE_4 0x00000004 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_TYPE_SHORT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD0_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT 0x006c0d24 /* -W-4R */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_SIZE_1 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_SIZE_2 0x00000002 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_SIZE_4 0x00000004 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_TYPE_SHORT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_TEX_COORD1_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT 0x006c0d2c /* -W-4R */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_TYPE_SHORT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_NORMAL_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT 0x006c0d34 /* -W-4R */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_SIZE_1 0x00000001 /* -W--V */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_TYPE_SHORT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_WEIGHT_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT 0x006c0d3c /* -W-4R */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_SIZE_0 0x00000000 /* -W--V */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_SIZE_1 0x00000001 /* -W--V */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_TYPE_SHORT 0x00000001 /* -W--V */
|
|
#define NV_056_SET_FOG_ARRAY_FORMAT_TYPE_FLOAT 0x00000002 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END 0x006c0dfc /* -W-4R */
|
|
#define NV_056_SET_BEGIN_END_OP 31:0 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END_OP_END 0x00000000 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_POINTS 0x00000001 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_LINES 0x00000002 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_LINE_LOOP 0x00000003 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_LINE_STRIP 0x00000004 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_TRIANGLES 0x00000005 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_TRIANGLE_STRIP 0x00000006 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_TRIANGLE_FAN 0x00000007 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_QUADS 0x00000008 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_QUAD_STRIP 0x00000009 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END_OP_POLYGON 0x0000000A /* -W--V */
|
|
#define NV_056_ARRAY_ELEMENT16(i) (0x006c0e00+(i)*4) /* -W-4A */
|
|
#define NV_056_ARRAY_ELEMENT16__SIZE_1 128 /* */
|
|
#define NV_056_ARRAY_ELEMENT16_VERTEX0 15:0 /* -WXUF */
|
|
#define NV_056_ARRAY_ELEMENT16_VERTEX1 31:16 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END2 0x006c10fc /* -W-4R */
|
|
#define NV_056_SET_BEGIN_END2_OP 31:0 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END2_OP_END 0x00000000 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_POINTS 0x00000001 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_LINES 0x00000002 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_LINE_LOOP 0x00000003 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_LINE_STRIP 0x00000004 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_TRIANGLES 0x00000005 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_TRIANGLE_STRIP 0x00000006 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_TRIANGLE_FAN 0x00000007 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_QUADS 0x00000008 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_QUAD_STRIP 0x00000009 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END2_OP_POLYGON 0x0000000A /* -W--V */
|
|
#define NV_056_ARRAY_ELEMENT32(i) (0x006c1100+(i)*4) /* -W-4A */
|
|
#define NV_056_ARRAY_ELEMENT32__SIZE_1 64 /* */
|
|
#define NV_056_ARRAY_ELEMENT32_V 31:0 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END3 0x006c13fc /* -W-4R */
|
|
#define NV_056_SET_BEGIN_END3_OP 31:0 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END3_OP_END 0x00000000 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_POINTS 0x00000001 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_LINES 0x00000002 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_LINE_LOOP 0x00000003 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_LINE_STRIP 0x00000004 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_TRIANGLES 0x00000005 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_TRIANGLE_STRIP 0x00000006 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_TRIANGLE_FAN 0x00000007 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_QUADS 0x00000008 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_QUAD_STRIP 0x00000009 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END3_OP_POLYGON 0x0000000A /* -W--V */
|
|
#define NV_056_DRAW_ARRAYS(i) (0x006c1400+(i)*4) /* -W-4A */
|
|
#define NV_056_DRAW_ARRAYS__SIZE_1 128 /* */
|
|
#define NV_056_DRAW_ARRAYS_COUNT 31:24 /* -WXUF */
|
|
#define NV_056_DRAW_ARRAYS_START_INDEX 23:0 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END4 0x006c17fc /* -W-4R */
|
|
#define NV_056_SET_BEGIN_END4_OP 31:0 /* -WXUF */
|
|
#define NV_056_SET_BEGIN_END4_OP_END 0x00000000 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_POINTS 0x00000001 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_LINES 0x00000002 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_LINE_LOOP 0x00000003 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_LINE_STRIP 0x00000004 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_TRIANGLES 0x00000005 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_TRIANGLE_STRIP 0x00000006 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_TRIANGLE_FAN 0x00000007 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_QUADS 0x00000008 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_QUAD_STRIP 0x00000009 /* -W--V */
|
|
#define NV_056_SET_BEGIN_END4_OP_POLYGON 0x0000000A /* -W--V */
|
|
#define NV_056_INLINE_ARRAY(i) (0x006c1800+(i)*4) /* -W-4A */
|
|
#define NV_056_INLINE_ARRAY__SIZE_1 512 /* */
|
|
#define NV_056_INLINE_ARRAY_V 31:0 /* -WXUF */
|
|
#define NV_056_DEBUG_INIT(i) (0x006c1600+(i)*4) /* -W-4A */
|
|
#define NV_056_DEBUG_INIT__SIZE_1 10 /* */
|
|
#define NV_056_DEBUG_INIT_V 31:0 /* -WXUF */
|
|
/* usr_nv20_kelvin_primitive.ref */
|
|
#define NV20_KELVIN_PRIMITIVE 0x00000097 /* ----C */
|
|
#define NV20_KELVIN_PRIMITIVE_HWCLASS 0x00000097 /* ----C */
|
|
#define NV_097 0x005c1fff:0x005c0000 /* -W--D */
|
|
#define NV_097_NV20_KELVIN_PRIMITIVE 0x005c0000 /* -W-4R */
|
|
#define NV_097_NV20_KELVIN_PRIMITIVE_HANDLE 31:0 /* -WXVF */
|
|
#define NV_097_NO_OPERATION 0x005c0100 /* -W-4R */
|
|
#define NV_097_NOTIFY 0x005c0104 /* -W-4R */
|
|
#define NV_097_NOTIFY_TYPE 31:0 /* -WXUF */
|
|
#define NV_097_NOTIFY_TYPE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_097_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_097_SET_WARNING_ENABLE 0x005c0108 /* -W-4R */
|
|
#define NV_097_SET_WARNING_ENABLE_V 31:0 /* -WXUF */
|
|
#define NV_097_SET_WARNING_ENABLE_V_STOP 0x00000000 /* -W--V */
|
|
#define NV_097_SET_WARNING_ENABLE_V_WRITE_ONLY 0x00000001 /* -W--V */
|
|
#define NV_097_SET_WARNING_ENABLE_V_WRITE_THEN_AWAKEN 0x00000002 /* -W--V */
|
|
#define NV_097_GET_STATE 0x005c010c /* -W-4R */
|
|
#define NV_097_GET_STATE_GETSTATE 31:0 /* -WXUF */
|
|
#define NV_097_GET_STATE_GETSTATE_ALL_STATE 0x00000001 /* -W--V */
|
|
#define NV_097_GET_STATE_GETSTATE_PUT_ALL_STATE 0x00000002 /* -W--V */
|
|
#define NV_097_WAIT_FOR_IDLE 0x005c0110 /* -W-4R */
|
|
#define NV_097_PM_TRIGGER 0x005c0140 /* -W-4R */
|
|
#define NV_097_PM_TRIGGER_V 31:0 /* -WXUF */
|
|
#define NV_097_PM_TRIGGER_V_NOP 0x00000000 /* -W--V */
|
|
#define NV_097_PM_TRIGGER_V_TRIGGER 0x00000001 /* -W--V */
|
|
#define NV_097_SET_FLIP_READ 0x005c0120 /* -W-4R */
|
|
#define NV_097_SET_FLIP_READ_V 31:0 /* -WXUF */
|
|
#define NV_097_SET_FLIP_WRITE 0x005c0124 /* -W-4R */
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#define NV_097_SET_FLIP_WRITE_V 31:0 /* -WXUF */
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#define NV_097_SET_FLIP_MODULO 0x005c0128 /* -W-4R */
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#define NV_097_SET_FLIP_MODULO_V 31:0 /* -WXUF */
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#define NV_097_FLIP_INCREMENT_WRITE 0x005c012c /* -W-4R */
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#define NV_097_FLIP_STALL 0x005c0130 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_NOTIFIES 0x005c0180 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_NOTIFIES_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_A 0x005c0184 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_A_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_B 0x005c0188 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_B_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_STATE 0x005c0190 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_STATE_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_COLOR 0x005c0194 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_COLOR_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_ZETA 0x005c0198 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_ZETA_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_VERTEX_A 0x005c019c /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_VERTEX_A_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_VERTEX_B 0x005c01a0 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_VERTEX_B_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_SEMAPHORE 0x005c01a4 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_SEMAPHORE_V 31:0 /* -WXUF */
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#define NV_097_SET_CONTEXT_DMA_REPORT 0x005c01a8 /* -W-4R */
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#define NV_097_SET_CONTEXT_DMA_REPORT_V 31:0 /* -WXUF */
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#define NV_097_SET_SURFACE_CLIP_HORIZONTAL 0x005c0200 /* -W-4R */
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#define NV_097_SET_SURFACE_CLIP_HORIZONTAL_X 15:0 /* -WXUF */
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#define NV_097_SET_SURFACE_CLIP_HORIZONTAL_WIDTH 31:16 /* -WXUF */
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#define NV_097_SET_SURFACE_CLIP_VERTICAL 0x005c0204 /* -W-4R */
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#define NV_097_SET_SURFACE_CLIP_VERTICAL_Y 15:0 /* -WXUF */
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#define NV_097_SET_SURFACE_CLIP_VERTICAL_HEIGHT 31:16 /* -WXUF */
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#define NV_097_SET_SURFACE_PITCH 0x005c020c /* -W-4R */
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#define NV_097_SET_SURFACE_PITCH_COLOR 15:0 /* -WXUF */
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#define NV_097_SET_SURFACE_PITCH_ZETA 31:16 /* -WXUF */
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#define NV_097_SET_SURFACE_COLOR_OFFSET 0x005c0210 /* -W-4R */
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#define NV_097_SET_SURFACE_COLOR_OFFSET_V 31:0 /* -WXUF */
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#define NV_097_SET_SURFACE_ZETA_OFFSET 0x005c0214 /* -W-4R */
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#define NV_097_SET_SURFACE_ZETA_OFFSET_V 31:0 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW(i) (0x005c0260+(i)*4) /* -W-4A */
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#define NV_097_SET_COMBINER_ALPHA_ICW__SIZE_1 8 /* */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP 31:29 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_ALPHA 28:28 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE 27:24 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_A_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP 23:21 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_ALPHA 20:20 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE 19:16 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_B_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP 15:13 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_ALPHA 12:12 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_C_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP 7:5 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_ALPHA 4:4 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE 3:0 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_ICW_D_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW(i) (0x005c0ac0+(i)*4) /* -W-4A */
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#define NV_097_SET_COMBINER_COLOR_ICW__SIZE_1 8 /* */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP 31:29 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_ALPHA 28:28 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE 27:24 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_A_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP 23:21 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_ALPHA 20:20 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE 19:16 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_B_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP 15:13 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_ALPHA 12:12 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_C_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP 7:5 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_UNSIGNED_IDENTITY 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_UNSIGNED_INVERT 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_EXPAND_NORMAL 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_EXPAND_NEGATE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_HALFBIAS_NORMAL 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_HALFBIAS_NEGATE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_SIGNED_IDENTITY 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_MAP_SIGNED_NEGATE 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_ALPHA 4:4 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE 3:0 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_ICW_D_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_FACTOR0(i) (0x005c0a60+(i)*4) /* -W-4A */
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#define NV_097_SET_COMBINER_FACTOR0__SIZE_1 8 /* */
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#define NV_097_SET_COMBINER_FACTOR0_BLUE 7:0 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR0_GREEN 15:8 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR0_RED 23:16 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR0_ALPHA 31:24 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR1(i) (0x005c0a80+(i)*4) /* -W-4A */
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#define NV_097_SET_COMBINER_FACTOR1__SIZE_1 8 /* */
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#define NV_097_SET_COMBINER_FACTOR1_BLUE 7:0 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR1_GREEN 15:8 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR1_RED 23:16 /* -WXUF */
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#define NV_097_SET_COMBINER_FACTOR1_ALPHA 31:24 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_OCW(i) (0x005c0aa0+(i)*4) /* -W-4A */
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#define NV_097_SET_COMBINER_ALPHA_OCW__SIZE_1 8 /* */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION 31:15 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION_NOSHIFT 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION_NOSHIFT_BIAS 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTLEFTBY1 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTLEFTBY1_BIAS 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTLEFTBY2 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_OPERATION_SHIFTRIGHTBY1 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_MUX_ENABLE 14:14 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_OCW_MUX_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_MUX_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_SUM_DST_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST 7:4 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_AB_DST_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST 3:0 /* -WXUF */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_ALPHA_OCW_CD_DST_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0 0x005c0288 /* -W-4R */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE 31:29 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA 28:28 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE 27:24 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_A_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE 23:21 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA 20:20 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE 19:16 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_B_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE 15:13 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA 12:12 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_C_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE 7:5 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA 4:4 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE 3:0 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_SPECLIT 0x0000000E /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW0_D_SOURCE_REG_EF_PROD 0x0000000F /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1 0x005c028c /* -W-4R */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE 31:29 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA 28:28 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE 27:24 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_E_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE 23:21 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA 20:20 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE 19:16 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_F_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE 15:13 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_INVERSE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA 12:12 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_ALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_1 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_2 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_3 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_G_SOURCE_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP 7:7 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_CLAMP_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5 6:6 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R5_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12 5:0 /* -WXUF */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_SPECULAR_FOG_CW1_SPECULAR_ADD_INVERT_R12_TRUE 0x00000020 /* -W--V */
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#define NV_097_SET_CONTROL0 0x005c0290 /* -W-4R */
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#define NV_097_SET_CONTROL0_COLOR_SPACE_CONVERT 31:28 /* -WXUF */
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#define NV_097_SET_CONTROL0_COLOR_SPACE_CONVERT_PASS 0x00000000 /* -W--V */
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#define NV_097_SET_CONTROL0_COLOR_SPACE_CONVERT_CRYCB_TO_RGB 0x00000001 /* -W--V */
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#define NV_097_SET_CONTROL0_COLOR_SPACE_CONVERT_SCRYSCB_TO_RGB 0x00000002 /* -W--V */
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#define NV_097_SET_CONTROL0_PREMULTIPLIEDALPHA 27:24 /* -WXUF */
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#define NV_097_SET_CONTROL0_PREMULTIPLIEDALPHA_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_CONTROL0_PREMULTIPLIEDALPHA_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_CONTROL0_TEXTUREPERSPECTIVE 23:20 /* -WXUF */
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#define NV_097_SET_CONTROL0_TEXTUREPERSPECTIVE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_CONTROL0_TEXTUREPERSPECTIVE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_CONTROL0_Z_PERSPECTIVE_ENABLE 19:16 /* -WXUF */
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#define NV_097_SET_CONTROL0_Z_PERSPECTIVE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_CONTROL0_Z_PERSPECTIVE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_CONTROL0_Z_FORMAT 15:12 /* -WXUF */
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#define NV_097_SET_CONTROL0_Z_FORMAT_FIXED 0x00000000 /* -W--V */
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#define NV_097_SET_CONTROL0_Z_FORMAT_FLOAT 0x00000001 /* -W--V */
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#define NV_097_SET_CONTROL0_STENCIL_WRITE_ENABLE 7:0 /* -WXUF */
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#define NV_097_SET_CONTROL0_STENCIL_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_CONTROL0_STENCIL_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_CONTROL 0x005c0294 /* -W-4R */
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#define NV_097_SET_LIGHT_CONTROL_LOCALEYE 16:16 /* -WXUF */
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#define NV_097_SET_LIGHT_CONTROL_LOCALEYE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_CONTROL_LOCALEYE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_CONTROL_SOUT 31:17 /* -WXUF */
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#define NV_097_SET_LIGHT_CONTROL_SOUT_ZERO_OUT 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_CONTROL_SOUT_PASSTHROUGH 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_CONTROL_SEPARATE_SPECULAR_EN 1:0 /* -WXUF */
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#define NV_097_SET_LIGHT_CONTROL_SEPARATE_SPECULAR_EN_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_CONTROL_SEPARATE_SPECULAR_EN_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL 0x005c0298 /* -W-4R */
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#define NV_097_SET_COLOR_MATERIAL_EMISSIVE_MATERIAL 1:0 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_EMISSIVE_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_EMISSIVE_MATERIAL_DIFFUSE_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_EMISSIVE_MATERIAL_SPECULAR_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_AMBIENT_MATERIAL 3:2 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_AMBIENT_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_AMBIENT_MATERIAL_DIFFUSE_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_AMBIENT_MATERIAL_SPECULAR_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_DIFF_MATERIAL 5:4 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_DIFF_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_DIFF_MATERIAL_DIFFUSE_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_DIFF_MATERIAL_SPECULAR_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_SPECULAR_MATERIAL 7:6 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_SPECULAR_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_SPECULAR_MATERIAL_DIFFUSE_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_SPECULAR_MATERIAL_SPECULAR_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_EMISSIVE_MATERIAL 9:8 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_BACK_EMISSIVE_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_EMISSIVE_MATERIAL_DIFF_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_EMISSIVE_MATERIAL_SPEC_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_AMBIENT_MATERIAL 11:10 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_BACK_AMBIENT_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_AMBIENT_MATERIAL_DIFF_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_AMBIENT_MATERIAL_SPEC_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_DIFF_MATERIAL 13:12 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_BACK_DIFF_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_DIFF_MATERIAL_DIFF_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_DIFF_MATERIAL_SPEC_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_SPECULAR_MATERIAL 15:14 /* -WXUF */
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#define NV_097_SET_COLOR_MATERIAL_BACK_SPECULAR_MATERIAL_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_SPECULAR_MATERIAL_DIFF_VTX_COLOR 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MATERIAL_BACK_SPECULAR_MATERIAL_SPEC_VTX_COLOR 0x00000002 /* -W--V */
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#define NV_097_SET_FOG_MODE 0x005c029c /* -W-4R */
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#define NV_097_SET_FOG_MODE_V 31:0 /* -WXUF */
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#define NV_097_SET_FOG_MODE_V_LINEAR 0x00002601 /* -W--V */
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#define NV_097_SET_FOG_MODE_V_EXP 0x00000800 /* -W--V */
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#define NV_097_SET_FOG_MODE_V_EXP2 0x00000801 /* -W--V */
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#define NV_097_SET_FOG_MODE_V_EXP_ABS 0x00000802 /* -W--V */
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#define NV_097_SET_FOG_MODE_V_EXP2_ABS 0x00000803 /* -W--V */
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#define NV_097_SET_FOG_MODE_V_LINEAR_ABS 0x00000804 /* -W--V */
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#define NV_097_SET_FOG_GEN_MODE 0x005c02a0 /* -W-4R */
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#define NV_097_SET_FOG_GEN_MODE_V 31:0 /* -WXUF */
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#define NV_097_SET_FOG_GEN_MODE_V_SPEC_ALPHA 0x00000000 /* -W--V */
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#define NV_097_SET_FOG_GEN_MODE_V_RADIAL 0x00000001 /* -W--V */
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#define NV_097_SET_FOG_GEN_MODE_V_PLANAR 0x00000002 /* -W--V */
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#define NV_097_SET_FOG_GEN_MODE_V_ABS_PLANAR 0x00000003 /* -W--V */
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#define NV_097_SET_FOG_GEN_MODE_V_FOG_X 0x00000006 /* -W--V */
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#define NV_097_SET_FOG_ENABLE 0x005c02a4 /* -W-4R */
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#define NV_097_SET_FOG_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_FOG_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_FOG_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_FOG_COLOR 0x005c02a8 /* -W-4R */
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#define NV_097_SET_FOG_COLOR_RED 7:0 /* -WXUF */
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#define NV_097_SET_FOG_COLOR_GREEN 15:8 /* -WXUF */
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#define NV_097_SET_FOG_COLOR_BLUE 23:16 /* -WXUF */
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#define NV_097_SET_FOG_COLOR_ALPHA 31:24 /* -WXUF */
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#define NV_097_SET_COLOR_KEY_COLOR(i) (0x005c0ae0+(i)*4) /* -W-4A */
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#define NV_097_SET_COLOR_KEY_COLOR__SIZE_1 4 /* */
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#define NV_097_SET_COLOR_KEY_COLOR_V 31:0 /* -WXUF */
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#define NV_097_SET_WINDOW_CLIP_TYPE 0x005c02b4 /* -W-4R */
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#define NV_097_SET_WINDOW_CLIP_TYPE_V 31:0 /* -WXUF */
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#define NV_097_SET_WINDOW_CLIP_TYPE_V_INCLUSIVE 0x00000000 /* -W--V */
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#define NV_097_SET_WINDOW_CLIP_TYPE_V_EXCLUSIVE 0x00000001 /* -W--V */
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#define NV_097_SET_WINDOW_CLIP_HORIZONTAL(i) (0x005c02c0+(i)*4) /* -W-4A */
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#define NV_097_SET_WINDOW_CLIP_HORIZONTAL__SIZE_1 8 /* */
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#define NV_097_SET_WINDOW_CLIP_HORIZONTAL_XMIN 11:0 /* -WXUF */
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#define NV_097_SET_WINDOW_CLIP_HORIZONTAL_XMAX 27:16 /* -WXUF */
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#define NV_097_SET_WINDOW_CLIP_VERTICAL(i) (0x005c02e0+(i)*4) /* -W-4A */
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#define NV_097_SET_WINDOW_CLIP_VERTICAL__SIZE_1 8 /* */
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#define NV_097_SET_WINDOW_CLIP_VERTICAL_YMIN 11:0 /* -WXUF */
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#define NV_097_SET_WINDOW_CLIP_VERTICAL_YMAX 27:16 /* -WXUF */
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#define NV_097_SET_ALPHA_TEST_ENABLE 0x005c0300 /* -W-4R */
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#define NV_097_SET_ALPHA_TEST_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_ALPHA_TEST_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_ALPHA_TEST_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_BLEND_ENABLE 0x005c0304 /* -W-4R */
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#define NV_097_SET_BLEND_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_BLEND_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_BLEND_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_CULL_FACE_ENABLE 0x005c0308 /* -W-4R */
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#define NV_097_SET_CULL_FACE_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_CULL_FACE_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_CULL_FACE_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_DEPTH_TEST_ENABLE 0x005c030c /* -W-4R */
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#define NV_097_SET_DEPTH_TEST_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_DEPTH_TEST_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_DEPTH_TEST_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_DITHER_ENABLE 0x005c0310 /* -W-4R */
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#define NV_097_SET_DITHER_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_DITHER_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_DITHER_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHTING_ENABLE 0x005c0314 /* -W-4R */
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#define NV_097_SET_LIGHTING_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_LIGHTING_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHTING_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POINT_PARAMS_ENABLE 0x005c0318 /* -W-4R */
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#define NV_097_SET_POINT_PARAMS_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_POINT_PARAMS_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_POINT_PARAMS_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POINT_SMOOTH_ENABLE 0x005c031c /* -W-4R */
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#define NV_097_SET_POINT_SMOOTH_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_POINT_SMOOTH_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_POINT_SMOOTH_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_LINE_SMOOTH_ENABLE 0x005c0320 /* -W-4R */
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#define NV_097_SET_LINE_SMOOTH_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_LINE_SMOOTH_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_LINE_SMOOTH_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POLY_SMOOTH_ENABLE 0x005c0324 /* -W-4R */
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#define NV_097_SET_POLY_SMOOTH_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_POLY_SMOOTH_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_POLY_SMOOTH_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_STIPPLE_CONTROL 0x005c147c /* -W-4R */
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#define NV_097_SET_STIPPLE_CONTROL_V 31:0 /* -WXUF */
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#define NV_097_SET_STIPPLE_CONTROL_V_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_STIPPLE_CONTROL_V_POLYGON 0x00000001 /* -W--V */
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#define NV_097_SET_STIPPLE_PATTERN(i) (0x005c1480+(i)*4) /* -W-4A */
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#define NV_097_SET_STIPPLE_PATTERN__SIZE_1 32 /* */
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#define NV_097_SET_STIPPLE_PATTERN_V 31:0 /* -WXUF */
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#define NV_097_SET_SKIN_MODE 0x005c0328 /* -W-4R */
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#define NV_097_SET_SKIN_MODE_V 31:0 /* -WXUF */
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#define NV_097_SET_SKIN_MODE_V_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_SKIN_MODE_V_2G 0x00000001 /* -W--V */
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#define NV_097_SET_SKIN_MODE_V_2 0x00000002 /* -W--V */
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#define NV_097_SET_SKIN_MODE_V_3G 0x00000003 /* -W--V */
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#define NV_097_SET_SKIN_MODE_V_3 0x00000004 /* -W--V */
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#define NV_097_SET_SKIN_MODE_V_4G 0x00000005 /* -W--V */
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#define NV_097_SET_SKIN_MODE_V_4 0x00000006 /* -W--V */
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#define NV_097_SET_STENCIL_TEST_ENABLE 0x005c032c /* -W-4R */
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#define NV_097_SET_STENCIL_TEST_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_TEST_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_STENCIL_TEST_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POLY_OFFSET_POINT_ENABLE 0x005c0330 /* -W-4R */
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#define NV_097_SET_POLY_OFFSET_POINT_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_POLY_OFFSET_POINT_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_POLY_OFFSET_POINT_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POLY_OFFSET_LINE_ENABLE 0x005c0334 /* -W-4R */
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#define NV_097_SET_POLY_OFFSET_LINE_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_POLY_OFFSET_LINE_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_POLY_OFFSET_LINE_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POLY_OFFSET_FILL_ENABLE 0x005c0338 /* -W-4R */
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#define NV_097_SET_POLY_OFFSET_FILL_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_POLY_OFFSET_FILL_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_POLY_OFFSET_FILL_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC 0x005c033c /* -W-4R */
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#define NV_097_SET_ALPHA_FUNC_V 31:0 /* -WXUF */
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#define NV_097_SET_ALPHA_FUNC_V_NEVER 0x00000200 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_LESS 0x00000201 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_EQUAL 0x00000202 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_LEQUAL 0x00000203 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_GREATER 0x00000204 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_NOTEQUAL 0x00000205 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_GEQUAL 0x00000206 /* -W--V */
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#define NV_097_SET_ALPHA_FUNC_V_ALWAYS 0x00000207 /* -W--V */
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#define NV_097_SET_ALPHA_REF 0x005c0340 /* -W-4R */
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#define NV_097_SET_ALPHA_REF_V 31:0 /* -WXUF */
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#define NV_097_SET_BLEND_FUNC_SFACTOR 0x005c0344 /* -W-4R */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V 31:0 /* -WXUF */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ZERO 0x00000000 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE 0x00000001 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_SRC_COLOR 0x00000300 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_COLOR 0x00000301 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA 0x00000302 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_SRC_ALPHA 0x00000303 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_DST_ALPHA 0x00000304 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_ALPHA 0x00000305 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_DST_COLOR 0x00000306 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_DST_COLOR 0x00000307 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_SRC_ALPHA_SATURATE 0x00000308 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_COLOR 0x00008001 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x00008002 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_CONSTANT_ALPHA 0x00008003 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_SFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x00008004 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR 0x005c0348 /* -W-4R */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V 31:0 /* -WXUF */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ZERO 0x00000000 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE 0x00000001 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_SRC_COLOR 0x00000300 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_COLOR 0x00000301 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA 0x00000302 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_SRC_ALPHA 0x00000303 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_DST_ALPHA 0x00000304 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_ALPHA 0x00000305 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_DST_COLOR 0x00000306 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_DST_COLOR 0x00000307 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_SRC_ALPHA_SATURATE 0x00000308 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_COLOR 0x00008001 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_COLOR 0x00008002 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_CONSTANT_ALPHA 0x00008003 /* -W--V */
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#define NV_097_SET_BLEND_FUNC_DFACTOR_V_ONE_MINUS_CONSTANT_ALPHA 0x00008004 /* -W--V */
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#define NV_097_SET_BLEND_COLOR 0x005c034c /* -W-4R */
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#define NV_097_SET_BLEND_COLOR_V 31:0 /* -WXUF */
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#define NV_097_SET_BLEND_EQUATION 0x005c0350 /* -W-4R */
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#define NV_097_SET_BLEND_EQUATION_V 31:0 /* -WXUF */
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#define NV_097_SET_BLEND_EQUATION_V_FUNC_SUBTRACT 0x0000800A /* -W--V */
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#define NV_097_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT 0x0000800B /* -W--V */
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#define NV_097_SET_BLEND_EQUATION_V_FUNC_ADD 0x00008006 /* -W--V */
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#define NV_097_SET_BLEND_EQUATION_V_MIN 0x00008007 /* -W--V */
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#define NV_097_SET_BLEND_EQUATION_V_MAX 0x00008008 /* -W--V */
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#define NV_097_SET_BLEND_EQUATION_V_FUNC_REVERSE_SUBTRACT_SIGNED 0x0000F005 /* -W--V */
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#define NV_097_SET_BLEND_EQUATION_V_FUNC_ADD_SIGNED 0x0000F006 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC 0x005c0354 /* -W-4R */
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#define NV_097_SET_DEPTH_FUNC_V 31:0 /* -WXUF */
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#define NV_097_SET_DEPTH_FUNC_V_NEVER 0x00000200 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_LESS 0x00000201 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_EQUAL 0x00000202 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_LEQUAL 0x00000203 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_GREATER 0x00000204 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_NOTEQUAL 0x00000205 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_GEQUAL 0x00000206 /* -W--V */
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#define NV_097_SET_DEPTH_FUNC_V_ALWAYS 0x00000207 /* -W--V */
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#define NV_097_SET_COLOR_MASK 0x005c0358 /* -W-4R */
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#define NV_097_SET_COLOR_MASK_ALPHA_WRITE_ENABLE 31:24 /* -WXUF */
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#define NV_097_SET_COLOR_MASK_ALPHA_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MASK_ALPHA_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MASK_RED_WRITE_ENABLE 23:16 /* -WXUF */
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#define NV_097_SET_COLOR_MASK_RED_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MASK_RED_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MASK_GREEN_WRITE_ENABLE 15:8 /* -WXUF */
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#define NV_097_SET_COLOR_MASK_GREEN_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MASK_GREEN_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COLOR_MASK_BLUE_WRITE_ENABLE 7:0 /* -WXUF */
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#define NV_097_SET_COLOR_MASK_BLUE_WRITE_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COLOR_MASK_BLUE_WRITE_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_DEPTH_MASK 0x005c035c /* -W-4R */
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#define NV_097_SET_DEPTH_MASK_V 31:0 /* -WXUF */
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#define NV_097_SET_DEPTH_MASK_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_DEPTH_MASK_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_STENCIL_MASK 0x005c0360 /* -W-4R */
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#define NV_097_SET_STENCIL_MASK_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_FUNC 0x005c0364 /* -W-4R */
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#define NV_097_SET_STENCIL_FUNC_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_FUNC_V_NEVER 0x00000200 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_LESS 0x00000201 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_EQUAL 0x00000202 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_LEQUAL 0x00000203 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_GREATER 0x00000204 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_NOTEQUAL 0x00000205 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_GEQUAL 0x00000206 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_V_ALWAYS 0x00000207 /* -W--V */
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#define NV_097_SET_STENCIL_FUNC_REF 0x005c0368 /* -W-4R */
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#define NV_097_SET_STENCIL_FUNC_REF_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_FUNC_MASK 0x005c036c /* -W-4R */
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#define NV_097_SET_STENCIL_FUNC_MASK_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_OP_FAIL 0x005c0370 /* -W-4R */
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#define NV_097_SET_STENCIL_OP_FAIL_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_OP_FAIL_V_KEEP 0x00001E00 /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_ZERO 0x00000000 /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_REPLACE 0x00001E01 /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_INCRSAT 0x00001E02 /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_DECRSAT 0x00001E03 /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_INVERT 0x0000150A /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_INCR 0x00008507 /* -W--V */
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#define NV_097_SET_STENCIL_OP_FAIL_V_DECR 0x00008508 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL 0x005c0374 /* -W-4R */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_KEEP 0x00001E00 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_ZERO 0x00000000 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_REPLACE 0x00001E01 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_INCRSAT 0x00001E02 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_DECRSAT 0x00001E03 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_INVERT 0x0000150A /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_INCR 0x00008507 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZFAIL_V_DECR 0x00008508 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS 0x005c0378 /* -W-4R */
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#define NV_097_SET_STENCIL_OP_ZPASS_V 31:0 /* -WXUF */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_KEEP 0x00001E00 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_ZERO 0x00000000 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_REPLACE 0x00001E01 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_INCRSAT 0x00001E02 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_DECRSAT 0x00001E03 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_INVERT 0x0000150A /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_INCR 0x00008507 /* -W--V */
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#define NV_097_SET_STENCIL_OP_ZPASS_V_DECR 0x00008508 /* -W--V */
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#define NV_097_SET_SHADE_MODE 0x005c037c /* -W-4R */
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#define NV_097_SET_SHADE_MODE_V 31:0 /* -WXUF */
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#define NV_097_SET_SHADE_MODE_V_FLAT 0x00001D00 /* -W--V */
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#define NV_097_SET_SHADE_MODE_V_SMOOTH 0x00001D01 /* -W--V */
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#define NV_097_SET_LINE_WIDTH 0x005c0380 /* -W-4R */
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#define NV_097_SET_LINE_WIDTH_V 31:0 /* -WXUF */
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#define NV_097_SET_POLYGON_OFFSET_SCALE_FACTOR 0x005c0384 /* -W-4R */
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#define NV_097_SET_POLYGON_OFFSET_SCALE_FACTOR_V 31:0 /* -WXUF */
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#define NV_097_SET_POLYGON_OFFSET_BIAS 0x005c0388 /* -W-4R */
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#define NV_097_SET_POLYGON_OFFSET_BIAS_V 31:0 /* -WXUF */
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#define NV_097_SET_FRONT_POLYGON_MODE 0x005c038c /* -W-4R */
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#define NV_097_SET_FRONT_POLYGON_MODE_V 31:0 /* -WXUF */
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#define NV_097_SET_FRONT_POLYGON_MODE_V_POINT 0x00001B00 /* -W--V */
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#define NV_097_SET_FRONT_POLYGON_MODE_V_LINE 0x00001B01 /* -W--V */
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#define NV_097_SET_FRONT_POLYGON_MODE_V_FILL 0x00001B02 /* -W--V */
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#define NV_097_SET_BACK_POLYGON_MODE 0x005c0390 /* -W-4R */
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#define NV_097_SET_BACK_POLYGON_MODE_V 31:0 /* -WXUF */
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#define NV_097_SET_BACK_POLYGON_MODE_V_POINT 0x00001B00 /* -W--V */
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#define NV_097_SET_BACK_POLYGON_MODE_V_LINE 0x00001B01 /* -W--V */
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#define NV_097_SET_BACK_POLYGON_MODE_V_FILL 0x00001B02 /* -W--V */
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#define NV_097_SET_CLIP_MIN 0x005c0394 /* -W-4R */
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#define NV_097_SET_CLIP_MIN_V 31:0 /* -WXUF */
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#define NV_097_SET_CLIP_MAX 0x005c0398 /* -W-4R */
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#define NV_097_SET_CLIP_MAX_V 31:0 /* -WXUF */
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#define NV_097_SET_CULL_FACE 0x005c039c /* -W-4R */
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#define NV_097_SET_CULL_FACE_V 31:0 /* -WXUF */
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#define NV_097_SET_CULL_FACE_V_FRONT 0x00000404 /* -W--V */
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#define NV_097_SET_CULL_FACE_V_BACK 0x00000405 /* -W--V */
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#define NV_097_SET_CULL_FACE_V_FRONT_AND_BACK 0x00000408 /* -W--V */
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#define NV_097_SET_FRONT_FACE 0x005c03a0 /* -W-4R */
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#define NV_097_SET_FRONT_FACE_V 31:0 /* -WXUF */
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#define NV_097_SET_FRONT_FACE_V_CW 0x00000900 /* -W--V */
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#define NV_097_SET_FRONT_FACE_V_CCW 0x00000901 /* -W--V */
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#define NV_097_SET_NORMALIZATION_ENABLE 0x005c03a4 /* -W-4R */
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#define NV_097_SET_NORMALIZATION_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_NORMALIZATION_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_NORMALIZATION_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_MATERIAL_EMISSION(i) (0x005c03a8+(i)*4) /* -W-4A */
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#define NV_097_SET_MATERIAL_EMISSION__SIZE_1 3 /* */
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#define NV_097_SET_MATERIAL_EMISSION_V 31:0 /* -WXUF */
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#define NV_097_SET_MATERIAL_ALPHA 0x005c03b4 /* -W-4R */
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#define NV_097_SET_MATERIAL_ALPHA_V 31:0 /* -WXUF */
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#define NV_097_SET_BACK_MATERIAL_ALPHA 0x005c17ac /* -W-4R */
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#define NV_097_SET_BACK_MATERIAL_ALPHA_V 31:0 /* -WXUF */
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#define NV_097_SET_SPECULAR_ENABLE 0x005c03b8 /* -W-4R */
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#define NV_097_SET_SPECULAR_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_SPECULAR_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_SPECULAR_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK 0x005c03bc /* -W-4R */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT0 1:0 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT0_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT0_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT0_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT0_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT1 3:2 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT1_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT1_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT1_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT1_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT2 5:4 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT2_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT2_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT2_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT2_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT3 7:6 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT3_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT3_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT3_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT3_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT4 9:8 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT4_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT4_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT4_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT4_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT5 11:10 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT5_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT5_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT5_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT5_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT6 13:12 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT6_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT6_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT6_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT6_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT7 15:14 /* -WXUF */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT7_OFF 0x00000000 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT7_INFINITE 0x00000001 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT7_LOCAL 0x00000002 /* -W--V */
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#define NV_097_SET_LIGHT_ENABLE_MASK_LIGHT7_SPOT 0x00000003 /* -W--V */
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#define NV_097_SET_VERTEX_DATA2F_M(i,j) (0x005c1880+(i)*8+(j)*4) /* -W-4A */
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#define NV_097_SET_VERTEX_DATA2F_M__SIZE_1 16 /* */
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#define NV_097_SET_VERTEX_DATA2F_M__SIZE_2 2 /* */
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#define NV_097_SET_VERTEX_DATA2F_M_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX_DATA4F_M(i,j) (0x005c1a00+(i)*16+(j)*4) /* -W-4A */
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#define NV_097_SET_VERTEX_DATA4F_M__SIZE_1 16 /* */
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#define NV_097_SET_VERTEX_DATA4F_M__SIZE_2 4 /* */
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#define NV_097_SET_VERTEX_DATA4F_M_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX_DATA2S(i) (0x005c1900+(i)*4) /* -W-4A */
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#define NV_097_SET_VERTEX_DATA2S__SIZE_1 16 /* */
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#define NV_097_SET_VERTEX_DATA2S_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX_DATA4UB(i) (0x005c1940+(i)*4) /* -W-4A */
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#define NV_097_SET_VERTEX_DATA4UB__SIZE_1 16 /* */
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#define NV_097_SET_VERTEX_DATA4UB_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX_DATA4S_M(i,j) (0x005c1980+(i)*8+(j)*4) /* -W-4A */
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#define NV_097_SET_VERTEX_DATA4S_M__SIZE_1 16 /* */
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#define NV_097_SET_VERTEX_DATA4S_M__SIZE_2 2 /* */
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#define NV_097_SET_VERTEX_DATA4S_M_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_S(i) (0x005c03c0+(i)*16) /* -W-4A */
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#define NV_097_SET_TEXGEN_S__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_S_V_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXGEN_S_V_NORMAL_MAP 0x00008511 /* -W--V */
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#define NV_097_SET_TEXGEN_S_V_REFLECTION_MAP 0x00008512 /* -W--V */
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#define NV_097_SET_TEXGEN_S_V_EYE_LINEAR 0x00002400 /* -W--V */
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#define NV_097_SET_TEXGEN_S_V_OBJECT_LINEAR 0x00002401 /* -W--V */
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#define NV_097_SET_TEXGEN_S_V_SPHERE_MAP 0x00002402 /* -W--V */
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#define NV_097_SET_TEXGEN_T(i) (0x005c03c4+(i)*16) /* -W-4A */
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#define NV_097_SET_TEXGEN_T__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_T_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_T_V_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXGEN_T_V_NORMAL_MAP 0x00008511 /* -W--V */
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#define NV_097_SET_TEXGEN_T_V_REFLECTION_MAP 0x00008512 /* -W--V */
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#define NV_097_SET_TEXGEN_T_V_EYE_LINEAR 0x00002400 /* -W--V */
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#define NV_097_SET_TEXGEN_T_V_OBJECT_LINEAR 0x00002401 /* -W--V */
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#define NV_097_SET_TEXGEN_T_V_SPHERE_MAP 0x00002402 /* -W--V */
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#define NV_097_SET_TEXGEN_R(i) (0x005c03c8+(i)*16) /* -W-4A */
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#define NV_097_SET_TEXGEN_R__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_R_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_R_V_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXGEN_R_V_NORMAL_MAP 0x00008511 /* -W--V */
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#define NV_097_SET_TEXGEN_R_V_REFLECTION_MAP 0x00008512 /* -W--V */
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#define NV_097_SET_TEXGEN_R_V_EYE_LINEAR 0x00002400 /* -W--V */
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#define NV_097_SET_TEXGEN_R_V_OBJECT_LINEAR 0x00002401 /* -W--V */
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#define NV_097_SET_TEXGEN_Q(i) (0x005c03cc+(i)*16) /* -W-4A */
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#define NV_097_SET_TEXGEN_Q__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_Q_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_Q_V_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXGEN_Q_V_EYE_LINEAR 0x00002400 /* -W--V */
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#define NV_097_SET_TEXGEN_Q_V_OBJECT_LINEAR 0x00002401 /* -W--V */
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#define NV_097_SET_TEXGEN_VIEW_MODEL 0x005c09cc /* -W-4R */
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#define NV_097_SET_TEXGEN_VIEW_MODEL_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_VIEW_MODEL_V_LOCAL_VIEWER 0x00000000 /* -W--V */
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#define NV_097_SET_TEXGEN_VIEW_MODEL_V_INFINITE_VIEWER 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_MATRIX_ENABLE(i) (0x005c0420+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXTURE_MATRIX_ENABLE__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_MATRIX_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_MATRIX_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_MATRIX_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_POINT_SIZE 0x005c043c /* -W-4R */
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#define NV_097_SET_POINT_SIZE_V 31:0 /* -WXUF */
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#define NV_097_SET_SWATH_WIDTH 0x005c09f8 /* -W-4R */
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#define NV_097_SET_SWATH_WIDTH_V 31:0 /* -WXUF */
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#define NV_097_SET_SWATH_WIDTH_V_8 0x00000000 /* -W--V */
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#define NV_097_SET_SWATH_WIDTH_V_16 0x00000001 /* -W--V */
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#define NV_097_SET_SWATH_WIDTH_V_32 0x00000002 /* -W--V */
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#define NV_097_SET_SWATH_WIDTH_V_64 0x00000003 /* -W--V */
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#define NV_097_SET_SWATH_WIDTH_V_128 0x00000004 /* -W--V */
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#define NV_097_SET_SWATH_WIDTH_V_OFF 0x0000000F /* -W--V */
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#define NV_097_SET_FLAT_SHADE_OP 0x005c09fc /* -W-4R */
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#define NV_097_SET_FLAT_SHADE_OP_V 31:0 /* -WXUF */
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#define NV_097_SET_FLAT_SHADE_OP_V_LAST_VTX 0x00000000 /* -W--V */
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#define NV_097_SET_FLAT_SHADE_OP_V_FIRST_VTX 0x00000001 /* -W--V */
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#define NV_097_SET_PROJECTION_MATRIX(i) (0x005c0440+(i)*4) /* -W-4A */
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#define NV_097_SET_PROJECTION_MATRIX__SIZE_1 16 /* */
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#define NV_097_SET_PROJECTION_MATRIX_V 31:0 /* -WXUF */
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#define NV_097_SET_MODEL_VIEW_MATRIX0(i) (0x005c0480+(i)*4) /* -W-4A */
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#define NV_097_SET_MODEL_VIEW_MATRIX0__SIZE_1 16 /* */
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#define NV_097_SET_MODEL_VIEW_MATRIX0_V 31:0 /* -WXUF */
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#define NV_097_SET_MODEL_VIEW_MATRIX1(i) (0x005c04c0+(i)*4) /* -W-4A */
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#define NV_097_SET_MODEL_VIEW_MATRIX1__SIZE_1 16 /* */
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#define NV_097_SET_MODEL_VIEW_MATRIX1_V 31:0 /* -WXUF */
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#define NV_097_SET_MODEL_VIEW_MATRIX2(i) (0x005c0500+(i)*4) /* -W-4A */
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#define NV_097_SET_MODEL_VIEW_MATRIX2__SIZE_1 16 /* */
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#define NV_097_SET_MODEL_VIEW_MATRIX2_V 31:0 /* -WXUF */
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#define NV_097_SET_MODEL_VIEW_MATRIX3(i) (0x005c0540+(i)*4) /* -W-4A */
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#define NV_097_SET_MODEL_VIEW_MATRIX3__SIZE_1 16 /* */
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#define NV_097_SET_MODEL_VIEW_MATRIX3_V 31:0 /* -WXUF */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX0(i) (0x005c0580+(i)*4) /* -W-4A */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX0__SIZE_1 16 /* */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX0_V 31:0 /* -WXUF */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX1(i) (0x005c05c0+(i)*4) /* -W-4A */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX1__SIZE_1 16 /* */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX1_V 31:0 /* -WXUF */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX2(i) (0x005c0600+(i)*4) /* -W-4A */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX2__SIZE_1 16 /* */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX2_V 31:0 /* -WXUF */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX3(i) (0x005c0640+(i)*4) /* -W-4A */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX3__SIZE_1 16 /* */
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#define NV_097_SET_INVERSE_MODEL_VIEW_MATRIX3_V 31:0 /* -WXUF */
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#define NV_097_SET_COMPOSITE_MATRIX(i) (0x005c0680+(i)*4) /* -W-4A */
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#define NV_097_SET_COMPOSITE_MATRIX__SIZE_1 16 /* */
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#define NV_097_SET_COMPOSITE_MATRIX_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_MATRIX0(i) (0x005c06c0+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXTURE_MATRIX0__SIZE_1 16 /* */
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#define NV_097_SET_TEXTURE_MATRIX0_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_MATRIX1(i) (0x005c0700+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXTURE_MATRIX1__SIZE_1 16 /* */
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#define NV_097_SET_TEXTURE_MATRIX1_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_MATRIX2(i) (0x005c0740+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXTURE_MATRIX2__SIZE_1 16 /* */
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#define NV_097_SET_TEXTURE_MATRIX2_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_MATRIX3(i) (0x005c0780+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXTURE_MATRIX3__SIZE_1 16 /* */
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#define NV_097_SET_TEXTURE_MATRIX3_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_PLANE_S(i,j) (0x005c0840+(i)*64+(j)*4) /* -W-4A */
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#define NV_097_SET_TEXGEN_PLANE_S__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_S__SIZE_2 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_PLANE_T(i,j) (0x005c0850+(i)*64+(j)*4) /* -W-4A */
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#define NV_097_SET_TEXGEN_PLANE_T__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_T__SIZE_2 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_T_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_PLANE_R(i,j) (0x005c0860+(i)*64+(j)*4) /* -W-4A */
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#define NV_097_SET_TEXGEN_PLANE_R__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_R__SIZE_2 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_R_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXGEN_PLANE_Q(i,j) (0x005c0870+(i)*64+(j)*4) /* -W-4A */
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#define NV_097_SET_TEXGEN_PLANE_Q__SIZE_1 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_Q__SIZE_2 4 /* */
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#define NV_097_SET_TEXGEN_PLANE_Q_V 31:0 /* -WXUF */
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#define NV_097_SET_FOG_PARAMS(i) (0x005c09c0+(i)*4) /* -W-4A */
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#define NV_097_SET_FOG_PARAMS__SIZE_1 3 /* */
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#define NV_097_SET_FOG_PARAMS_V 31:0 /* -WXUF */
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#define NV_097_SET_FOG_PLANE(i) (0x005c09d0+(i)*4) /* -W-4A */
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#define NV_097_SET_FOG_PLANE__SIZE_1 4 /* */
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#define NV_097_SET_FOG_PLANE_V 31:0 /* -WXUF */
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#define NV_097_SET_SPECULAR_PARAMS(i) (0x005c09e0+(i)*4) /* -W-4A */
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#define NV_097_SET_SPECULAR_PARAMS__SIZE_1 6 /* */
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#define NV_097_SET_SPECULAR_PARAMS_V 31:0 /* -WXUF */
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#define NV_097_SET_BACK_SPECULAR_PARAMS(i) (0x005c1e28+(i)*4) /* -W-4A */
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#define NV_097_SET_BACK_SPECULAR_PARAMS__SIZE_1 6 /* */
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#define NV_097_SET_BACK_SPECULAR_PARAMS_V 31:0 /* -WXUF */
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#define NV_097_SET_SCENE_AMBIENT_COLOR(i) (0x005c0a10+(i)*4) /* -W-4A */
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#define NV_097_SET_SCENE_AMBIENT_COLOR__SIZE_1 3 /* */
|
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#define NV_097_SET_SCENE_AMBIENT_COLOR_V 31:0 /* -WXUF */
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#define NV_097_SET_VIEWPORT_SCALE(i) (0x005c0af0+(i)*4) /* -W-4A */
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#define NV_097_SET_VIEWPORT_SCALE__SIZE_1 4 /* */
|
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#define NV_097_SET_VIEWPORT_SCALE_V 31:0 /* -WXUF */
|
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#define NV_097_SET_VIEWPORT_OFFSET(i) (0x005c0a20+(i)*4) /* -W-4A */
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#define NV_097_SET_VIEWPORT_OFFSET__SIZE_1 4 /* */
|
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#define NV_097_SET_VIEWPORT_OFFSET_V 31:0 /* -WXUF */
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#define NV_097_SET_POINT_PARAMS(i) (0x005c0a30+(i)*4) /* -W-4A */
|
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#define NV_097_SET_POINT_PARAMS__SIZE_1 8 /* */
|
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#define NV_097_SET_POINT_PARAMS_V 31:0 /* -WXUF */
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#define NV_097_SET_EYE_POSITION(i) (0x005c0a50+(i)*4) /* -W-4A */
|
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#define NV_097_SET_EYE_POSITION__SIZE_1 4 /* */
|
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#define NV_097_SET_EYE_POSITION_V 31:0 /* -WXUF */
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#define NV_097_SET_BACK_LIGHT_AMBIENT_COLOR(i,j) (0x005c0c00+(i)*64+(j)*4) /* -W-4A */
|
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#define NV_097_SET_BACK_LIGHT_AMBIENT_COLOR__SIZE_1 8 /* */
|
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#define NV_097_SET_BACK_LIGHT_AMBIENT_COLOR__SIZE_2 3 /* */
|
|
#define NV_097_SET_BACK_LIGHT_AMBIENT_COLOR_V 31:0 /* -WXUF */
|
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#define NV_097_SET_BACK_LIGHT_DIFFUSE_COLOR(i,j) (0x005c0c0c+(i)*64+(j)*4) /* -W-4A */
|
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#define NV_097_SET_BACK_LIGHT_DIFFUSE_COLOR__SIZE_1 8 /* */
|
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#define NV_097_SET_BACK_LIGHT_DIFFUSE_COLOR__SIZE_2 3 /* */
|
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#define NV_097_SET_BACK_LIGHT_DIFFUSE_COLOR_V 31:0 /* -WXUF */
|
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#define NV_097_SET_BACK_LIGHT_SPECULAR_COLOR(i,j) (0x005c0c18+(i)*64+(j)*4) /* -W-4A */
|
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#define NV_097_SET_BACK_LIGHT_SPECULAR_COLOR__SIZE_1 8 /* */
|
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#define NV_097_SET_BACK_LIGHT_SPECULAR_COLOR__SIZE_2 3 /* */
|
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#define NV_097_SET_BACK_LIGHT_SPECULAR_COLOR_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LIGHT_AMBIENT_COLOR(i,j) (0x005c1000+(i)*128+(j)*4) /* -W-4A */
|
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#define NV_097_SET_LIGHT_AMBIENT_COLOR__SIZE_1 8 /* */
|
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#define NV_097_SET_LIGHT_AMBIENT_COLOR__SIZE_2 3 /* */
|
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#define NV_097_SET_LIGHT_AMBIENT_COLOR_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LIGHT_DIFFUSE_COLOR(i,j) (0x005c100c+(i)*128+(j)*4) /* -W-4A */
|
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#define NV_097_SET_LIGHT_DIFFUSE_COLOR__SIZE_1 8 /* */
|
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#define NV_097_SET_LIGHT_DIFFUSE_COLOR__SIZE_2 3 /* */
|
|
#define NV_097_SET_LIGHT_DIFFUSE_COLOR_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LIGHT_SPECULAR_COLOR(i,j) (0x005c1018+(i)*128+(j)*4) /* -W-4A */
|
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#define NV_097_SET_LIGHT_SPECULAR_COLOR__SIZE_1 8 /* */
|
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#define NV_097_SET_LIGHT_SPECULAR_COLOR__SIZE_2 3 /* */
|
|
#define NV_097_SET_LIGHT_SPECULAR_COLOR_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LIGHT_LOCAL_RANGE(i) (0x005c1024+(i)*128) /* -W-4A */
|
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#define NV_097_SET_LIGHT_LOCAL_RANGE__SIZE_1 8 /* */
|
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#define NV_097_SET_LIGHT_LOCAL_RANGE_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LIGHT_INFINITE_HALF_VECTOR(i,j) (0x005c1028+(i)*128+(j)*4) /* -W-4A */
|
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#define NV_097_SET_LIGHT_INFINITE_HALF_VECTOR__SIZE_1 8 /* */
|
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#define NV_097_SET_LIGHT_INFINITE_HALF_VECTOR__SIZE_2 3 /* */
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#define NV_097_SET_LIGHT_INFINITE_HALF_VECTOR_V 31:0 /* -WXUF */
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#define NV_097_SET_LIGHT_INFINITE_DIRECTION(i,j) (0x005c1034+(i)*128+(j)*4) /* -W-4A */
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#define NV_097_SET_LIGHT_INFINITE_DIRECTION__SIZE_1 8 /* */
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#define NV_097_SET_LIGHT_INFINITE_DIRECTION__SIZE_2 3 /* */
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#define NV_097_SET_LIGHT_INFINITE_DIRECTION_V 31:0 /* -WXUF */
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#define NV_097_SET_LIGHT_SPOT_FALLOFF(i,j) (0x005c1040+(i)*128+(j)*4) /* -W-4A */
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#define NV_097_SET_LIGHT_SPOT_FALLOFF__SIZE_1 8 /* */
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#define NV_097_SET_LIGHT_SPOT_FALLOFF__SIZE_2 3 /* */
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#define NV_097_SET_LIGHT_SPOT_FALLOFF_V 31:0 /* -WXUF */
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#define NV_097_SET_LIGHT_SPOT_DIRECTION(i,j) (0x005c104c+(i)*128+(j)*4) /* -W-4A */
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#define NV_097_SET_LIGHT_SPOT_DIRECTION__SIZE_1 8 /* */
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#define NV_097_SET_LIGHT_SPOT_DIRECTION__SIZE_2 4 /* */
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#define NV_097_SET_LIGHT_SPOT_DIRECTION_V 31:0 /* -WXUF */
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#define NV_097_SET_LIGHT_LOCAL_POSITION(i,j) (0x005c105c+(i)*128+(j)*4) /* -W-4A */
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#define NV_097_SET_LIGHT_LOCAL_POSITION__SIZE_1 8 /* */
|
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#define NV_097_SET_LIGHT_LOCAL_POSITION__SIZE_2 3 /* */
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#define NV_097_SET_LIGHT_LOCAL_POSITION_V 31:0 /* -WXUF */
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#define NV_097_SET_LIGHT_LOCAL_ATTENUATION(i,j) (0x005c1068+(i)*128+(j)*4) /* -W-4A */
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#define NV_097_SET_LIGHT_LOCAL_ATTENUATION__SIZE_1 8 /* */
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#define NV_097_SET_LIGHT_LOCAL_ATTENUATION__SIZE_2 3 /* */
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#define NV_097_SET_LIGHT_LOCAL_ATTENUATION_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX3F(i) (0x005c1500+(i)*4) /* -W-4A */
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#define NV_097_SET_VERTEX3F__SIZE_1 3 /* */
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#define NV_097_SET_VERTEX3F_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX4F(i) (0x005c1518+(i)*4) /* -W-4A */
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#define NV_097_SET_VERTEX4F__SIZE_1 4 /* */
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#define NV_097_SET_VERTEX4F_V 31:0 /* -WXUF */
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#define NV_097_SET_VERTEX4S(i) (0x005c1528+(i)*4) /* -W-4A */
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#define NV_097_SET_VERTEX4S__SIZE_1 2 /* */
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#define NV_097_SET_VERTEX4S_V 31:0 /* -WXUF */
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#define NV_097_SET_NORMAL3F(i) (0x005c1530+(i)*4) /* -W-4A */
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#define NV_097_SET_NORMAL3F__SIZE_1 3 /* */
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#define NV_097_SET_NORMAL3F_V 31:0 /* -WXUF */
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#define NV_097_SET_NORMAL3S(i) (0x005c1540+(i)*4) /* -W-4A */
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#define NV_097_SET_NORMAL3S__SIZE_1 2 /* */
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#define NV_097_SET_NORMAL3S_V 31:0 /* -WXUF */
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#define NV_097_SET_DIFFUSE_COLOR4F(i) (0x005c1550+(i)*4) /* -W-4A */
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#define NV_097_SET_DIFFUSE_COLOR4F__SIZE_1 4 /* */
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#define NV_097_SET_DIFFUSE_COLOR4F_V 31:0 /* -WXUF */
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#define NV_097_SET_DIFFUSE_COLOR3F(i) (0x005c1560+(i)*4) /* -W-4A */
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#define NV_097_SET_DIFFUSE_COLOR3F__SIZE_1 3 /* */
|
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#define NV_097_SET_DIFFUSE_COLOR3F_V 31:0 /* -WXUF */
|
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#define NV_097_SET_DIFFUSE_COLOR4UB 0x005c156c /* -W-4R */
|
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#define NV_097_SET_DIFFUSE_COLOR4UB_V 31:0 /* -WXUF */
|
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#define NV_097_SET_SPECULAR_COLOR4F(i) (0x005c1570+(i)*4) /* -W-4A */
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#define NV_097_SET_SPECULAR_COLOR4F__SIZE_1 4 /* */
|
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#define NV_097_SET_SPECULAR_COLOR4F_V 31:0 /* -WXUF */
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#define NV_097_SET_SPECULAR_COLOR3F(i) (0x005c1580+(i)*4) /* -W-4A */
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#define NV_097_SET_SPECULAR_COLOR3F__SIZE_1 3 /* */
|
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#define NV_097_SET_SPECULAR_COLOR3F_V 31:0 /* -WXUF */
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#define NV_097_SET_SPECULAR_COLOR4UB 0x005c158c /* -W-4R */
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#define NV_097_SET_SPECULAR_COLOR4UB_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD0_2F(i) (0x005c1590+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD0_2F__SIZE_1 2 /* */
|
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#define NV_097_SET_TEXCOORD0_2F_V 31:0 /* -WXUF */
|
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#define NV_097_SET_TEXCOORD0_2S 0x005c1598 /* -W-4R */
|
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#define NV_097_SET_TEXCOORD0_2S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD0_4F(i) (0x005c15a0+(i)*4) /* -W-4A */
|
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#define NV_097_SET_TEXCOORD0_4F__SIZE_1 4 /* */
|
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#define NV_097_SET_TEXCOORD0_4F_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD0_4S(i) (0x005c15b0+(i)*4) /* -W-4A */
|
|
#define NV_097_SET_TEXCOORD0_4S__SIZE_1 2 /* */
|
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#define NV_097_SET_TEXCOORD0_4S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD1_2F(i) (0x005c15b8+(i)*4) /* -W-4A */
|
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#define NV_097_SET_TEXCOORD1_2F__SIZE_1 2 /* */
|
|
#define NV_097_SET_TEXCOORD1_2F_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD1_2S 0x005c15c0 /* -W-4R */
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#define NV_097_SET_TEXCOORD1_2S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD1_4F(i) (0x005c15c8+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD1_4F__SIZE_1 4 /* */
|
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#define NV_097_SET_TEXCOORD1_4F_V 31:0 /* -WXUF */
|
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#define NV_097_SET_TEXCOORD1_4S(i) (0x005c15d8+(i)*4) /* -W-4A */
|
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#define NV_097_SET_TEXCOORD1_4S__SIZE_1 2 /* */
|
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#define NV_097_SET_TEXCOORD1_4S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD2_2F(i) (0x005c15e0+(i)*4) /* -W-4A */
|
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#define NV_097_SET_TEXCOORD2_2F__SIZE_1 2 /* */
|
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#define NV_097_SET_TEXCOORD2_2F_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD2_2S 0x005c15e8 /* -W-4R */
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#define NV_097_SET_TEXCOORD2_2S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD2_4F(i) (0x005c15f0+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD2_4F__SIZE_1 4 /* */
|
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#define NV_097_SET_TEXCOORD2_4F_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD2_4S(i) (0x005c1600+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD2_4S__SIZE_1 2 /* */
|
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#define NV_097_SET_TEXCOORD2_4S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD3_2F(i) (0x005c1608+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD3_2F__SIZE_1 2 /* */
|
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#define NV_097_SET_TEXCOORD3_2F_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD3_2S 0x005c1610 /* -W-4R */
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#define NV_097_SET_TEXCOORD3_2S_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD3_4F(i) (0x005c1620+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD3_4F__SIZE_1 4 /* */
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#define NV_097_SET_TEXCOORD3_4F_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXCOORD3_4S(i) (0x005c1630+(i)*4) /* -W-4A */
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#define NV_097_SET_TEXCOORD3_4S__SIZE_1 2 /* */
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#define NV_097_SET_TEXCOORD3_4S_V 31:0 /* -WXUF */
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#define NV_097_SET_FOG1F 0x005c1698 /* -W-4R */
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#define NV_097_SET_FOG1F_V 31:0 /* -WXUF */
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#define NV_097_SET_WEIGHT1F 0x005c169c /* -W-4R */
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#define NV_097_SET_WEIGHT1F_V 31:0 /* -WXUF */
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#define NV_097_SET_WEIGHT2F(i) (0x005c16a0+(i)*4) /* -W-4A */
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#define NV_097_SET_WEIGHT2F__SIZE_1 2 /* */
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#define NV_097_SET_WEIGHT2F_V 31:0 /* -WXUF */
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#define NV_097_SET_WEIGHT3F(i) (0x005c16b0+(i)*4) /* -W-4A */
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#define NV_097_SET_WEIGHT3F__SIZE_1 3 /* */
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#define NV_097_SET_WEIGHT3F_V 31:0 /* -WXUF */
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#define NV_097_SET_WEIGHT4F(i) (0x005c16c0+(i)*4) /* -W-4A */
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#define NV_097_SET_WEIGHT4F__SIZE_1 4 /* */
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#define NV_097_SET_WEIGHT4F_V 31:0 /* -WXUF */
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#define NV_097_SET_EDGE_FLAG 0x005c16bc /* -W-4R */
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#define NV_097_SET_EDGE_FLAG_V 31:0 /* -WXUF */
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#define NV_097_SET_EDGE_FLAG_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_EDGE_FLAG_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TRANSFORM_FIXED_CONST0(i) (0x005c16e0+(i)*4) /* -W-4A */
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#define NV_097_SET_TRANSFORM_FIXED_CONST0__SIZE_1 4 /* */
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#define NV_097_SET_TRANSFORM_FIXED_CONST0_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_FIXED_CONST1(i) (0x005c16f0+(i)*4) /* -W-4A */
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#define NV_097_SET_TRANSFORM_FIXED_CONST1__SIZE_1 4 /* */
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#define NV_097_SET_TRANSFORM_FIXED_CONST1_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_FIXED_CONST2(i) (0x005c1700+(i)*4) /* -W-4A */
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#define NV_097_SET_TRANSFORM_FIXED_CONST2__SIZE_1 4 /* */
|
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#define NV_097_SET_TRANSFORM_FIXED_CONST2_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_FIXED_CONST3(i) (0x005c16d0+(i)*4) /* -W-4A */
|
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#define NV_097_SET_TRANSFORM_FIXED_CONST3__SIZE_1 4 /* */
|
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#define NV_097_SET_TRANSFORM_FIXED_CONST3_V 31:0 /* -WXUF */
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#define NV_097_SET_TLCONST_ZERO(i) (0x005c17d4+(i)*4) /* -W-4A */
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#define NV_097_SET_TLCONST_ZERO__SIZE_1 3 /* */
|
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#define NV_097_SET_TLCONST_ZERO_V 31:0 /* -WXUF */
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#define NV_097_SET_EYE_DIRECTION(i) (0x005c17e0+(i)*4) /* -W-4A */
|
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#define NV_097_SET_EYE_DIRECTION__SIZE_1 3 /* */
|
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#define NV_097_SET_EYE_DIRECTION_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LINEAR_FOG_CONST(i) (0x005c17ec+(i)*4) /* -W-4A */
|
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#define NV_097_SET_LINEAR_FOG_CONST__SIZE_1 3 /* */
|
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#define NV_097_SET_LINEAR_FOG_CONST_V 31:0 /* -WXUF */
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#define NV_097_INVALIDATE_VERTEX_CACHE_FILE 0x005c1710 /* -W-4R */
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#define NV_097_INVALIDATE_VERTEX_FILE 0x005c1714 /* -W-4R */
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#define NV_097_TL_NOP 0x005c1718 /* -W-4R */
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#define NV_097_TL_SYNC 0x005c171c /* -W-4R */
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#define NV_097_SET_VERTEX_DATA_ARRAY_OFFSET(i) (0x005c1720+(i)*4) /* -W-4A */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_OFFSET__SIZE_1 16 /* */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_OFFSET_CONTEXT_DMA 31:31 /* -WXUF */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_OFFSET_CONTEXT_DMA_VERTEX_A 0x00000000 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_OFFSET_CONTEXT_DMA_VERTEX_B 0x00000001 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_OFFSET_OFFSET 30:0 /* -WXUF */
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT(i) (0x005c1760+(i)*4) /* -W-4A */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT__SIZE_1 16 /* */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_STRIDE 31:8 /* -WXUF */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE 7:4 /* -WXUF */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE_DISABLED 0x00000000 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE_1 0x00000001 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE_2 0x00000002 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE_3 0x00000003 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE_4 0x00000004 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_SIZE_3W 0x00000007 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE 3:0 /* -WXUF */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_UB_D3D 0x00000000 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_S1 0x00000001 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_F 0x00000002 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_UB_OGL 0x00000004 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_S32K 0x00000005 /* -W--V */
|
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#define NV_097_SET_VERTEX_DATA_ARRAY_FORMAT_TYPE_CMP 0x00000006 /* -W--V */
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#define NV_097_SET_LOGIC_OP_ENABLE 0x005c17bc /* -W-4R */
|
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#define NV_097_SET_LOGIC_OP_ENABLE_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LOGIC_OP_ENABLE_V_FALSE 0x00000000 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_ENABLE_V_TRUE 0x00000001 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP 0x005c17c0 /* -W-4R */
|
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#define NV_097_SET_LOGIC_OP_V 31:0 /* -WXUF */
|
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#define NV_097_SET_LOGIC_OP_V_CLEAR 0x00001500 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_AND 0x00001501 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_AND_REVERSE 0x00001502 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_COPY 0x00001503 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_AND_INVERTED 0x00001504 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_NOOP 0x00001505 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_XOR 0x00001506 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_OR 0x00001507 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_NOR 0x00001508 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_EQUIV 0x00001509 /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_INVERT 0x0000150A /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_OR_REVERSE 0x0000150B /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_COPY_INVERTED 0x0000150C /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_OR_INVERTED 0x0000150D /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_NAND 0x0000150E /* -W--V */
|
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#define NV_097_SET_LOGIC_OP_V_SET 0x0000150F /* -W--V */
|
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#define NV_097_SET_BEGIN_END 0x005c17fc /* -W-4R */
|
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#define NV_097_SET_BEGIN_END_OP 31:0 /* -WXUF */
|
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#define NV_097_SET_BEGIN_END_OP_END 0x00000000 /* -W--V */
|
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#define NV_097_SET_BEGIN_END_OP_POINTS 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_LINES 0x00000002 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_LINE_LOOP 0x00000003 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_LINE_STRIP 0x00000004 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_TRIANGLES 0x00000005 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_TRIANGLE_STRIP 0x00000006 /* -W--V */
|
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#define NV_097_SET_BEGIN_END_OP_TRIANGLE_FAN 0x00000007 /* -W--V */
|
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#define NV_097_SET_BEGIN_END_OP_QUADS 0x00000008 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_QUAD_STRIP 0x00000009 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_OP_POLYGON 0x0000000A /* -W--V */
|
|
#define NV_097_ARRAY_ELEMENT16 0x005c1800 /* -W-4R */
|
|
#define NV_097_ARRAY_ELEMENT16_VERTEX0 15:0 /* -WXUF */
|
|
#define NV_097_ARRAY_ELEMENT16_VERTEX1 31:16 /* -WXUF */
|
|
#define NV_097_ARRAY_ELEMENT32 0x005c1808 /* -W-4R */
|
|
#define NV_097_ARRAY_ELEMENT32_V 31:0 /* -WXUF */
|
|
#define NV_097_DRAW_ARRAYS 0x005c1810 /* -W-4R */
|
|
#define NV_097_DRAW_ARRAYS_COUNT 31:24 /* -WXUF */
|
|
#define NV_097_DRAW_ARRAYS_START_INDEX 23:0 /* -WXUF */
|
|
#define NV_097_INLINE_VERTEX_REUSE 0x005c1828 /* -W-4R */
|
|
#define NV_097_INLINE_VERTEX_REUSE_V 31:0 /* -WXUF */
|
|
#define NV_097_INLINE_ARRAY 0x005c1818 /* -W-4R */
|
|
#define NV_097_INLINE_ARRAY_V 31:0 /* -WXUF */
|
|
#define NV_097_SET_TEXTURE_OFFSET(i) (0x005c1b00+(i)*64) /* -W-4A */
|
|
#define NV_097_SET_TEXTURE_OFFSET__SIZE_1 4 /* */
|
|
#define NV_097_SET_TEXTURE_OFFSET_V 31:0 /* -WXUF */
|
|
#define NV_097_SET_TEXTURE_FORMAT(i) (0x005c1b04+(i)*64) /* -W-4A */
|
|
#define NV_097_SET_TEXTURE_FORMAT__SIZE_1 4 /* */
|
|
#define NV_097_SET_TEXTURE_FORMAT_CONTEXT_DMA 1:0 /* -WXUF */
|
|
#define NV_097_SET_TEXTURE_FORMAT_CONTEXT_DMA_A 0x00000001 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_CONTEXT_DMA_B 0x00000002 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE 2:2 /* -WXUF */
|
|
#define NV_097_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE_FALSE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_CUBEMAP_ENABLE_TRUE 0x00000001 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_BORDER_SOURCE 3:3 /* -WXUF */
|
|
#define NV_097_SET_TEXTURE_FORMAT_BORDER_SOURCE_TEXTURE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_BORDER_SOURCE_COLOR 0x00000001 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_DIMENSIONALITY 7:4 /* -WXUF */
|
|
#define NV_097_SET_TEXTURE_FORMAT_DIMENSIONALITY_ONE 0x00000001 /* -W--V */
|
|
#define NV_097_SET_TEXTURE_FORMAT_DIMENSIONALITY_TWO 0x00000002 /* -W--V */
|
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#define NV_097_SET_TEXTURE_FORMAT_DIMENSIONALITY_THREE 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR 15:8 /* -WXUF */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_Y8 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_AY8 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_A1R5G5B5 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_X1R5G5B5 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_A4R4G4B4 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_R5G6B5 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_A8R8G8B8 0x00000006 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_X8R8G8B8 0x00000007 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_I8_A8R8G8B8 0x0000000B /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_L_DXT1_A1R5G5B5 0x0000000C /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_L_DXT23_A8R8G8B8 0x0000000E /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_L_DXT45_A8R8G8B8 0x0000000F /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A1R5G5B5 0x00000010 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R5G6B5 0x00000011 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8R8G8B8 0x00000012 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_Y8 0x00000013 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_SY8 0x00000014 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X7SY9 0x00000015 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R8B8 0x00000016 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_G8B8 0x00000017 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_SG8SB8 0x00000018 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_A8 0x00000019 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_A8Y8 0x0000001A /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_AY8 0x0000001B /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X1R5G5B5 0x0000001C /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A4R4G4B4 0x0000001D /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_X8R8G8B8 0x0000001E /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8 0x0000001F /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8Y8 0x00000020 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_CR8YB8CB8YA8 0x00000024 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_YB8CR8YA8CB8 0x00000025 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8CR8CB8Y8 0x00000026 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_R6G5B5 0x00000027 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_G8B8 0x00000028 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_R8B8 0x00000029 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_X8_Y24_FIXED 0x0000002A /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_X8_Y24_FLOAT 0x0000002B /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_Y16_FIXED 0x0000002C /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_DEPTH_Y16_FLOAT 0x0000002D /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_X8_Y24_FIXED 0x0000002E /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_X8_Y24_FLOAT 0x0000002F /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_Y16_FIXED 0x00000030 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_DEPTH_Y16_FLOAT 0x00000031 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_Y16 0x00000032 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_YB_16_YA_16 0x00000033 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LC_IMAGE_A4V6YB6A4U6YA6 0x00000034 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_Y16 0x00000035 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_YB16YA16 0x00000036 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R6G5B5 0x00000037 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_R5G5B5A1 0x00000038 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_R4G4B4A4 0x00000039 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_A8B8G8R8 0x0000003A /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_B8G8R8A8 0x0000003B /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_SZ_R8G8B8A8 0x0000003C /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R5G5B5A1 0x0000003D /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R4G4B4A4 0x0000003E /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_A8B8G8R8 0x0000003F /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_B8G8R8A8 0x00000040 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_COLOR_LU_IMAGE_R8G8B8A8 0x00000041 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_MIPMAP_LEVELS 19:16 /* -WXUF */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U 23:20 /* -WXUF */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_1 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_2 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_4 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_8 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_16 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_32 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_64 0x00000006 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_128 0x00000007 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_256 0x00000008 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_512 0x00000009 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_1024 0x0000000A /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_2048 0x0000000B /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_U_4096 0x0000000C /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V 27:24 /* -WXUF */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_1 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_2 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_4 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_8 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_16 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_32 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_64 0x00000006 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_128 0x00000007 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_256 0x00000008 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_512 0x00000009 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_1024 0x0000000A /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_2048 0x0000000B /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_V_4096 0x0000000C /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P 31:28 /* -WXUF */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_1 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_2 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_4 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_8 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_16 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_32 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_64 0x00000006 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_128 0x00000007 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_256 0x00000008 /* -W--V */
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#define NV_097_SET_TEXTURE_FORMAT_BASE_SIZE_P_512 0x00000009 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS(i) (0x005c1b08+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_ADDRESS__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_ADDRESS_U 3:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_U_WRAP 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_U_MIRROR 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_U_CLAMP_TO_EDGE 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_U_BORDER 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_U_CLAMP_OGL 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_U 7:4 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_U_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_U_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_V 11:8 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_V_WRAP 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_V_MIRROR 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_V_CLAMP_TO_EDGE 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_V_BORDER 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_V_CLAMP_OGL 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_V 15:12 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_P 19:16 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_P_WRAP 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_P_MIRROR 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_P_CLAMP_TO_EDGE 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_P_BORDER 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_P_CLAMP_OGL 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_P 23:20 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_P_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_P_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_Q 31:24 /* -WXUF */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_Q_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_ADDRESS_CYLWRAP_Q_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0(i) (0x005c1b0c+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_CONTROL0__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_CONTROL0_ENABLE 31:30 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_MIN_LOD_CLAMP 29:18 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_MAX_LOD_CLAMP 17:6 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO 5:4 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO_0 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO_1 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO_2 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_LOG_MAX_ANISO_3 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_IMAGE_FIELD_ENABLE 3:3 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_IMAGE_FIELD_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_IMAGE_FIELD_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_ALPHA_KILL_ENABLE 2:2 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_ALPHA_KILL_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_ALPHA_KILL_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION 1:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_ALPHA 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_RGBA 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL0_COLOR_KEY_OPERATION_KILL 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_CONTROL1(i) (0x005c1b10+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_CONTROL1__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_CONTROL1_IMAGE_PITCH 31:16 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER(i) (0x005c1b14+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_FILTER__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_FILTER_MIPMAP_LOD_BIAS 12:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_CONVOLUTION_KERNEL 15:13 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_CONVOLUTION_KERNEL_QUINCUNX 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_CONVOLUTION_KERNEL_GAUSSIAN_3 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN 23:16 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_MIN_BOX_LOD0 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN_TENT_LOD0 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN_BOX_NEARESTLOD 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN_TENT_NEARESTLOD 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN_BOX_TENT_LOD 0x00000005 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN_TENT_TENT_LOD 0x00000006 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MIN_CONVOLUTION_2D_LOD0 0x00000007 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MAG 27:24 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_MAG_BOX_LOD0 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MAG_TENT_LOD0 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_MAG_CONVOLUTION_2D_LOD0 0x00000004 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_ASIGNED 28:28 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_ASIGNED_BIT_DISABLED 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_ASIGNED_BIT_ENABLED 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_RSIGNED 29:29 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_RSIGNED_BIT_DISABLED 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_RSIGNED_BIT_ENABLED 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_GSIGNED 30:30 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_GSIGNED_BIT_DISABLED 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_GSIGNED_BIT_ENABLED 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_BSIGNED 31:31 /* -WXUF */
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#define NV_097_SET_TEXTURE_FILTER_BSIGNED_BIT_DISABLED 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_FILTER_BSIGNED_BIT_ENABLED 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_IMAGE_RECT(i) (0x005c1b1c+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_IMAGE_RECT__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_IMAGE_RECT_WIDTH 31:16 /* -WXUF */
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#define NV_097_SET_TEXTURE_IMAGE_RECT_HEIGHT 15:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_PALETTE(i) (0x005c1b20+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_PALETTE__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_PALETTE_CONTEXT_DMA 1:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_PALETTE_CONTEXT_DMA_A 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_PALETTE_CONTEXT_DMA_B 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_PALETTE_LENGTH 5:2 /* -WXUF */
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#define NV_097_SET_TEXTURE_PALETTE_LENGTH_256 0x00000000 /* -W--V */
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#define NV_097_SET_TEXTURE_PALETTE_LENGTH_128 0x00000001 /* -W--V */
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#define NV_097_SET_TEXTURE_PALETTE_LENGTH_64 0x00000002 /* -W--V */
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#define NV_097_SET_TEXTURE_PALETTE_LENGTH_32 0x00000003 /* -W--V */
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#define NV_097_SET_TEXTURE_PALETTE_OFFSET 31:6 /* -WXUF */
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#define NV_097_SET_TEXTURE_BORDER_COLOR(i) (0x005c1b24+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_BORDER_COLOR__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_BORDER_COLOR_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT00(i) (0x005c1b28+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT00__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT00_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT01(i) (0x005c1b2c+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT01__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT01_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT11(i) (0x005c1b30+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT11__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT11_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT10(i) (0x005c1b34+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT10__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_MAT10_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_SCALE(i) (0x005c1b38+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_SCALE__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_SCALE_V 31:0 /* -WXUF */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_OFFSET(i) (0x005c1b3c+(i)*64) /* -W-4A */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_OFFSET__SIZE_1 4 /* */
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#define NV_097_SET_TEXTURE_SET_BUMP_ENV_OFFSET_V 31:0 /* -WXUF */
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#define NV_097_PARK_ATTRIBUTE 0x005c1d64 /* -W-4R */
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#define NV_097_UNPARK_ATTRIBUTE 0x005c1d68 /* -W-4R */
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#define NV_097_SET_SEMAPHORE_OFFSET 0x005c1d6c /* -W-4R */
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#define NV_097_SET_SEMAPHORE_OFFSET_V 31:0 /* -WXUF */
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#define NV_097_BACK_END_WRITE_SEMAPHORE_RELEASE 0x005c1d70 /* -W-4R */
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#define NV_097_BACK_END_WRITE_SEMAPHORE_RELEASE_V 31:0 /* -WXUF */
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#define NV_097_TEXTURE_READ_SEMAPHORE_RELEASE 0x005c1d74 /* -W-4R */
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#define NV_097_TEXTURE_READ_SEMAPHORE_RELEASE_V 31:0 /* -WXUF */
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#define NV_097_SET_ZMIN_MAX_CONTROL 0x005c1d78 /* -W-4R */
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#define NV_097_SET_ZMIN_MAX_CONTROL_CULL_NEAR_FAR_EN 3:0 /* -WXUF */
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#define NV_097_SET_ZMIN_MAX_CONTROL_CULL_NEAR_FAR_EN_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_ZMIN_MAX_CONTROL_CULL_NEAR_FAR_EN_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_ZMIN_MAX_CONTROL_ZCLAMP_EN 7:4 /* -WXUF */
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#define NV_097_SET_ZMIN_MAX_CONTROL_ZCLAMP_EN_CULL 0x00000000 /* -W--V */
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#define NV_097_SET_ZMIN_MAX_CONTROL_ZCLAMP_EN_CLAMP 0x00000001 /* -W--V */
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#define NV_097_SET_ZMIN_MAX_CONTROL_CULL_IGNORE_W 11:8 /* -WXUF */
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#define NV_097_SET_ZMIN_MAX_CONTROL_CULL_IGNORE_W_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_ZMIN_MAX_CONTROL_CULL_IGNORE_W_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL 0x005c1d7c /* -W-4R */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ENABLE 3:0 /* -WXUF */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ALPHA_TO_COVERAGE 7:4 /* -WXUF */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ALPHA_TO_COVERAGE_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ALPHA_TO_COVERAGE_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ALPHA_TO_ONE 11:8 /* -WXUF */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ALPHA_TO_ONE_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_ALPHA_TO_ONE_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_ANTI_ALIASING_CONTROL_SAMPLE_MASK 31:16 /* -WXUF */
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#define NV_097_SET_DXT_DITHER_ENABLE_SW 0x005c1d88 /* -W-4R */
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#define NV_097_SET_DXT_DITHER_ENABLE_SW_V 31:0 /* -WXUF */
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#define NV_097_SET_DXT_DITHER_ENABLE_SW_V_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_DXT_DITHER_ENABLE_SW_V_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_COMPRESS_ZBUFFER_EN 0x005c1d80 /* -W-4R */
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#define NV_097_SET_COMPRESS_ZBUFFER_EN_V 31:0 /* -WXUF */
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#define NV_097_SET_COMPRESS_ZBUFFER_EN_V_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COMPRESS_ZBUFFER_EN_V_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN 0x005c1d84 /* -W-4R */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN_OCCLUDE_ZEN 0:0 /* -WXUF */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN_OCCLUDE_ZEN_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN_OCCLUDE_ZEN_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN_OCCLUDE_STENCIL_EN 1:1 /* -WXUF */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN_OCCLUDE_STENCIL_EN_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_OCCLUDE_ZSTENCIL_EN_OCCLUDE_STENCIL_EN_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT 0x005c0208 /* -W-4R */
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#define NV_097_SET_SURFACE_FORMAT_COLOR 3:0 /* -WXUF */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x00000001 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x00000002 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_R5G6B5 0x00000003 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x00000004 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x00000005 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000006 /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000007 /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_A8R8G8B8 0x00000008 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_B8 0x00000009 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_COLOR_LE_G8B8 0x0000000A /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_ZETA 7:4 /* -WXUF */
|
|
#define NV_097_SET_SURFACE_FORMAT_ZETA_Z16 0x00000001 /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_ZETA_Z24S8 0x00000002 /* -W--V */
|
|
#define NV_097_SET_SURFACE_FORMAT_TYPE 11:8 /* -WXUF */
|
|
#define NV_097_SET_SURFACE_FORMAT_TYPE_PITCH 0x00000001 /* -W--V */
|
|
#define NV_097_SET_SURFACE_FORMAT_TYPE_SWIZZLE 0x00000002 /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_ANTI_ALIASING 15:12 /* -WXUF */
|
|
#define NV_097_SET_SURFACE_FORMAT_ANTI_ALIASING_CENTER_1 0x00000000 /* -W--V */
|
|
#define NV_097_SET_SURFACE_FORMAT_ANTI_ALIASING_CENTER_CORNER_2 0x00000001 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_ANTI_ALIASING_SQUARE_OFFSET_4 0x00000002 /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_WIDTH 23:16 /* -WXUF */
|
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_1 0x00000000 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_2 0x00000001 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_4 0x00000002 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_8 0x00000003 /* -W--V */
|
|
#define NV_097_SET_SURFACE_FORMAT_WIDTH_16 0x00000004 /* -W--V */
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|
#define NV_097_SET_SURFACE_FORMAT_WIDTH_32 0x00000005 /* -W--V */
|
|
#define NV_097_SET_SURFACE_FORMAT_WIDTH_64 0x00000006 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_128 0x00000007 /* -W--V */
|
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_256 0x00000008 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_512 0x00000009 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_1024 0x0000000A /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_2048 0x0000000B /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_WIDTH_4096 0x0000000C /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT 31:24 /* -WXUF */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_1 0x00000000 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_2 0x00000001 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_4 0x00000002 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_8 0x00000003 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_16 0x00000004 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_32 0x00000005 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_64 0x00000006 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_128 0x00000007 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_256 0x00000008 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_512 0x00000009 /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_1024 0x0000000A /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_2048 0x0000000B /* -W--V */
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#define NV_097_SET_SURFACE_FORMAT_HEIGHT_4096 0x0000000C /* -W--V */
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#define NV_097_SET_ZSTENCIL_CLEAR_VALUE 0x005c1d8c /* -W-4R */
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#define NV_097_SET_ZSTENCIL_CLEAR_VALUE_V 31:0 /* -WXUF */
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#define NV_097_SET_COLOR_CLEAR_VALUE 0x005c1d90 /* -W-4R */
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#define NV_097_SET_COLOR_CLEAR_VALUE_V 31:0 /* -WXUF */
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#define NV_097_CLEAR_SURFACE 0x005c1d94 /* -W-4R */
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#define NV_097_CLEAR_SURFACE_Z 0:0 /* -WXUF */
|
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#define NV_097_CLEAR_SURFACE_Z_DISABLE 0x00000000 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_Z_ENABLE 0x00000001 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_STENCIL 1:1 /* -WXUF */
|
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#define NV_097_CLEAR_SURFACE_STENCIL_DISABLE 0x00000000 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_STENCIL_ENABLE 0x00000001 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_R 4:4 /* -WXUF */
|
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#define NV_097_CLEAR_SURFACE_R_DISABLE 0x00000000 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_R_ENABLE 0x00000001 /* -W--V */
|
|
#define NV_097_CLEAR_SURFACE_G 5:5 /* -WXUF */
|
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#define NV_097_CLEAR_SURFACE_G_DISABLE 0x00000000 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_G_ENABLE 0x00000001 /* -W--V */
|
|
#define NV_097_CLEAR_SURFACE_B 6:6 /* -WXUF */
|
|
#define NV_097_CLEAR_SURFACE_B_DISABLE 0x00000000 /* -W--V */
|
|
#define NV_097_CLEAR_SURFACE_B_ENABLE 0x00000001 /* -W--V */
|
|
#define NV_097_CLEAR_SURFACE_A 7:7 /* -WXUF */
|
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#define NV_097_CLEAR_SURFACE_A_DISABLE 0x00000000 /* -W--V */
|
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#define NV_097_CLEAR_SURFACE_A_ENABLE 0x00000001 /* -W--V */
|
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#define NV_097_SET_CLEAR_RECT_HORIZONTAL 0x005c1d98 /* -W-4R */
|
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#define NV_097_SET_CLEAR_RECT_HORIZONTAL_XMIN 15:0 /* -WXUF */
|
|
#define NV_097_SET_CLEAR_RECT_HORIZONTAL_XMAX 31:16 /* -WXUF */
|
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#define NV_097_SET_CLEAR_RECT_VERTICAL 0x005c1d9c /* -W-4R */
|
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#define NV_097_SET_CLEAR_RECT_VERTICAL_YMIN 15:0 /* -WXUF */
|
|
#define NV_097_SET_CLEAR_RECT_VERTICAL_YMAX 31:16 /* -WXUF */
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#define NV_097_SET_BEGIN_PATCH0 0x005c1de0 /* -W-4R */
|
|
#define NV_097_SET_BEGIN_PATCH0_POSITION_DEGREE 3:0 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH0_PARAM1_DEGREE 7:4 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH0_PARAM2_DEGREE 11:8 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH0_PARAM3_DEGREE 15:12 /* -WXUF */
|
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#define NV_097_SET_BEGIN_PATCH0_PARAM4_DEGREE 19:16 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH0_PARAM5_DEGREE 23:20 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH0_PARAM6_DEGREE 27:24 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH0_PARAM7_DEGREE 31:28 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1 0x005c1de4 /* -W-4R */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM8_DEGREE 3:0 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM9_DEGREE 7:4 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM10_DEGREE 11:8 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM11_DEGREE 15:12 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM12_DEGREE 19:16 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM13_DEGREE 23:20 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM14_DEGREE 27:24 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH1_PARAM15_DEGREE 31:28 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2 0x005c1de8 /* -W-4R */
|
|
#define NV_097_SET_BEGIN_PATCH2_SWATCH_ROWS 7:0 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2_SWATCH_COLS 15:8 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2_SWATCH_SIZE 20:16 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2_PARTIAL_SWATCH_WIDTH 25:21 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2_PARTIAL_SWATCH_HEIGHT 30:26 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2_PATCH_TYPE 31:31 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH2_PATCH_TYPE_SQUARE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3 0x005c1dec /* -W-4R */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS 2:0 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS_NONE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS_FIRST 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS_LAST 0x00000002 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS_FIRST_AND_LAST 0x00000003 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS_REV_FIRST 0x00000005 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_ROW_TRNS_REV_LAST 0x00000006 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS 5:3 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS_NONE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS_FIRST 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS_LAST 0x00000002 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS_FIRST_AND_LAST 0x00000003 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS_REV_FIRST 0x00000005 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_COL_TRNS_REV_LAST 0x00000006 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_POSITION_GUARD_CURVE_DEGREE 9:6 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH3_NORMAL_GUARD_CURVE_DEGREE 13:10 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH3_PRIMITIVE 15:14 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH3_PRIMITIVE_TRI_STRIP 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_PRIMITIVE_REVERSED_TRI_STRIP 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_PRIMITIVE_BW_TRI_STRIP 0x00000002 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_PRIMITIVE_BW_REVERSED_TRI_STRIP 0x00000003 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_TESSELATION 16:16 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_PATCH3_TESSELATION_ADAPTIVE_STITCH 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_TESSELATION_FIXED_STITCH 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_PATCH3_NUM_COEFFS 31:24 /* -WXUF */
|
|
#define NV_097_SET_END_PATCH 0x005c1df0 /* -W-4R */
|
|
#define NV_097_SET_BEGIN_END_SWATCH 0x005c1df4 /* -W-4R */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SWATCH_CMD 3:0 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SWATCH_CMD_END 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SWATCH_CMD_BEGIN 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_NEW_SWATH 7:4 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_NEW_SWATH_CONTINUE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_NEW_SWATH_NEW 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SKIP_FIRST_ROW 11:8 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SKIP_FIRST_ROW_FALSE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SKIP_FIRST_ROW_TRUE 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SKIP_FIRST_COL 15:12 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SKIP_FIRST_COL_FALSE 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SKIP_FIRST_COL_TRUE 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SHORT_SWATCH 19:16 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SHORT_SWATCH_FULL_HEIGHT 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_SHORT_SWATCH_PARTIAL_HEIGHT 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_NARROW_SWATCH 31:20 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_NARROW_SWATCH_FULL_WIDTH 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_SWATCH_NARROW_SWATCH_PARTIAL_WIDTH 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_CURVE 0x005c1df8 /* -W-4R */
|
|
#define NV_097_SET_BEGIN_END_CURVE_CMD 3:0 /* -WXUF */
|
|
#define NV_097_SET_BEGIN_END_CURVE_CMD_END_CURVE_DATA 0x00000000 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_CURVE_CMD_STRIP_CURVE 0x00000001 /* -W--V */
|
|
#define NV_097_SET_BEGIN_END_CURVE_CMD_LEFT_GUARD_CURVE 0x00000002 /* -W--V */
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#define NV_097_SET_BEGIN_END_CURVE_CMD_RIGHT_GUARD_CURVE 0x00000003 /* -W--V */
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#define NV_097_SET_BEGIN_END_CURVE_CMD_OUTER_TRANSITION_CURVE 0x00000004 /* -W--V */
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#define NV_097_SET_BEGIN_END_CURVE_CMD_INNER_TRANSITION_CURVE 0x00000005 /* -W--V */
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#define NV_097_SET_BEGIN_END_CURVE_CMD_OUTER_END_PT 0x00000006 /* -W--V */
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#define NV_097_SET_BEGIN_END_CURVE_CMD_INNER_END_PT 0x00000007 /* -W--V */
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#define NV_097_SET_CURVE_COEFFICIENTS(i) (0x005c1e00+(i)*4) /* -W-4A */
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#define NV_097_SET_CURVE_COEFFICIENTS__SIZE_1 4 /* */
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#define NV_097_SET_CURVE_COEFFICIENTS_V 31:0 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0 0x005c1e10 /* -W-4R */
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#define NV_097_SET_BEGIN_TRANSITION0_POSITION_DEGREE 3:0 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM1_DEGREE 7:4 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM2_DEGREE 11:8 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM3_DEGREE 15:12 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM4_DEGREE 19:16 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM5_DEGREE 23:20 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM6_DEGREE 27:24 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION0_PARAM7_DEGREE 31:28 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1 0x005c1e14 /* -W-4R */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM8_DEGREE 3:0 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM9_DEGREE 7:4 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM10_DEGREE 11:8 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM11_DEGREE 15:12 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM12_DEGREE 19:16 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM13_DEGREE 23:20 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM14_DEGREE 27:24 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION1_PARAM15_DEGREE 31:28 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION2 0x005c1e18 /* -W-4R */
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#define NV_097_SET_BEGIN_TRANSITION2_INSIDE_SEGMENTS 9:0 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION2_OUTSIDE_SEGMENTS 19:10 /* -WXUF */
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#define NV_097_SET_BEGIN_TRANSITION2_NUM_COEFFS 31:24 /* -WXUF */
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#define NV_097_SET_END_TRANSITION 0x005c1e1c /* -W-4R */
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#define NV_097_SET_SHADOW_ZSLOPE_THRESHOLD 0x005c1e68 /* -W-4R */
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#define NV_097_SET_SHADOW_ZSLOPE_THRESHOLD_V 31:0 /* -WXUF */
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#define NV_097_SET_SHADOW_DEPTH_FUNC 0x005c1e6c /* -W-4R */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V 31:0 /* -WXUF */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_NEVER 0x00000000 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_LESS 0x00000001 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_EQUAL 0x00000002 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_LEQUAL 0x00000003 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_GREATER 0x00000004 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_NOTEQUAL 0x00000005 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_GEQUAL 0x00000006 /* -W--V */
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#define NV_097_SET_SHADOW_DEPTH_FUNC_V_ALWAYS 0x00000007 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM 0x005c1e70 /* -W-4R */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0 4:0 /* -WXUF */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0_PROGRAM_NONE 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0_2D_PROJECTIVE 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0_3D_PROJECTIVE 0x00000002 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0_CUBE_MAP 0x00000003 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0_PASS_THROUGH 0x00000004 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE0_CLIP_PLANE 0x00000005 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1 9:5 /* -WXUF */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_PROGRAM_NONE 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_2D_PROJECTIVE 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_3D_PROJECTIVE 0x00000002 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_CUBE_MAP 0x00000003 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_PASS_THROUGH 0x00000004 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_CLIP_PLANE 0x00000005 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP 0x00000006 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_BUMPENVMAP_LUMINANCE 0x00000007 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_AR 0x0000000F /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_DEPENDENT_GB 0x00000010 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE1_DOT_PRODUCT 0x00000011 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2 14:10 /* -WXUF */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_PROGRAM_NONE 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_2D_PROJECTIVE 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_3D_PROJECTIVE 0x00000002 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_CUBE_MAP 0x00000003 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_PASS_THROUGH 0x00000004 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_CLIP_PLANE 0x00000005 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP 0x00000006 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_BUMPENVMAP_LUMINANCE 0x00000007 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_BRDF 0x00000008 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ST 0x00000009 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_ZW 0x0000000A /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_REFLECT_DIFFUSE 0x0000000B /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_AR 0x0000000F /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_DEPENDENT_GB 0x00000010 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE2_DOT_PRODUCT 0x00000011 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3 19:15 /* -WXUF */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_PROGRAM_NONE 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_2D_PROJECTIVE 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_3D_PROJECTIVE 0x00000002 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_CUBE_MAP 0x00000003 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_PASS_THROUGH 0x00000004 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_CLIP_PLANE 0x00000005 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP 0x00000006 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_BUMPENVMAP_LUMINANCE 0x00000007 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_BRDF 0x00000008 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ST 0x00000009 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_ZW 0x0000000A /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR 0x0000000C /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_3D 0x0000000D /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_STR_CUBE 0x0000000E /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_AR 0x0000000F /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DEPENDENT_GB 0x00000010 /* -W--V */
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#define NV_097_SET_SHADER_STAGE_PROGRAM_STAGE3_DOT_REFLECT_SPECULAR_CONST 0x00000012 /* -W--V */
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#define NV_097_SET_EYE_VECTOR(i) (0x005c181c+(i)*4) /* -W-4A */
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#define NV_097_SET_EYE_VECTOR__SIZE_1 3 /* */
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#define NV_097_SET_EYE_VECTOR_V 31:0 /* -WXUF */
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#define NV_097_SET_DOT_RGBMAPPING 0x005c1e74 /* -W-4R */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1 3:0 /* -WXUF */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_ZERO_TO_1 0x00000000 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_MINUS_1_TO_1_MS 0x00000001 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_MINUS_1_TO_1_GL 0x00000002 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_MINUS_1_TO_1_NV 0x00000003 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_HILO_1 0x00000004 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_HILO_HEMISPHERE_MS 0x00000005 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_HILO_HEMISPHERE_GL 0x00000006 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE1_HILO_HEMISPHERE_NV 0x00000007 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2 7:4 /* -WXUF */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_ZERO_TO_1 0x00000000 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_MINUS_1_TO_1_MS 0x00000001 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_MINUS_1_TO_1_GL 0x00000002 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_MINUS_1_TO_1_NV 0x00000003 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_HILO_1 0x00000004 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_HILO_HEMISPHERE_MS 0x00000005 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_HILO_HEMISPHERE_GL 0x00000006 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE2_HILO_HEMISPHERE_NV 0x00000007 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3 11:8 /* -WXUF */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_ZERO_TO_1 0x00000000 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_MINUS_1_TO_1_MS 0x00000001 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_MINUS_1_TO_1_GL 0x00000002 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_MINUS_1_TO_1_NV 0x00000003 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_HILO_1 0x00000004 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_HILO_HEMISPHERE_MS 0x00000005 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_HILO_HEMISPHERE_GL 0x00000006 /* -W--V */
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#define NV_097_SET_DOT_RGBMAPPING_STAGE3_HILO_HEMISPHERE_NV 0x00000007 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE 0x005c17f8 /* -W-4R */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_S 0:0 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_S_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_S_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_T 1:1 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_T_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_T_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_R 2:2 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_R_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_R_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_Q 3:3 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_Q_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE0_Q_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_S 4:4 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_S_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_S_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_T 5:5 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_T_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_T_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_R 6:6 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_R_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_R_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_Q 7:7 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_Q_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE1_Q_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_S 8:8 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_S_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_S_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_T 9:9 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_T_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_T_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_R 10:10 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_R_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_R_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_Q 11:11 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_Q_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE2_Q_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_S 12:12 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_S_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_S_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_T 13:13 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_T_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_T_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_R 14:14 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_R_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_R_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_Q 15:15 /* -WXUF */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_Q_CLIPLTZ 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_CLIP_PLANE_MODE_STAGE3_Q_CLIPGEZ 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT 0x005c1e78 /* -W-4R */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1 15:0 /* -WXUF */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE1_INSTAGE_0 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2 19:16 /* -WXUF */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_0 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE2_INSTAGE_1 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3 23:20 /* -WXUF */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_0 0x00000000 /* -W--V */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_1 0x00000001 /* -W--V */
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#define NV_097_SET_SHADER_OTHER_STAGE_INPUT_STAGE3_INSTAGE_2 0x00000002 /* -W--V */
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#define NV_097_SET_SPECULAR_FOG_FACTOR(i) (0x005c1e20+(i)*4) /* -W-4A */
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#define NV_097_SET_SPECULAR_FOG_FACTOR__SIZE_1 2 /* */
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#define NV_097_SET_SPECULAR_FOG_FACTOR_BLUE 7:0 /* -WXUF */
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#define NV_097_SET_SPECULAR_FOG_FACTOR_GREEN 15:8 /* -WXUF */
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#define NV_097_SET_SPECULAR_FOG_FACTOR_RED 23:16 /* -WXUF */
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#define NV_097_SET_SPECULAR_FOG_FACTOR_ALPHA 31:24 /* -WXUF */
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#define NV_097_SET_COMBINER_CONTROL 0x005c1e60 /* -W-4R */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT 7:0 /* -WXUF */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_ONE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_TWO 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_THREE 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_FOUR 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_FIVE 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_SIX 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_SEVEN 0x00000007 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_ITERATION_COUNT_EIGHT 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_MUX_SELECT 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_CONTROL_MUX_SELECT_LSB 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_MUX_SELECT_MSB 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_FACTOR0 15:12 /* -WXUF */
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#define NV_097_SET_COMBINER_CONTROL_FACTOR0_SAME_FACTOR_ALL 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_FACTOR0_EACH_STAGE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_FACTOR1 31:16 /* -WXUF */
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#define NV_097_SET_COMBINER_CONTROL_FACTOR1_SAME_FACTOR_ALL 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_CONTROL_FACTOR1_EACH_STAGE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW(i) (0x005c1e40+(i)*4) /* -W-4A */
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#define NV_097_SET_COMBINER_COLOR_OCW__SIZE_1 8 /* */
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#define NV_097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB 31:19 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_AB_AB_DST_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD 18:18 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_DISABLE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_BLUETOALPHA_CD_CD_DST_ENABLE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP 17:15 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP_NOSHIFT_BIAS 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1 0x00000002 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY1_BIAS 0x00000003 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP_SHIFTLEFTBY2 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_OP_SHIFTRIGHTBY1 0x00000006 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_MUX_ENABLE 14:14 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_MUX_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_MUX_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DOT_ENABLE 13:13 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DOT_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DOT_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DOT_ENABLE 12:12 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DOT_ENABLE_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DOT_ENABLE_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST 11:8 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_SUM_DST_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST 7:4 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_AB_DST_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST 3:0 /* -WXUF */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_0 0x00000000 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_4 0x00000004 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_5 0x00000005 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_8 0x00000008 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_9 0x00000009 /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_A 0x0000000A /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_B 0x0000000B /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_C 0x0000000C /* -W--V */
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#define NV_097_SET_COMBINER_COLOR_OCW_CD_DST_REG_D 0x0000000D /* -W--V */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE 0x005c1e94 /* -W-4R */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE_MODE 1:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE_MODE_FIXED 0x00000000 /* -W--V */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE_MODE_PROGRAM 0x00000002 /* -W--V */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE 31:2 /* -WXUF */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_USER 0x00000000 /* -W--V */
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#define NV_097_SET_TRANSFORM_EXECUTION_MODE_RANGE_MODE_PRIV 0x00000001 /* -W--V */
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#define NV_097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN 0x005c1e98 /* -W-4R */
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#define NV_097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN_V_READ_ONLY 0x00000000 /* -W--V */
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#define NV_097_SET_TRANSFORM_PROGRAM_CXT_WRITE_EN_V_READ_WRITE 0x00000001 /* -W--V */
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#define NV_097_SET_TRANSFORM_PROGRAM_LOAD 0x005c1e9c /* -W-4R */
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#define NV_097_SET_TRANSFORM_PROGRAM_LOAD_PROG_LD_PTR 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_PROGRAM_START 0x005c1ea0 /* -W-4R */
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#define NV_097_SET_TRANSFORM_PROGRAM_START_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_PROGRAM(i) (0x005c0b00+(i)*4) /* -W-4A */
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#define NV_097_SET_TRANSFORM_PROGRAM__SIZE_1 32 /* */
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#define NV_097_SET_TRANSFORM_PROGRAM_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_CONSTANT_LOAD 0x005c1ea4 /* -W-4R */
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#define NV_097_SET_TRANSFORM_CONSTANT_LOAD_CONST_LD_PTR 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_CONSTANT(i) (0x005c0b80+(i)*4) /* -W-4A */
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#define NV_097_SET_TRANSFORM_CONSTANT__SIZE_1 32 /* */
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#define NV_097_SET_TRANSFORM_CONSTANT_V 31:0 /* -WXUF */
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#define NV_097_SET_TRANSFORM_DATA(i) (0x005c1e80+(i)*4) /* -W-4A */
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#define NV_097_SET_TRANSFORM_DATA__SIZE_1 4 /* */
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#define NV_097_SET_TRANSFORM_DATA_V 31:0 /* -WXUF */
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#define NV_097_LAUNCH_TRANSFORM_PROGRAM 0x005c1e90 /* -W-4R */
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#define NV_097_LAUNCH_TRANSFORM_PROGRAM_V 31:0 /* -WXUF */
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#define NV_097_SET_TWO_SIDE_LIGHT_EN 0x005c17c4 /* -W-4R */
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#define NV_097_SET_TWO_SIDE_LIGHT_EN_V 31:0 /* -WXUF */
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#define NV_097_SET_TWO_SIDE_LIGHT_EN_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_TWO_SIDE_LIGHT_EN_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_SET_BACK_SCENE_AMBIENT_COLOR(i) (0x005c17a0+(i)*4) /* -W-4A */
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#define NV_097_SET_BACK_SCENE_AMBIENT_COLOR__SIZE_1 3 /* */
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#define NV_097_SET_BACK_SCENE_AMBIENT_COLOR_V 31:0 /* -WXUF */
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#define NV_097_SET_BACK_MATERIAL_EMISSION(i) (0x005c17b0+(i)*4) /* -W-4A */
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#define NV_097_SET_BACK_MATERIAL_EMISSION__SIZE_1 3 /* */
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#define NV_097_SET_BACK_MATERIAL_EMISSION_V 31:0 /* -WXUF */
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#define NV_097_CLEAR_REPORT_VALUE 0x005c17c8 /* -W-4R */
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#define NV_097_CLEAR_REPORT_VALUE_TYPE 31:0 /* -WXUF */
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#define NV_097_CLEAR_REPORT_VALUE_TYPE_ZPASS_PIXEL_CNT 0x00000001 /* -W--V */
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#define NV_097_SET_ZPASS_PIXEL_COUNT_ENABLE 0x005c17cc /* -W-4R */
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#define NV_097_SET_ZPASS_PIXEL_COUNT_ENABLE_V 31:0 /* -WXUF */
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#define NV_097_SET_ZPASS_PIXEL_COUNT_ENABLE_V_FALSE 0x00000000 /* -W--V */
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#define NV_097_SET_ZPASS_PIXEL_COUNT_ENABLE_V_TRUE 0x00000001 /* -W--V */
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#define NV_097_GET_REPORT 0x005c17d0 /* -W-4R */
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#define NV_097_GET_REPORT_OFFSET 23:0 /* -WXUF */
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#define NV_097_GET_REPORT_TYPE 31:24 /* -WXUF */
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#define NV_097_GET_REPORT_TYPE_ZPASS_PIXEL_CNT 0x00000001 /* -W--V */
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#define NV_097_DEBUG_INIT(i) (0x005c1fc0+(i)*4) /* -W-4A */
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#define NV_097_DEBUG_INIT__SIZE_1 10 /* */
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#define NV_097_DEBUG_INIT_V 31:0 /* -WXUF */
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/* usr_2074.ref */
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#define NV_2074_NOTIFICATION__SIZE_0 0x0000003f:0x00000000 /* ----M */
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#define NV_2074_NOTIFICATION_TIMESTAMP ( 1*32+31):( 0*32+ 0) /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_HDR ( 3*32+31):( 2*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_ZERO_0 1:0 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_CONSTRAINED_PARAMS_FLAG 2:2 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_VBV_BUFFER_SIZE_VALUE 12:3 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_ZERO_1 13:13 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_BIT_RATE_VALUE 31:14 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_FRAME_RATE_CODE 35:32 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_ASPECT_RATIO_INFORMATION 39:36 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_VERTICAL_SIZE_VALUE 51:40 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_HDR_HORIZONTAL_SIZE_VALUE 63:52 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT ( 5*32+31):( 4*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_ZERO_0 15:0 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_FRAME_RATE_EXTENTION_D 20:16 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_FRAME_RATE_EXTENSION_N 22:21 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_VBV_BUFFER_SIZE_EXT 31:24 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_ZERO_1 23:23 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_BIT_RATE_EXT 44:33 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_VERTICAL_SIZE_EXT 46:45 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_HORIZONTAL_SIZE_EXT 48:47 /* ---UF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_CHROMA_FORMAT 50:49 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_PROGRESSIVE_SEQUENCE 51:51 /* ---VF */
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#define NV_2074_NOTIFICAITON_SEQ_EXT_PROFILE_AND_LEVEL_IND 59:52 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_RECEIVED 63:60 /* ---VF */
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#define NV_2074_NOTIFICATION_SEQ_EXT_RECEIVED_NONE 0x00000000 /* ----V */
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#define NV_2074_NOTIFICATION_SEQ_EXT_RECEIVED_HEADER 0x00000001 /* ----V */
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#define NV_2074_NOTIFICATION_SEQ_EXT_RECEIVED_EXTENSION 0x00000002 /* ----V */
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#define NV_2074_NOTIFICATION_GOP_HDR ( 6*32+31):( 6*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_GOP_HDR_ZERO 4:0 /* ---VF */
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#define NV_2074_NOTIFICATION_GOP_HDR_BROKEN_LINK 5:5 /* ---VF */
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#define NV_2074_NOTIFICATION_GOP_HDR_CLOSED_GOP 6:6 /* ---VF */
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#define NV_2074_NOTIFICATION_GOP_HDR_TIME_CODE 31:7 /* ---VF */
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#define NV_2074_NOTIFICATION_ZERO_0 ( 7*32+31):( 7*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR ( 9*32+31):( 8*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_ZERO 26:0 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_BACKWARD_F_CODE 29:27 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_FULL_PEL_BACKWARD_VECTOR 30:30 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_FORWARD_F_CODE 33:31 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_FULL_PEL_FORWARD_VECTOR 34:34 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_VBV_DELAY 50:35 /* ---UF */
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#define NV_2074_NOTIFICATION_PIC_HDR_PICTURE_CODING_TYPE 53:51 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_HDR_TEMPORAL_REFERENCE 63:54 /* ---UF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT (11*32+31):(10*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_ZERO 9:0 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_SUB_CARRIER_PHASE 17:10 /* ---UF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_BURST_AMPLITUDE 24:18 /* ---UF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_SUB_CARRIER 25:25 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_FIELD_SEQUENCE 28:26 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_V_AXIS 29:29 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_COMPOSITE_DISP_FLAG 30:30 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_PROGRESSIVE_FRAME 31:31 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_CHROMA_420_TYPE 32:32 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_REPEAT_FIRST_FIELD 33:33 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_ALTERNATE_SCAN 34:34 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_INTRA_VLC_FORMAT 35:35 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_Q_SCALE_TYPE 36:36 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_CONCEALMENT_MTN_VECTS 37:37 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_FRAME_PRED_FRAME_DCT 38:38 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_TOP_FIELD_FIRST 39:39 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_PICTURE_STRUCTURE 41:40 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_INTRA_DC_PRECISION 43:42 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_F_CODE_BACKWARD_VERT 47:44 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_F_CODE_BACKWARD_HORIZ 51:48 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_F_CODE_FORWARD_VERT 55:52 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_F_CODE_FORWARD_HORIZ 59:56 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_RECEIVED 63:60 /* ---VF */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_RECEIVED_NONE 0x00000000 /* ----V */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_RECEIVED_HEADER 0x00000001 /* ----V */
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#define NV_2074_NOTIFICATION_PIC_CD_EXT_RECEIVED_EXT 0x00000002 /* ----V */
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#define NV_2074_NOTIFICATION_LST_PRSD_BIT_NBR (12*32+31):(12*31+ 0) /* ---UF */
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#define NV_2074_NOTIFICATION_PUBLIC_KEY (13*32+31):(13*31+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_ZERO_1 (15*32+23):(14*32+ 0) /* ---VF */
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#define NV_2074_NOTIFICATION_STATUS (15*32+31):(15*32+24) /* ---VF */
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#define NV_2074_NOTIFICATION_STATUS_DONE_SUCCESS 0x00000000 /* ----V */
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#define NV_2074_NOTIFICATION_STATUS_DONE_MPEG_ERROR 0x00000001 /* ----V */
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#define NV_2074_NOTIFICATION_STATUS_IN_PROGRESS 0x000000ff /* ----V */
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#define NV_2074_SYNCHRONIZE 0x00000100 /* -W-4R */
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#define NV_2074_SYNCHRONIZE_ALL_BITS 31:0 /* -W-VF */
|
|
#define NV_2074_SYNCHRONIZE_NO_OPERATION 0x00000000 /* -W--V */
|
|
#define NV_2074_SYNCHRONIZE_WFI 0x00000001 /* -W--V */
|
|
#define NV_2074_SYNCHRONIZE_WFI_WRITE_PE_NOTIFY 0x00000002 /* -W--V */
|
|
#define NV_2074_SYNCHRONIZE_WFI_WRITE_PE_NOTIFY_AWAKEN 0x00000003 /* -W--V */
|
|
#define NV_2074_SET_CONTEXT_DMA_NOTIFIES 0x00000180 /* -W-4R */
|
|
#define NV_2074_SET_CONTEXT_DMA_NOTIFIES_ALL_BITS 31:0 /* -WCVF */
|
|
#define NV_2074_SET_CONTEXT_DMA_FRAMES 0x00000184 /* -W-4R */
|
|
#define NV_2074_SET_CONTEXT_DMA_FRAMES_ALL_BITS 31:0 /* -WCVF */
|
|
#define NV_2074_SET_PUBLIC_KEY 0x000003e0 /* -W-4R */
|
|
#define NV_2074_SET_PUBLIC_KEY_ALL_BITS 31:0 /* -WCVF */
|
|
#define NV_2074_SET_FORMAT 0x000003e4 /* -W-4R */
|
|
#define NV_2074_SET_FORMAT_FRAME_PITCH 15:0 /* -WCUF */
|
|
#define NV_2074_SET_FORMAT_RENDERING 19:16 /* -WCVF */
|
|
#define NV_2074_SET_FORMAT_RENDERING_DISABLED 0x00000000 /* -W--V */
|
|
#define NV_2074_SET_FORMAT_RENDERING_ENABLED 0x00000001 /* -W--V */
|
|
#define NV_2074_SET_FORMAT_FIELD 31:20 /* -WCVF */
|
|
#define NV_2074_SET_FORMAT_FIELD_AUTOMATIC 0x00000000 /* -W--V */
|
|
#define NV_2074_SET_FORMAT_FIELD_FIRST 0x00000001 /* -W--V */
|
|
#define NV_2074_SET_FORMAT_FIELD_SECOND 0x00000002 /* -W--V */
|
|
#define NV_2074_SET_OFFSET_PAST_LUMA 0x000003e8 /* -W-4R */
|
|
#define NV_2074_SET_OFFSET_PAST_LUMA_ALL_BITS 31:0 /* -WCUF */
|
|
#define NV_2074_SET_OFFSET_PAST_CHROMA 0x000003ec /* -W-4R */
|
|
#define NV_2074_SET_OFFSET_PAST_CHROMA_ALL_BITS 31:0 /* -WCUF */
|
|
#define NV_2074_SET_OFFSET_CURRENT_LUMA 0x000003f0 /* -W-4R */
|
|
#define NV_2074_SET_OFFSET_CURRENT_LUMA_ALL_BITS 31:0 /* -WCUF */
|
|
#define NV_2074_SET_OFFSET_CURRENT_CHROMA 0x000003f4 /* -W-4R */
|
|
#define NV_2074_SET_OFFSET_CURRENT_CHROMA_ALL_BITS 31:0 /* -WCUF */
|
|
#define NV_2074_SET_OFFSET_FUTURE_LUMA 0x000003f8 /* -W-4R */
|
|
#define NV_2074_SET_OFFSET_FUTURE_LUMA_ALL_BITS 31:0 /* -WCUF */
|
|
#define NV_2074_SET_OFFSET_FUTURE_CHROMA 0x000003fc /* -W-4R */
|
|
#define NV_2074_SET_OFFSET_FUTURE_CHROMA_ALL_BITS 31:0 /* -WCUF */
|
|
#define NV_2074_SET_DATA(i) (0x00000400+(i)*4) /* -W-4A */
|
|
#define NV_2074_SET_DATA__SIZE_1 128 /* */
|
|
#define NV_2074_SET_DATA_VALUE 31:0 /* -WCVF */
|
|
#define NV_2074_SET_ENCRYPTED_DATA_LEFT(i) (0x00000600+(i)*8) /* -W-4A */
|
|
#define NV_2074_SET_ENCRYPTED_DATA_LEFT__SIZE_1 64 /* */
|
|
#define NV_2074_SET_ENCRYPTES_DATA_LEFT_ALL_BITS 31:0 /* -WCVF */
|
|
#define NV_2074_SET_ENCRYPTED_DATA_RIGHT(i) (0x00000604+(i)*8) /* -W-4A */
|
|
#define NV_2074_SET_ENCRYPTED_DATA_RIGHT__SIZE_1 64 /* */
|
|
#define NV_2074_SET_ENCRYPTED_DATA_RIGHT_ALL_BITS 31:0 /* -W-VF */
|
|
/* usr_pattern.ref */
|
|
#define NV_IMAGE_PATTERN 0x00000018 /* ----C */
|
|
#define NV_UPATT 0x00461FFF:0x00460000 /* -W--D */
|
|
#define NV_UPATT_CTX_SWITCH 0x00460000 /* -W-4R */
|
|
#define NV_UPATT_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UPATT_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UPATT_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UPATT_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UPATT_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UPATT_NOTIFY 0x00460104 /* -W-4R */
|
|
#define NV_UPATT_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UPATT_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UPATT_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UPATT_SET_NOTIFY 0x00460104 /* -W-4R */
|
|
#define NV_UPATT_SET_NOTIFY__ALIAS_1 NV_UPATT_NOTIFY /* */
|
|
#define NV_UPATT_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UPATT_SET_CONTEXT_DMA_NOTIFY 0x00460180 /* -W-4R */
|
|
#define NV_UPATT_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_IMAGE_OUTPUT 0x00460200 /* -W-4R */
|
|
#define NV_UPATT_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_COLOR_FORMAT 0x00460300 /* -W-4R */
|
|
#define NV_UPATT_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_COLOR_FORMAT_LE_X16A8Y8 0x00000001 /* -W--V */
|
|
#define NV_UPATT_SET_COLOR_FORMAT_LE_X16A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_UPATT_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_UPATT_SET_MONOCHROME_FORMAT 0x00460304 /* -W-4R */
|
|
#define NV_UPATT_SET_MONOCHROME_FORMAT_VALUE 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_SHAPE 0x00460308 /* -W-4R */
|
|
#define NV_UPATT_SET_SHAPE_VALUE 1:0 /* -W-VF */
|
|
#define NV_UPATT_SET_SHAPE_VALUE_8X_8Y 0x00000000 /* -W--V */
|
|
#define NV_UPATT_SET_SHAPE_VALUE_64X_1Y 0x00000001 /* -W--V */
|
|
#define NV_UPATT_SET_SHAPE_VALUE_1X_64Y 0x00000002 /* -W--V */
|
|
#define NV_UPATT_SET_COLOR0 0x00460310 /* -W-4R */
|
|
#define NV_UPATT_SET_COLOR0_VALUE 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_COLOR1 0x00460314 /* -W-4R */
|
|
#define NV_UPATT_SET_COLOR1_VALUE 31:0 /* -W-VF */
|
|
#define NV_UPATT_SET_PATTERN(i) (0x00460318+(i)*4) /* -W-4A */
|
|
#define NV_UPATT_SET_PATTERN__SIZE_1 2 /* */
|
|
#define NV_UPATT_SET_PATTERN_BITMAP 31:0 /* -W-VF */
|
|
/* usr_nv4_image_pattern.ref */
|
|
#define NV4_IMAGE_PATTERN 0x00000044 /* ----C */
|
|
#define NV_044 0x00681FFF:0x00680000 /* -W--D */
|
|
#define NV_044_CTX_SWITCH 0x00680000 /* -W-4R */
|
|
#define NV_044_NOP 0x00680100 /* -W-4R */
|
|
#define NV_044_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_044_NOTIFY 0x00680104 /* -W-4R */
|
|
#define NV_044_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_044_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_044_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_044_NOTIFY__ALIAS_1 NV_044_SET_NOTIFY /* */
|
|
#define NV_044_SET_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_044_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_044_SET_CONTEXT_DMA_NOTIFY 0x00680180 /* -W-4R */
|
|
#define NV_044_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_044_SET_IMAGE_OUTPUT 0x00680200 /* -W-4R */
|
|
#define NV_044_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_044_SET_COLOR_FORMAT 0x00680300 /* -W-4R */
|
|
#define NV_044_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_044_SET_COLOR_FORMAT_LE_A16R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_044_SET_COLOR_FORMAT_LE_X16A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_044_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_044_SET_MONOCHROME_FORMAT 0x00680304 /* -W-4R */
|
|
#define NV_044_SET_MONOCHROME_FORMAT_VALUE 31:0 /* -W-VF */
|
|
#define NV_044_SET_MONOCHROME_FORMAT_VALUE_CGA6_M1 0x00000001 /* -W--V */
|
|
#define NV_044_SET_MONOCHROME_FORMAT_VALUE_LE_M1 0x00000002 /* -W--V */
|
|
#define NV_044_SET_MONOCHROME_SHAPE 0x00680308 /* -W-4R */
|
|
#define NV_044_SET_MONOCHROME_SHAPE_VALUE 31:0 /* -W-VF */
|
|
#define NV_044_SET_MONOCHROME_SHAPE_VALUE_8X_8Y 0x00000000 /* -W--V */
|
|
#define NV_044_SET_MONOCHROME_SHAPE_VALUE_64X_1Y 0x00000001 /* -W--V */
|
|
#define NV_044_SET_MONOCHROME_SHAPE_VALUE_1X_64Y 0x00000002 /* -W--V */
|
|
#define NV_044_SET_PATTERN_SELECT 0x0068030C /* -W-4R */
|
|
#define NV_044_SET_PATTERN_SELECT_VALUE 31:0 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_SELECT_VALUE_MONOCHROME 0x00000001 /* -W--V */
|
|
#define NV_044_SET_PATTERN_SELECT_VALUE_COLOR 0x00000002 /* -W--V */
|
|
#define NV_044_SET_MONOCHROME_COLOR0 0x00680310 /* -W-4R */
|
|
#define NV_044_SET_MONOCHROME_COLOR0_VALUE 31:0 /* -W-VF */
|
|
#define NV_044_SET_MONOCHROME_COLOR1 0x00680314 /* -W-4R */
|
|
#define NV_044_SET_MONOCHROME_COLOR1_VALUE 31:0 /* -W-VF */
|
|
#define NV_044_SET_MONOCHROME_PATTERN0 0x00680318 /* -W-4A */
|
|
#define NV_044_SET_MONOCHROME_PATTERN0_BITMAP 31:0 /* -W-VF */
|
|
#define NV_044_SET_MONOCHROME_PATTERN1 0x0068031C /* -W-4A */
|
|
#define NV_044_SET_MONOCHROME_PATTERN1_BITMAP 31:0 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_Y8(i) (0x00680400+(i)*4) /* -W-4A */
|
|
#define NV_044_SET_PATTERN_Y8__SIZE_1 16 /* */
|
|
#define NV_044_SET_PATTERN_Y8_Y0 7:0 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_Y8_Y1 15:8 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_Y8_Y2 23:16 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_Y8_Y3 31:24 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_R5G6B5(i) (0x00680500+(i)*4) /* -W-4A */
|
|
#define NV_044_SET_PATTERN_R5G6B5__SIZE_1 32 /* */
|
|
#define NV_044_SET_PATTERN_R5G6B5_BLUE0 4:0 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_R5G6B5_GREEN0 10:5 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_R5G6B5_RED0 15:11 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_R5G6B5_BLUE1 20:16 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_R5G6B5_GREEN1 26:21 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_R5G6B5_RED1 31:27 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5(i) (0x00680600+(i)*4) /* -W-4A */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5__SIZE_1 32 /* */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_BLUE0 4:0 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_GREEN0 9:5 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_RED0 14:10 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_IGNORE0 15:15 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_BLUE1 20:16 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_GREEN1 25:21 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_RED1 30:26 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X1R5G5B5_IGNORE1 31:31 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X8R8G8B8(i) (0x00680700+(i)*4) /* -W-4A */
|
|
#define NV_044_SET_PATTERN_X8R8G8B8__SIZE_1 64 /* */
|
|
#define NV_044_SET_PATTERN_X8R8G8B8_BLUE 7:0 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X8R8G8B8_GREEN 15:8 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X8R8G8B8_RED 23:16 /* -W-VF */
|
|
#define NV_044_SET_PATTERN_X8R8G8B8_IGNORE 31:24 /* -W-VF */
|
|
/* usr_nv4_beta_solid.ref */
|
|
#define NV4_BETA_SOLID 0x00000072 /* ----C */
|
|
#define NV_072 0x00621FFF:0x00620000 /* -W--D */
|
|
#define NV_072_CTX_SWITCH 0x00620000 /* -W-4R */
|
|
#define NV_072_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_072_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_072_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_072_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_072_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_072_NOP 0x00620100 /* -W-4R */
|
|
#define NV_072_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_072_NOTIFY 0x00620104 /* -W-4R */
|
|
#define NV_072_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_072_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_072_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_072_SET_NOTIFY 0x00620104 /* -W-4R */
|
|
#define NV_072_SET_NOTIFY__ALIAS_1 NV_072_NOTIFY /* */
|
|
#define NV_072_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_072_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_072_SET_CONTEXT_DMA_NOTIFY 0x00620180 /* -W-4R */
|
|
#define NV_072_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_072_SET_BETA_OUTPUT 0x00620200 /* -W-4R */
|
|
#define NV_072_SET_BETA_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_072_SET_BETA_FACTOR 0x00620300 /* -W-4R */
|
|
#define NV_072_SET_BETA_FACTOR_BLUE 7:0 /* -W-UF */
|
|
#define NV_072_SET_BETA_FACTOR_GREEN 15:8 /* -W-UF */
|
|
#define NV_072_SET_BETA_FACTOR_RED 23:16 /* -W-UF */
|
|
#define NV_072_SET_BETA_FACTOR_ALPHA 31:24 /* -W-UF */
|
|
/* usr_nv1_render_solid_lin.ref */
|
|
#define NV1_RENDER_SOLID_LIN 0x0000001C /* ----C */
|
|
#define NV_01C 0x006A1FFF:0x006A0000 /* -W--D */
|
|
#define NV_01C_CTX_SWITCH 0x006A0000 /* -W-4R */
|
|
#define NV_01C_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_01C_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_01C_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_01C_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_01C_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_01C_NOP 0x006A0100 /* -W-4R */
|
|
#define NV_01C_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_01C_NOTIFY 0x006A0104 /* -W-4R */
|
|
#define NV_01C_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_01C_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_01C_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_01C_SET_NOTIFY 0x006A0104 /* -W-4R */
|
|
#define NV_01C_SET_NOTIFY__ALIAS_1 NV_01C_NOTIFY /* */
|
|
#define NV_01C_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_01C_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_01C_SET_PATCH 0x006A010C /* -W-4R */
|
|
#define NV_01C_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_01C_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_01C_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_01C_SET_CONTEXT_DMA_NOTIFY 0x006A0180 /* -W-4R */
|
|
#define NV_01C_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_01C_SET_IMAGE_OUTPUT 0x006A0200 /* -W-4R */
|
|
#define NV_01C_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_01C_SET_COLOR_FORMAT 0x006A0300 /* -W-4R */
|
|
#define NV_01C_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_01C_SET_COLOR_FORMAT_LE_X24Y8 0x00000001 /* -W--V */
|
|
#define NV_01C_SET_COLOR_FORMAT_LE_X17R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_01C_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_01C_SET_COLOR_FORMAT_LE_X16Y16 0x00000004 /* -W--V */
|
|
#define NV_01C_COLOR 0x006A0304 /* -W-4R */
|
|
#define NV_01C_COLOR_VALUE 31:0 /* -W-VF */
|
|
#define NV_01C_LIN_0(i) (0x006A0400+(i)*8) /* -W-4A */
|
|
#define NV_01C_LIN_0__SIZE_1 16 /* */
|
|
#define NV_01C_LIN_0_X 15:0 /* -W-SF */
|
|
#define NV_01C_LIN_0_Y 31:16 /* -W-SF */
|
|
#define NV_01C_LIN_1(i) (0x006A0404+(i)*8) /* -W-4A */
|
|
#define NV_01C_LIN_1__SIZE_1 16 /* */
|
|
#define NV_01C_LIN_1_X 15:0 /* -W-SF */
|
|
#define NV_01C_LIN_1_Y 31:16 /* -W-SF */
|
|
#define NV_01C_LIN32_0(i) (0x006A0480+(i)*16) /* -W-4A */
|
|
#define NV_01C_LIN32_0__SIZE_1 8 /* */
|
|
#define NV_01C_LIN32_0_X 31:0 /* -W-SF */
|
|
#define NV_01C_LIN32_1(i) (0x006A0484+(i)*16) /* -W-4A */
|
|
#define NV_01C_LIN32_1__SIZE_1 8 /* */
|
|
#define NV_01C_LIN32_1_Y 31:0 /* -W-SF */
|
|
#define NV_01C_LIN32_2(i) (0x006A0488+(i)*16) /* -W-4A */
|
|
#define NV_01C_LIN32_2__SIZE_1 8 /* */
|
|
#define NV_01C_LIN32_2_X 31:0 /* -W-SF */
|
|
#define NV_01C_LIN32_3(i) (0x006A048C+(i)*16) /* -W-4A */
|
|
#define NV_01C_LIN32_3__SIZE_1 8 /* */
|
|
#define NV_01C_LIN32_3_Y 31:0 /* -W-SF */
|
|
#define NV_01C_POLYLIN(i) (0x006A0500+(i)*4) /* -W-4A */
|
|
#define NV_01C_POLYLIN__SIZE_1 32 /* */
|
|
#define NV_01C_POLYLIN_X 15:0 /* -W-SF */
|
|
#define NV_01C_POLYLIN_Y 31:16 /* -W-SF */
|
|
#define NV_01C_POLYLIN32_0(i) (0x006A0580+(i)*8) /* -W-4A */
|
|
#define NV_01C_POLYLIN32_0__SIZE_1 16 /* */
|
|
#define NV_01C_POLYLIN32_0_X 31:0 /* -W-SF */
|
|
#define NV_01C_POLYLIN32_1(i) (0x006A0584+(i)*8) /* -W-4A */
|
|
#define NV_01C_POLYLIN32_1__SIZE_1 16 /* */
|
|
#define NV_01C_POLYLIN32_1_Y 31:0 /* -W-SF */
|
|
#define NV_01C_CPOLYLIN_0(i) (0x006A0600+(i)*8) /* -W-4A */
|
|
#define NV_01C_CPOLYLIN_0__SIZE_1 16 /* */
|
|
#define NV_01C_CPOLYLIN_0_COLOR 31:0 /* -W-VF */
|
|
#define NV_01C_CPOLYLIN_1(i) (0x006A0604+(i)*8) /* -W-4A */
|
|
#define NV_01C_CPOLYLIN_1__SIZE_1 16 /* */
|
|
#define NV_01C_CPOLYLIN_1_X 15:0 /* -W-SF */
|
|
#define NV_01C_CPOLYLIN_1_Y 31:16 /* -W-SF */
|
|
/* usr_nv4_render_solid_lin.ref */
|
|
#define NV4_RENDER_SOLID_LIN 0x0000005C /* ----C */
|
|
#define NV_ULIN 0x004A1FFF:0x004A0000 /* -W--D */
|
|
#define NV_ULIN_CTX_SWITCH 0x004A0000 /* -W-4R */
|
|
#define NV_ULIN_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_ULIN_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_ULIN_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_ULIN_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_ULIN_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_ULIN_NOP 0x004A0100 /* -W-4R */
|
|
#define NV_ULIN_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_ULIN_NOTIFY 0x004A0104 /* -W-4R */
|
|
#define NV_ULIN_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_ULIN_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_ULIN_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_ULIN_SET_NOTIFY 0x004A0104 /* -W-4R */
|
|
#define NV_ULIN_SET_NOTIFY__ALIAS_1 NV_ULIN_NOTIFY /* */
|
|
#define NV_ULIN_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_ULIN_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_ULIN_SET_PATCH 0x004A010C /* -W-4R */
|
|
#define NV_ULIN_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_ULIN_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_ULIN_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_ULIN_SET_CONTEXT_DMA_NOTIFY 0x004A0180 /* -W-4R */
|
|
#define NV_ULIN_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_ULIN_SET_IMAGE_OUTPUT 0x004A0200 /* -W-4R */
|
|
#define NV_ULIN_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_ULIN_SET_COLOR_FORMAT 0x004A0300 /* -W-4R */
|
|
#define NV_ULIN_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_ULIN_SET_COLOR_FORMAT_LE_X16R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_ULIN_SET_COLOR_FORMAT_LE_X17R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_ULIN_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_ULIN_COLOR 0x004A0304 /* -W-4R */
|
|
#define NV_ULIN_COLOR_VALUE 31:0 /* -W-VF */
|
|
#define NV_ULIN_LIN_0(i) (0x004A0400+(i)*8) /* -W-4A */
|
|
#define NV_ULIN_LIN_0__SIZE_1 16 /* */
|
|
#define NV_ULIN_LIN_0_X 15:0 /* -W-SF */
|
|
#define NV_ULIN_LIN_0_Y 31:16 /* -W-SF */
|
|
#define NV_ULIN_LIN_1(i) (0x004A0404+(i)*8) /* -W-4A */
|
|
#define NV_ULIN_LIN_1__SIZE_1 16 /* */
|
|
#define NV_ULIN_LIN_1_X 15:0 /* -W-SF */
|
|
#define NV_ULIN_LIN_1_Y 31:16 /* -W-SF */
|
|
#define NV_ULIN_LIN32_0(i) (0x004A0480+(i)*16) /* -W-4A */
|
|
#define NV_ULIN_LIN32_0__SIZE_1 8 /* */
|
|
#define NV_ULIN_LIN32_0_X 31:0 /* -W-SF */
|
|
#define NV_ULIN_LIN32_1(i) (0x004A0484+(i)*16) /* -W-4A */
|
|
#define NV_ULIN_LIN32_1__SIZE_1 8 /* */
|
|
#define NV_ULIN_LIN32_1_Y 31:0 /* -W-SF */
|
|
#define NV_ULIN_LIN32_2(i) (0x004A0488+(i)*16) /* -W-4A */
|
|
#define NV_ULIN_LIN32_2__SIZE_1 8 /* */
|
|
#define NV_ULIN_LIN32_2_X 31:0 /* -W-SF */
|
|
#define NV_ULIN_LIN32_3(i) (0x004A048C+(i)*16) /* -W-4A */
|
|
#define NV_ULIN_LIN32_3__SIZE_1 8 /* */
|
|
#define NV_ULIN_LIN32_3_Y 31:0 /* -W-SF */
|
|
#define NV_ULIN_POLYLIN(i) (0x004A0500+(i)*4) /* -W-4A */
|
|
#define NV_ULIN_POLYLIN__SIZE_1 32 /* */
|
|
#define NV_ULIN_POLYLIN_X 15:0 /* -W-SF */
|
|
#define NV_ULIN_POLYLIN_Y 31:16 /* -W-SF */
|
|
#define NV_ULIN_POLYLIN32_0(i) (0x004A0580+(i)*8) /* -W-4A */
|
|
#define NV_ULIN_POLYLIN32_0__SIZE_1 16 /* */
|
|
#define NV_ULIN_POLYLIN32_0_X 31:0 /* -W-SF */
|
|
#define NV_ULIN_POLYLIN32_1(i) (0x004A0584+(i)*8) /* -W-4A */
|
|
#define NV_ULIN_POLYLIN32_1__SIZE_1 16 /* */
|
|
#define NV_ULIN_POLYLIN32_1_Y 31:0 /* -W-SF */
|
|
#define NV_ULIN_CPOLYLIN_0(i) (0x004A0600+(i)*8) /* -W-4A */
|
|
#define NV_ULIN_CPOLYLIN_0__SIZE_1 16 /* */
|
|
#define NV_ULIN_CPOLYLIN_0_COLOR 31:0 /* -W-VF */
|
|
#define NV_ULIN_CPOLYLIN_1(i) (0x004A0604+(i)*8) /* -W-4A */
|
|
#define NV_ULIN_CPOLYLIN_1__SIZE_1 16 /* */
|
|
#define NV_ULIN_CPOLYLIN_1_X 15:0 /* -W-SF */
|
|
#define NV_ULIN_CPOLYLIN_1_Y 31:16 /* -W-SF */
|
|
/* usr_nv4_render_solid_rectangle.ref */
|
|
#define NV_RENDER_SOLID_RECTANGLE 0x0000005E /* ----C */
|
|
#define NV_URECT 0x00471FFF:0x00470000 /* -W--D */
|
|
#define NV_URECT_CTX_SWITCH 0x00470000 /* -W-4R */
|
|
#define NV_URECT_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_URECT_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_URECT_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_URECT_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_URECT_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_URECT_NOP 0x00470100 /* -W-4R */
|
|
#define NV_URECT_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_URECT_NOTIFY 0x00470104 /* -W-4R */
|
|
#define NV_URECT_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_URECT_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_URECT_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_URECT_SET_NOTIFY 0x00470104 /* -W-4R */
|
|
#define NV_URECT_SET_NOTIFY__ALIAS_1 NV_URECT_NOTIFY /* */
|
|
#define NV_URECT_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_URECT_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_URECT_SET_PATCH 0x0047010C /* -W-4R */
|
|
#define NV_URECT_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_URECT_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_URECT_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_URECT_SET_CONTEXT_DMA_NOTIFY 0x00470180 /* -W-4R */
|
|
#define NV_URECT_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_URECT_SET_IMAGE_OUTPUT 0x00470200 /* -W-4R */
|
|
#define NV_URECT_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_URECT_SET_COLOR_FORMAT 0x00470300 /* -W-4R */
|
|
#define NV_URECT_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_URECT_SET_COLOR_FORMAT_LE_X16R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_URECT_SET_COLOR_FORMAT_LE_X17R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_URECT_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_URECT_COLOR 0x00470304 /* -W-4R */
|
|
#define NV_URECT_COLOR_VALUE 31:0 /* -W-VF */
|
|
#define NV_URECT_RECTANGLE_0(i) (0x00470400+(i)*8) /* -W-4A */
|
|
#define NV_URECT_RECTANGLE_0__SIZE_1 16 /* */
|
|
#define NV_URECT_RECTANGLE_0_X 15:0 /* -W-SF */
|
|
#define NV_URECT_RECTANGLE_0_Y 31:16 /* -W-SF */
|
|
#define NV_URECT_RECTANGLE_1(i) (0x00470404+(i)*8) /* -W-4A */
|
|
#define NV_URECT_RECTANGLE_1__SIZE_1 16 /* */
|
|
#define NV_URECT_RECTANGLE_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_URECT_RECTANGLE_1_HEIGHT 31:16 /* -W-UF */
|
|
/* usr_nv4_render_solid_triangle.ref */
|
|
#define NV_RENDER_SOLID_TRIANGLE 0x0000005D /* ----C */
|
|
#define NV_UTRI 0x004B1FFF:0x004B0000 /* -W--D */
|
|
#define NV_UTRI_CTX_SWITCH 0x004B0000 /* -W-4R */
|
|
#define NV_UTRI_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UTRI_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UTRI_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UTRI_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UTRI_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UTRI_NOP 0x004B0100 /* -W-4R */
|
|
#define NV_UTRI_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UTRI_NOTIFY 0x004B0104 /* -W-4R */
|
|
#define NV_UTRI_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UTRI_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UTRI_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UTRI_SET_NOTIFY 0x004B0104 /* -W-4R */
|
|
#define NV_UTRI_SET_NOTIFY__ALIAS_1 NV_UTRI_NOTIFY /* */
|
|
#define NV_UTRI_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UTRI_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UTRI_SET_PATCH 0x004B010C /* -W-4R */
|
|
#define NV_UTRI_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UTRI_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_UTRI_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_UTRI_SET_CONTEXT_DMA_NOTIFY 0x004B0180 /* -W-4R */
|
|
#define NV_UTRI_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UTRI_SET_IMAGE_OUTPUT 0x004B0200 /* -W-4R */
|
|
#define NV_UTRI_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UTRI_SET_COLOR_FORMAT 0x004B0300 /* -W-4R */
|
|
#define NV_UTRI_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_UTRI_SET_COLOR_FORMAT_LE_X16R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_UTRI_SET_COLOR_FORMAT_LE_X17R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_UTRI_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_UTRI_COLOR 0x004B0304 /* -W-4R */
|
|
#define NV_UTRI_COLOR_VALUE 31:0 /* -W-VF */
|
|
#define NV_UTRI_TRIANGLE_0 0x004B0310 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE_0_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE_0_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE_1 0x004B0314 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE_1_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE_1_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE_2 0x004B0318 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE_2_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE_2_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE32_0 0x004B0320 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE32_0_X 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE32_1 0x004B0324 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE32_1_Y 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE32_2 0x004B0328 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE32_2_X 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE32_3 0x004B032C /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE32_3_Y 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE32_4 0x004B0330 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE32_4_X 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIANGLE32_5 0x004B0334 /* -W-4R */
|
|
#define NV_UTRI_TRIANGLE32_5_Y 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIMESH(i) (0x004B0400+(i)*4) /* -W-4A */
|
|
#define NV_UTRI_TRIMESH__SIZE_1 32 /* */
|
|
#define NV_UTRI_TRIMESH_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_TRIMESH_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_TRIMESH32_0(i) (0x004B0480+(i)*8) /* -W-4A */
|
|
#define NV_UTRI_TRIMESH32_0__SIZE_1 16 /* */
|
|
#define NV_UTRI_TRIMESH32_0_X 31:0 /* -W-SF */
|
|
#define NV_UTRI_TRIMESH32_1(i) (0x004B0484+(i)*8) /* -W-4A */
|
|
#define NV_UTRI_TRIMESH32_1__SIZE_1 16 /* */
|
|
#define NV_UTRI_TRIMESH32_1_Y 31:0 /* -W-SF */
|
|
#define NV_UTRI_CTRIANGLE_0(i) (0x004B0500+(i)*16) /* -W-4A */
|
|
#define NV_UTRI_CTRIANGLE_0__SIZE_1 8 /* */
|
|
#define NV_UTRI_CTRIANGLE_0_COLOR 31:0 /* -W-VF */
|
|
#define NV_UTRI_CTRIANGLE_1(i) (0x004B0504+(i)*16) /* -W-4A */
|
|
#define NV_UTRI_CTRIANGLE_1__SIZE_1 8 /* */
|
|
#define NV_UTRI_CTRIANGLE_1_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_CTRIANGLE_1_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_CTRIANGLE_2(i) (0x004B0508+(i)*16) /* -W-4A */
|
|
#define NV_UTRI_CTRIANGLE_2__SIZE_1 8 /* */
|
|
#define NV_UTRI_CTRIANGLE_2_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_CTRIANGLE_2_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_CTRIANGLE_3(i) (0x004B050C+(i)*16) /* -W-4A */
|
|
#define NV_UTRI_CTRIANGLE_3__SIZE_1 8 /* */
|
|
#define NV_UTRI_CTRIANGLE_3_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_CTRIANGLE_3_Y 31:16 /* -W-SF */
|
|
#define NV_UTRI_CTRIMESH_0(i) (0x004B0580+(i)*8) /* -W-4A */
|
|
#define NV_UTRI_CTRIMESH_0__SIZE_1 16 /* */
|
|
#define NV_UTRI_CTRIMESH_0_COLOR 31:0 /* -W-VF */
|
|
#define NV_UTRI_CTRIMESH_1(i) (0x004B0584+(i)*8) /* -W-4A */
|
|
#define NV_UTRI_CTRIMESH_1__SIZE_1 16 /* */
|
|
#define NV_UTRI_CTRIMESH_1_X 15:0 /* -W-SF */
|
|
#define NV_UTRI_CTRIMESH_1_Y 31:16 /* -W-SF */
|
|
/* usr_nv4_image_blit.ref */
|
|
#define NV_IMAGE_BLIT 0x0000005F /* ----C */
|
|
#define NV_UBLIT 0x00501FFF:0x00500000 /* -W--D */
|
|
#define NV_UBLIT_CTX_SWITCH 0x00500000 /* -W-4R */
|
|
#define NV_UBLIT_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UBLIT_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UBLIT_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UBLIT_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UBLIT_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UBLIT_NOP 0x00500100 /* -W-4R */
|
|
#define NV_UBLIT_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBLIT_NOTIFY 0x00500104 /* -W-4R */
|
|
#define NV_UBLIT_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UBLIT_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UBLIT_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UBLIT_SET_NOTIFY 0x00500104 /* -W-4R */
|
|
#define NV_UBLIT_SET_NOTIFY__ALIAS_1 NV_UBLIT_NOTIFY /* */
|
|
#define NV_UBLIT_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBLIT_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UBLIT_SET_PATCH 0x0050010C /* -W-4R */
|
|
#define NV_UBLIT_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBLIT_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_UBLIT_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_UBLIT_SET_CONTEXT_DMA_NOTIFY 0x00500180 /* -W-4R */
|
|
#define NV_UBLIT_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBLIT_SET_IMAGE_OUTPUT 0x00500200 /* -W-4R */
|
|
#define NV_UBLIT_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBLIT_SET_IMAGE_INPUT 0x00500204 /* -W-4R */
|
|
#define NV_UBLIT_SET_IMAGE_INPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UBLIT_POINT_IN 0x00500300 /* -W-4R */
|
|
#define NV_UBLIT_POINT_IN_X 15:0 /* -W-UF */
|
|
#define NV_UBLIT_POINT_IN_Y 31:16 /* -W-UF */
|
|
#define NV_UBLIT_POINT_OUT 0x00500304 /* -W-4R */
|
|
#define NV_UBLIT_POINT_OUT_X 15:0 /* -W-UF */
|
|
#define NV_UBLIT_POINT_OUT_Y 31:16 /* -W-UF */
|
|
#define NV_UBLIT_SIZE 0x00500308 /* -W-4R */
|
|
#define NV_UBLIT_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_UBLIT_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
/* usr_nv4_indexed_image_from_cpu.ref */
|
|
#define NV4_INDEXED_IMAGE_FROM_CPU 0x00000060 /* ----C */
|
|
#define NV_060 0x00691FFF:0x00690000 /* -W--D */
|
|
#define NV_060_CTX_SWITCH 0x00690000 /* -W-4R */
|
|
#define NV_060_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_060_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_060_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_060_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_060_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_060_NOP 0x00690100 /* -W-4R */
|
|
#define NV_060_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_060_NOTIFY 0x00690104 /* -W-4R */
|
|
#define NV_060_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_060_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_060_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_060_SET_NOTIFY 0x00690104 /* -W-4R */
|
|
#define NV_060_SET_NOTIFY__ALIAS_1 NV_060_NOTIFY /* */
|
|
#define NV_060_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_060_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_060_SET_PATCH 0x0069010C /* -W-4R */
|
|
#define NV_060_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_060_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_060_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_060_SET_CONTEXT_DMA_NOTIFY 0x00690180 /* -W-4R */
|
|
#define NV_060_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_060_SET_CONTEXT_DMA_LUT 0x00690184 /* -W-4R */
|
|
#define NV_060_SET_CONTEXT_DMA_LUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_060_SET_IMAGE_OUTPUT 0x00690200 /* -W-4R */
|
|
#define NV_060_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_060_SET_COLOR_FORMAT 0x006903E8 /* -W-4R */
|
|
#define NV_060_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_060_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_060_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_060_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_060_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_060_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_060_INDEX_FORMAT 0x006903EC /* -W-4R */
|
|
#define NV_060_INDEX_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_060_INDEX_FORMAT_LE_I8 0x00000000 /* -W--V */
|
|
#define NV_060_INDEX_FORMAT_LE_I4 0x00000001 /* -W--V */
|
|
#define NV_060_LUT_OFFSET 0x006903F0 /* -W-4R */
|
|
#define NV_060_LUT_OFFSET_ARGUMENT 31:0 /* -W-UF */
|
|
#define NV_060_POINT 0x006903F4 /* -W-4R */
|
|
#define NV_060_POINT_X 15:0 /* -W-SF */
|
|
#define NV_060_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_060_SIZE_OUT 0x006903F8 /* -W-4R */
|
|
#define NV_060_SIZE_OUT_WIDTH 15:0 /* -W-UF */
|
|
#define NV_060_SIZE_OUT_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_060_SIZE_IN 0x006903FC /* -W-4R */
|
|
#define NV_060_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_060_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_060_COLOR(i) (0x00690400+(i)*4) /* -W-4A */
|
|
#define NV_060_COLOR__SIZE_1 1792 /* */
|
|
#define NV_060_COLOR_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv5_indexed_image_from_cpu.ref */
|
|
#define NV5_INDEXED_IMAGE_FROM_CPU 0x00000064 /* ----C */
|
|
#define NV_064 0x00651FFF:0x00650000 /* -W--D */
|
|
#define NV_064_NV5_INDEXED_IMAGE_FROM_CPU 0x00650000 /* -W-4R */
|
|
#define NV_064_NV5_INDEXED_IMAGE_FROM_CPU_HANDLE 31:0 /* -WXVF */
|
|
#define NV_064_NOP 0x00650100 /* -W-4R */
|
|
#define NV_064_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_NOTIFY 0x00650104 /* -W-4R */
|
|
#define NV_064_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_064_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_064_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_064_SET_NOTIFY 0x00650104 /* -W-4R */
|
|
#define NV_064_SET_NOTIFY__ALIAS_1 NV_064_NOTIFY /* */
|
|
#define NV_064_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_064_SET_CONTEXT_DMA_NOTIFY 0x00650180 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_DMA_LUT 0x00650184 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_DMA_LUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_COLOR_KEY 0x00650188 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_COLOR_KEY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_CLIP_RECTANGLE 0x0065018C /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_CLIP_RECTANGLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_PATTERN 0x00650190 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_ROP 0x00650194 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_BETA1 0x00650198 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_BETA4 0x0065019C /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_CONTEXT_SURFACE 0x006501A0 /* -W-4R */
|
|
#define NV_064_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_064_SET_COLOR_CONVERSION 0x006503E0 /* -W-4R */
|
|
#define NV_064_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_064_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_064_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_064_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_064_SET_OPERATION 0x006503E4 /* -W-4R */
|
|
#define NV_064_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_064_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_064_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_064_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_064_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_064_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_064_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_064_SET_COLOR_FORMAT 0x006503E8 /* -W-4R */
|
|
#define NV_064_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_064_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_064_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_064_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_064_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_064_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_064_INDEX_FORMAT 0x006503EC /* -W-4R */
|
|
#define NV_064_INDEX_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_064_INDEX_FORMAT_LE_I8 0x00000000 /* -W--V */
|
|
#define NV_064_INDEX_FORMAT_LE_I4 0x00000001 /* -W--V */
|
|
#define NV_064_LUT_OFFSET 0x006503F0 /* -W-4R */
|
|
#define NV_064_LUT_OFFSET_ARGUMENT 31:0 /* -W-UF */
|
|
#define NV_064_POINT 0x006503F4 /* -W-4R */
|
|
#define NV_064_POINT_X 15:0 /* -W-SF */
|
|
#define NV_064_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_064_SIZE_OUT 0x006503F8 /* -W-4R */
|
|
#define NV_064_SIZE_OUT_WIDTH 15:0 /* -W-UF */
|
|
#define NV_064_SIZE_OUT_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_064_SIZE_IN 0x006503FC /* -W-4R */
|
|
#define NV_064_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_064_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_064_INDICES(i) (0x00650400+(i)*4) /* -W-4A */
|
|
#define NV_064_INDICES__SIZE_1 1792 /* */
|
|
#define NV_064_INDICES_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv4_image_from_cpu.ref */
|
|
#define NV_IMAGE_FROM_CPU 0x00000061 /* ----C */
|
|
#define NV_UIMAGE 0x00511FFF:0x00510000 /* -W--D */
|
|
#define NV_UIMAGE_CTX_SWITCH 0x00510000 /* -W-4R */
|
|
#define NV_UIMAGE_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UIMAGE_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UIMAGE_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UIMAGE_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UIMAGE_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UIMAGE_NOP 0x00510100 /* -W-4R */
|
|
#define NV_UIMAGE_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_NOTIFY 0x00510104 /* -W-4R */
|
|
#define NV_UIMAGE_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UIMAGE_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UIMAGE_SET_NOTIFY 0x00510104 /* -W-4R */
|
|
#define NV_UIMAGE_SET_NOTIFY__ALIAS_1 NV_UIMAGE_NOTIFY /* */
|
|
#define NV_UIMAGE_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UIMAGE_SET_PATCH 0x0051010C /* -W-4R */
|
|
#define NV_UIMAGE_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_UIMAGE_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_UIMAGE_SET_CONTEXT_DMA_NOTIFY 0x00510180 /* -W-4R */
|
|
#define NV_UIMAGE_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_SET_IMAGE_OUTPUT 0x00510200 /* -W-4R */
|
|
#define NV_UIMAGE_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT 0x00510300 /* -W-4R */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_UIMAGE_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_UIMAGE_POINT 0x00510304 /* -W-4R */
|
|
#define NV_UIMAGE_POINT_X 15:0 /* -W-SF */
|
|
#define NV_UIMAGE_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_UIMAGE_SIZE 0x00510308 /* -W-4R */
|
|
#define NV_UIMAGE_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_UIMAGE_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_UIMAGE_SIZE_IN 0x0051030C /* -W-4R */
|
|
#define NV_UIMAGE_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_UIMAGE_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_UIMAGE_COLOR(i) (0x00510400+(i)*4) /* -W-4A */
|
|
#define NV_UIMAGE_COLOR__SIZE_1 32 /* */
|
|
#define NV_UIMAGE_COLOR_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv5_image_from_cpu.ref */
|
|
#define NV5_IMAGE_FROM_CPU 0x00000065 /* ----C */
|
|
#define NV_065 0x00661FFF:0x00660000 /* -W--D */
|
|
#define NV_065_NV5_IMAGE_FROM_CPU 0x00660000 /* -W-4R */
|
|
#define NV_065_NV5_IMAGE_FROM_CPU_HANDLE 31:0 /* -WXVF */
|
|
#define NV_065_NOP 0x00660100 /* -W-4R */
|
|
#define NV_065_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_NOTIFY 0x00660104 /* -W-4R */
|
|
#define NV_065_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_065_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_065_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_065_SET_NOTIFY 0x00660104 /* -W-4R */
|
|
#define NV_065_SET_NOTIFY__ALIAS_1 NV_065_NOTIFY /* */
|
|
#define NV_065_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_065_SET_CONTEXT_DMA_NOTIFY 0x00660180 /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_COLOR_KEY 0x00660184 /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_COLOR_KEY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_CLIP_RECTANGLE 0x00660188 /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_CLIP_RECTANGLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_PATTERN 0x0066018C /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_ROP 0x00660190 /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_BETA1 0x00660194 /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_BETA4 0x00660198 /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_CONTEXT_SURFACE 0x0066019C /* -W-4R */
|
|
#define NV_065_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_065_SET_COLOR_CONVERSION 0x006602F8 /* -W-4R */
|
|
#define NV_065_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_065_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_065_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_065_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_065_SET_OPERATION 0x006602FC /* -W-4R */
|
|
#define NV_065_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_065_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_065_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_065_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_065_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_065_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_065_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_065_SET_COLOR_FORMAT 0x00660300 /* -W-4R */
|
|
#define NV_065_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_065_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_065_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_065_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_065_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_065_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_065_POINT 0x00660304 /* -W-4R */
|
|
#define NV_065_POINT_X 15:0 /* -W-SF */
|
|
#define NV_065_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_065_SIZE_OUT 0x00660308 /* -W-4R */
|
|
#define NV_065_SIZE_OUT_WIDTH 15:0 /* -W-UF */
|
|
#define NV_065_SIZE_OUT_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_065_SIZE_IN 0x0066030C /* -W-4R */
|
|
#define NV_065_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_065_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_065_COLOR(i) (0x00660400+(i)*4) /* -W-4A */
|
|
#define NV_065_COLOR__SIZE_1 1792 /* */
|
|
#define NV_065_COLOR_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv10_image_from_cpu.ref */
|
|
#define NV10_IMAGE_FROM_CPU 0x0000008A /* ----C */
|
|
#define NV_08A 0x00541FFF:0x00540000 /* -W--D */
|
|
#define NV_08A_NV10_IMAGE_FROM_CPU 0x00540000 /* -W-4R */
|
|
#define NV_08A_NV10_IMAGE_FROM_CPU_HANDLE 31:0 /* -WXVF */
|
|
#define NV_08A_NOP 0x00540100 /* -W-4R */
|
|
#define NV_08A_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_NOTIFY 0x00540104 /* -W-4R */
|
|
#define NV_08A_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_08A_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_08A_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_08A_SET_NOTIFY 0x00540104 /* -W-4R */
|
|
#define NV_08A_SET_NOTIFY__ALIAS_1 NV_08A_NOTIFY /* */
|
|
#define NV_08A_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_08A_WAIT_FOR_IDLE 0x00540108 /* -W-4R */
|
|
#define NV_08A_WAIT_FOR_IDLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_DMA_NOTIFY 0x00540180 /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_COLOR_KEY 0x00540184 /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_COLOR_KEY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_CLIP_RECTANGLE 0x00540188 /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_CLIP_RECTANGLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_PATTERN 0x0054018C /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_ROP 0x00540190 /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_BETA1 0x00540194 /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_BETA4 0x00540198 /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_CONTEXT_SURFACE 0x0054019C /* -W-4R */
|
|
#define NV_08A_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_08A_SET_COLOR_CONVERSION 0x005402F8 /* -W-4R */
|
|
#define NV_08A_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_08A_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_08A_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_08A_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_08A_SET_OPERATION 0x005402FC /* -W-4R */
|
|
#define NV_08A_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_08A_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_08A_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_08A_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_08A_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_08A_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_08A_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_08A_SET_COLOR_FORMAT 0x00540300 /* -W-4R */
|
|
#define NV_08A_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_08A_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_08A_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_08A_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_08A_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_08A_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_08A_POINT 0x00540304 /* -W-4R */
|
|
#define NV_08A_POINT_X 15:0 /* -W-SF */
|
|
#define NV_08A_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_08A_SIZE_OUT 0x00540308 /* -W-4R */
|
|
#define NV_08A_SIZE_OUT_WIDTH 15:0 /* -W-UF */
|
|
#define NV_08A_SIZE_OUT_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_08A_SIZE_IN 0x0054030C /* -W-4R */
|
|
#define NV_08A_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_08A_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_08A_COLORA(i) (0x00540400+(i)*8) /* -W-4A */
|
|
#define NV_08A_COLORA__SIZE_1 896 /* */
|
|
#define NV_08A_COLOR_VALUE 31:0 /* -W-VF */
|
|
#define NV_08A_COLORB(i) (0x00540404+(i)*8) /* -W-4A */
|
|
#define NV_08A_COLORB__SIZE_1 896 /* */
|
|
#define NV_08A_COLORB_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv10_texture_from_cpu.ref */
|
|
#define NV10_TEXTURE_FROM_CPU 0x0000007B /* ----C */
|
|
#define NV_07B 0x00531FFF:0x00530000 /* -W--D */
|
|
#define NV_07B_NV10_TEXTURE_FROM_CPU 0x00530000 /* -W-4R */
|
|
#define NV_07B_NV10_TEXTURE_FROM_CPU_HANDLE 31:0 /* -WXVF */
|
|
#define NV_07B_NOP 0x00530100 /* -W-4R */
|
|
#define NV_07B_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_07B_PM_TRIGGER 0x00530140 /* -W-4R */
|
|
#define NV_07B_PM_TRIGGER_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_07B_NOTIFY 0x00530104 /* -W-4R */
|
|
#define NV_07B_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_07B_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_07B_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_07B_SET_NOTIFY 0x00530104 /* -W-4R */
|
|
#define NV_07B_SET_NOTIFY__ALIAS_1 NV_07B_NOTIFY /* */
|
|
#define NV_07B_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_07B_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_07B_WAIT_FOR_IDLE 0x00530108 /* -W-4R */
|
|
#define NV_07B_WAIT_FOR_IDLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_07B_SET_CONTEXT_DMA_NOTIFY 0x00530180 /* -W-4R */
|
|
#define NV_07B_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_07B_SET_CONTEXT_SURFACE 0x00530184 /* -W-4R */
|
|
#define NV_07B_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_07B_SET_COLOR_FORMAT 0x00530300 /* -W-4R */
|
|
#define NV_07B_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_07B_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_07B_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_07B_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_07B_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_07B_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_07B_POINT 0x00530304 /* -W-4R */
|
|
#define NV_07B_POINT_X 15:0 /* -W-SF */
|
|
#define NV_07B_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_07B_SIZE 0x00530308 /* -W-4R */
|
|
#define NV_07B_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_07B_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_07B_CLIP_HORIZONTAL 0x0053030C /* -W-4R */
|
|
#define NV_07B_CLIP_HORIZONTAL_X 15:0 /* -W-UF */
|
|
#define NV_07B_CLIP_HORIZONTAL_WIDTH 31:16 /* -W-UF */
|
|
#define NV_07B_CLIP_VERTICAL 0x00530310 /* -W-4R */
|
|
#define NV_07B_CLIP_VERTICAL_Y 15:0 /* -W-UF */
|
|
#define NV_07B_CLIP_VERTICAL_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_07B_COLORA(i) (0x00530400+(i)*8) /* -W-4A */
|
|
#define NV_07B_COLORA__SIZE_1 896 /* */
|
|
#define NV_07B_COLOR_VALUE 31:0 /* -W-VF */
|
|
#define NV_07B_COLORB(i) (0x00530404+(i)*8) /* -W-4A */
|
|
#define NV_07B_COLORB__SIZE_1 896 /* */
|
|
#define NV_07B_COLORB_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv4_scaled_image_from_mem.ref */
|
|
#define NV_SCALED_IMAGE_FROM_MEMORY 0x00000077 /* ----C */
|
|
#define NV_USCALED 0x004E1FFF:0x004E0000 /* -W--D */
|
|
#define NV_USCALED_CTX_SWITCH 0x004E0000 /* -W-4R */
|
|
#define NV_USCALED_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_USCALED_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_USCALED_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_USCALED_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_USCALED_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_USCALED_NOP 0x004E0100 /* -W-4R */
|
|
#define NV_USCALED_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USCALED_NOTIFY 0x004e0104 /* -W-4R */
|
|
#define NV_USCALED_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_USCALED_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_USCALED_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_USCALED_SET_NOTIFY 0x004e0104 /* -W-4R */
|
|
#define NV_USCALED_SET_NOTIFY__ALIAS_1 NV_USCALED_NOTIFY /* */
|
|
#define NV_USCALED_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USCALED_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_USCALED_SET_PATCH 0x004e010C /* -W-4R */
|
|
#define NV_USCALED_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USCALED_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_USCALED_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_USCALED_SET_CONTEXT_DMA_NOTIFY 0x004e0180 /* -W-4R */
|
|
#define NV_USCALED_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USCALED_SET_CONTEXT_DMA_IMAGE 0x004e0184 /* -W-4R */
|
|
#define NV_USCALED_SET_CONTEXT_DMA_IMAGE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USCALED_SET_IMAGE_OUTPUT 0x004e0200 /* -W-4R */
|
|
#define NV_USCALED_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USCALED_SET_COLOR_FORMAT 0x004E0300 /* -W-4R */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000001 /* -W--V */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_V8YB8U8YA8 0x00000005 /* -W--V */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_YB8V8YA8U8 0x00000006 /* -W--V */
|
|
#define NV_USCALED_SET_COLOR_FORMAT_LE_R5G6B5 0x00000007 /* -W--V */
|
|
#define NV_USCALED_CLIP_0 0x004E0308 /* -W-4R */
|
|
#define NV_USCALED_CLIP_0_X 15:0 /* -W-SF */
|
|
#define NV_USCALED_CLIP_0_Y 31:16 /* -W-SF */
|
|
#define NV_USCALED_CLIP_1 0x004E030C /* -W-4R */
|
|
#define NV_USCALED_CLIP_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_USCALED_CLIP_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_USCALED_RECTANGLE_OUT_0 0x004E0310 /* -W-4R */
|
|
#define NV_USCALED_RECTANGLE_OUT_0_X 15:0 /* -W-SF */
|
|
#define NV_USCALED_RECTANGLE_OUT_0_Y 31:16 /* -W-SF */
|
|
#define NV_USCALED_RECTANGLE_OUT_1 0x004E0314 /* -W-4R */
|
|
#define NV_USCALED_RECTANGLE_OUT_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_USCALED_RECTANGLE_OUT_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_USCALED_DELTA_DU_DX 0x004E0318 /* -W-4R */
|
|
#define NV_USCALED_DELTA_DU_DX_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_USCALED_DELTA_DU_DX_R_INT 31:20 /* -W-UF */
|
|
#define NV_USCALED_DELTA_DU_DX_R 31:0 /* -W-UF */
|
|
#define NV_USCALED_DELTA_DV_DY 0x004E031C /* -W-4R */
|
|
#define NV_USCALED_DELTA_DV_DY_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_USCALED_DELTA_DV_DY_R_INT 31:20 /* -W-UF */
|
|
#define NV_USCALED_DELTA_DV_DY_R 31:0 /* -W-UF */
|
|
#define NV_USCALED_SIZE 0x004E0400 /* -W-4R */
|
|
#define NV_USCALED_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_USCALED_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_USCALED_FORMAT 0x004E0404 /* -W-4R */
|
|
#define NV_USCALED_FORMAT_PITCH 15:0 /* -W-SF */
|
|
#define NV_USCALED_FORMAT_ORIGIN 23:16 /* -W-VF */
|
|
#define NV_USCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* -W--V */
|
|
#define NV_USCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* -W--V */
|
|
#define NV_USCALED_FORMAT_INTERPOLATOR 31:24 /* -W-VF */
|
|
#define NV_USCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* -W--V */
|
|
#define NV_USCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* -W--V */
|
|
#define NV_USCALED_OFFSET 0x004E0408 /* -W-4R */
|
|
#define NV_USCALED_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_USCALED_POINT 0x004E040C /* -W-4R */
|
|
#define NV_USCALED_POINT_V_FRACTION 11:0 /* -W-UF */
|
|
#define NV_USCALED_POINT_V_INT 15:12 /* -W-UF */
|
|
#define NV_USCALED_POINT_V_VALUE 15:0 /* -W-UF */
|
|
#define NV_USCALED_POINT_U_FRACTION 19:16 /* -W-UF */
|
|
#define NV_USCALED_POINT_U_INT 31:20 /* -W-UF */
|
|
#define NV_USCALED_POINT_U_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv5_scaled_image_from_mem.ref */
|
|
#define NV5_SCALED_IMAGE_FROM_MEMORY 0x00000063 /* ----C */
|
|
#define NV_063 0x00641FFF:0x00640000 /* -W--D */
|
|
#define NV_063_NV5_SCALED_IMAGE_FROM_MEMORY 0x00640000 /* -W-4R */
|
|
#define NV_063_NV5_SCALED_IMAGE_FROM_MEMORY_HANDLE 31:0 /* -WXVF */
|
|
#define NV_063_NOP 0x00640100 /* -W-4R */
|
|
#define NV_063_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_NOTIFY 0x00640104 /* -W-4R */
|
|
#define NV_063_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_063_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_063_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_063_SET_NOTIFY 0x00640104 /* -W-4R */
|
|
#define NV_063_SET_NOTIFY__ALIAS_1 NV_063_NOTIFY /* */
|
|
#define NV_063_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_063_SET_CONTEXT_DMA_NOTIFY 0x00640180 /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_CONTEXT_DMA_IMAGE 0x00640184 /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_DMA_IMAGE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_CONTEXT_PATTERN 0x00640188 /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_CONTEXT_ROP 0x0064018C /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_CONTEXT_BETA1 0x00640190 /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_CONTEXT_BETA4 0x00640194 /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_CONTEXT_SURFACE 0x00640198 /* -W-4R */
|
|
#define NV_063_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_063_SET_COLOR_CONVERSION 0x006402FC /* -W-4R */
|
|
#define NV_063_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_063_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_063_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_063_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT 0x00640300 /* -W-4R */
|
|
#define NV_063_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000001 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_V8YB8U8YA8 0x00000005 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_YB8V8YA8U8 0x00000006 /* -W--V */
|
|
#define NV_063_SET_COLOR_FORMAT_LE_R5G6B5 0x00000007 /* -W--V */
|
|
#define NV_063_SET_OPERATION 0x00640304 /* -W-4R */
|
|
#define NV_063_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_063_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_063_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_063_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_063_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_063_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_063_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_063_CLIP_0 0x00640308 /* -W-4R */
|
|
#define NV_063_CLIP_0_X 15:0 /* -W-SF */
|
|
#define NV_063_CLIP_0_Y 31:16 /* -W-SF */
|
|
#define NV_063_CLIP_1 0x0064030C /* -W-4R */
|
|
#define NV_063_CLIP_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_063_CLIP_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_063_RECTANGLE_OUT_0 0x00640310 /* -W-4R */
|
|
#define NV_063_RECTANGLE_OUT_0_X 15:0 /* -W-SF */
|
|
#define NV_063_RECTANGLE_OUT_0_Y 31:16 /* -W-SF */
|
|
#define NV_063_RECTANGLE_OUT_1 0x00640314 /* -W-4R */
|
|
#define NV_063_RECTANGLE_OUT_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_063_RECTANGLE_OUT_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_063_DELTA_DU_DX 0x00640318 /* -W-4R */
|
|
#define NV_063_DELTA_DU_DX_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_063_DELTA_DU_DX_R_INT 31:20 /* -W-SF */
|
|
#define NV_063_DELTA_DU_DX_R 31:0 /* -W-SF */
|
|
#define NV_063_DELTA_DV_DY 0x0064031C /* -W-4R */
|
|
#define NV_063_DELTA_DV_DY_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_063_DELTA_DV_DY_R_INT 31:20 /* -W-SF */
|
|
#define NV_063_DELTA_DV_DY_R 31:0 /* -W-SF */
|
|
#define NV_063_SIZE 0x00640400 /* -W-4R */
|
|
#define NV_063_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_063_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_063_FORMAT 0x00640404 /* -W-4R */
|
|
#define NV_063_FORMAT_PITCH 15:0 /* -W-SF */
|
|
#define NV_063_FORMAT_ORIGIN 23:16 /* -W-VF */
|
|
#define NV_063_FORMAT_ORIGIN_CENTER 0x00000001 /* -W--V */
|
|
#define NV_063_FORMAT_ORIGIN_CORNER 0x00000002 /* -W--V */
|
|
#define NV_063_FORMAT_INTERPOLATOR 31:24 /* -W-VF */
|
|
#define NV_063_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* -W--V */
|
|
#define NV_063_FORMAT_INTERPOLATOR_FOH 0x00000001 /* -W--V */
|
|
#define NV_063_OFFSET 0x00640408 /* -W-4R */
|
|
#define NV_063_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_063_POINT 0x0064040C /* -W-4R */
|
|
#define NV_063_POINT_V_FRACTION 11:0 /* -W-UF */
|
|
#define NV_063_POINT_V_INT 15:12 /* -W-UF */
|
|
#define NV_063_POINT_V_VALUE 15:0 /* -W-UF */
|
|
#define NV_063_POINT_U_FRACTION 19:16 /* -W-UF */
|
|
#define NV_063_POINT_U_INT 31:20 /* -W-UF */
|
|
#define NV_063_POINT_U_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv10_scaled_image_from_mem.ref */
|
|
#define NV10_SCALED_IMAGE_FROM_MEMORY 0x00000089 /* ----C */
|
|
#define NV_089 0x006E1FFF:0x006E0000 /* -W--D */
|
|
#define NV_089_NV10_SCALED_IMAGE_FROM_MEMORY 0x006E0000 /* -W-4R */
|
|
#define NV_089_NV10_SCALED_IMAGE_FROM_MEMORY_HANDLE 31:0 /* -WXVF */
|
|
#define NV_089_NOP 0x006E0100 /* -W-4R */
|
|
#define NV_089_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_PM_TRIGGER 0x006E0140 /* -W-4R */
|
|
#define NV_089_PM_TRIGGER_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_NOTIFY 0x006E0104 /* -W-4R */
|
|
#define NV_089_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_089_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_089_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_089_SET_NOTIFY 0x006E0104 /* -W-4R */
|
|
#define NV_089_SET_NOTIFY__ALIAS_1 NV_089_NOTIFY /* */
|
|
#define NV_089_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_089_WAIT_FOR_IDLE 0x006E0108 /* -W-4R */
|
|
#define NV_089_WAIT_FOR_IDLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_DMA_NOTIFY 0x006E0180 /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_DMA_IMAGE 0x006E0184 /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_DMA_IMAGE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_PATTERN 0x006E0188 /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_ROP 0x006E018C /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_BETA1 0x006E0190 /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_BETA4 0x006E0194 /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_CONTEXT_SURFACE 0x006E0198 /* -W-4R */
|
|
#define NV_089_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_089_SET_COLOR_CONVERSION 0x006E02FC /* -W-4R */
|
|
#define NV_089_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_089_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_089_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_089_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT 0x006E0300 /* -W-4R */
|
|
#define NV_089_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000001 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_V8YB8U8YA8 0x00000005 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_YB8V8YA8U8 0x00000006 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_R5G6B5 0x00000007 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_Y8 0x00000008 /* -W--V */
|
|
#define NV_089_SET_COLOR_FORMAT_LE_AY8 0x00000009 /* -W--V */
|
|
#define NV_089_SET_OPERATION 0x006E0304 /* -W-4R */
|
|
#define NV_089_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_089_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_089_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_089_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_089_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_089_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_089_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_089_CLIP_0 0x006E0308 /* -W-4R */
|
|
#define NV_089_CLIP_0_X 15:0 /* -W-SF */
|
|
#define NV_089_CLIP_0_Y 31:16 /* -W-SF */
|
|
#define NV_089_CLIP_1 0x006E030C /* -W-4R */
|
|
#define NV_089_CLIP_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_089_CLIP_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_089_RECTANGLE_OUT_0 0x006E0310 /* -W-4R */
|
|
#define NV_089_RECTANGLE_OUT_0_X 15:0 /* -W-SF */
|
|
#define NV_089_RECTANGLE_OUT_0_Y 31:16 /* -W-SF */
|
|
#define NV_089_RECTANGLE_OUT_1 0x006E0314 /* -W-4R */
|
|
#define NV_089_RECTANGLE_OUT_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_089_RECTANGLE_OUT_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_089_DELTA_DU_DX 0x006E0318 /* -W-4R */
|
|
#define NV_089_DELTA_DU_DX_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_089_DELTA_DU_DX_R_INT 31:20 /* -W-SF */
|
|
#define NV_089_DELTA_DU_DX_R 31:0 /* -W-SF */
|
|
#define NV_089_DELTA_DV_DY 0x006E031C /* -W-4R */
|
|
#define NV_089_DELTA_DV_DY_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_089_DELTA_DV_DY_R_INT 31:20 /* -W-SF */
|
|
#define NV_089_DELTA_DV_DY_R 31:0 /* -W-SF */
|
|
#define NV_089_SIZE 0x006E0400 /* -W-4R */
|
|
#define NV_089_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_089_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_089_FORMAT 0x006E0404 /* -W-4R */
|
|
#define NV_089_FORMAT_PITCH 15:0 /* -W-SF */
|
|
#define NV_089_FORMAT_ORIGIN 23:16 /* -W-VF */
|
|
#define NV_089_FORMAT_ORIGIN_CENTER 0x00000001 /* -W--V */
|
|
#define NV_089_FORMAT_ORIGIN_CORNER 0x00000002 /* -W--V */
|
|
#define NV_089_FORMAT_INTERPOLATOR 31:24 /* -W-VF */
|
|
#define NV_089_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* -W--V */
|
|
#define NV_089_FORMAT_INTERPOLATOR_FOH 0x00000001 /* -W--V */
|
|
#define NV_089_OFFSET 0x006E0408 /* -W-4R */
|
|
#define NV_089_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_089_POINT 0x006E040C /* -W-4R */
|
|
#define NV_089_POINT_V_FRACTION 11:0 /* -W-UF */
|
|
#define NV_089_POINT_V_INT 15:12 /* -W-UF */
|
|
#define NV_089_POINT_V_VALUE 15:0 /* -W-UF */
|
|
#define NV_089_POINT_U_FRACTION 19:16 /* -W-UF */
|
|
#define NV_089_POINT_U_INT 31:20 /* -W-UF */
|
|
#define NV_089_POINT_U_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv11_scaled_image_from_mem.ref */
|
|
#define NV11_SCALED_IMAGE_FROM_MEMORY 0x00000089 /* ----C */
|
|
#define NV_1189 0x006E1FFF:0x006E0000 /* -W--D */
|
|
#define NV_1189_NV11_SCALED_IMAGE_FROM_MEMORY 0x006E0000 /* -W-4R */
|
|
#define NV_1189_NV11_SCALED_IMAGE_FROM_MEMORY_HANDLE 31:0 /* -WXVF */
|
|
#define NV_1189_NOP 0x006E0100 /* -W-4R */
|
|
#define NV_1189_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_PM_TRIGGER 0x006E0140 /* -W-4R */
|
|
#define NV_1189_PM_TRIGGER_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_NOTIFY 0x006E0104 /* -W-4R */
|
|
#define NV_1189_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_1189_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_1189_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_1189_SET_NOTIFY 0x006E0104 /* -W-4R */
|
|
#define NV_1189_SET_NOTIFY__ALIAS_1 NV_1189_NOTIFY /* */
|
|
#define NV_1189_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_1189_WAIT_FOR_IDLE 0x006E0108 /* -W-4R */
|
|
#define NV_1189_WAIT_FOR_IDLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_DMA_NOTIFY 0x006E0180 /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_DMA_IMAGE 0x006E0184 /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_DMA_IMAGE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_PATTERN 0x006E0188 /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_ROP 0x006E018C /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_BETA1 0x006E0190 /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_BETA4 0x006E0194 /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_CONTEXT_SURFACE 0x006E0198 /* -W-4R */
|
|
#define NV_1189_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_1189_SET_COLOR_CONVERSION 0x006E02FC /* -W-4R */
|
|
#define NV_1189_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_1189_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_1189_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_1189_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT 0x006E0300 /* -W-4R */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000001 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_V8YB8U8YA8 0x00000005 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_YB8V8YA8U8 0x00000006 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_R5G6B5 0x00000007 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_Y8 0x00000008 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_AY8 0x00000009 /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_EYB8ECR8EYA8ECB8 0x0000000A /* -W--V */
|
|
#define NV_1189_SET_COLOR_FORMAT_LE_ECR8EYB8ECB8EYA8 0x0000000B /* -W--V */
|
|
#define NV_1189_SET_OPERATION 0x006E0304 /* -W-4R */
|
|
#define NV_1189_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_1189_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_1189_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_1189_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_1189_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_1189_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_1189_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_1189_CLIP_0 0x006E0308 /* -W-4R */
|
|
#define NV_1189_CLIP_0_X 15:0 /* -W-SF */
|
|
#define NV_1189_CLIP_0_Y 31:16 /* -W-SF */
|
|
#define NV_1189_CLIP_1 0x006E030C /* -W-4R */
|
|
#define NV_1189_CLIP_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_1189_CLIP_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_1189_RECTANGLE_OUT_0 0x006E0310 /* -W-4R */
|
|
#define NV_1189_RECTANGLE_OUT_0_X 15:0 /* -W-SF */
|
|
#define NV_1189_RECTANGLE_OUT_0_Y 31:16 /* -W-SF */
|
|
#define NV_1189_RECTANGLE_OUT_1 0x006E0314 /* -W-4R */
|
|
#define NV_1189_RECTANGLE_OUT_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_1189_RECTANGLE_OUT_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_1189_DELTA_DU_DX 0x006E0318 /* -W-4R */
|
|
#define NV_1189_DELTA_DU_DX_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_1189_DELTA_DU_DX_R_INT 31:20 /* -W-SF */
|
|
#define NV_1189_DELTA_DU_DX_R 31:0 /* -W-SF */
|
|
#define NV_1189_DELTA_DV_DY 0x006E031C /* -W-4R */
|
|
#define NV_1189_DELTA_DV_DY_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_1189_DELTA_DV_DY_R_INT 31:20 /* -W-SF */
|
|
#define NV_1189_DELTA_DV_DY_R 31:0 /* -W-SF */
|
|
#define NV_1189_SIZE 0x006E0400 /* -W-4R */
|
|
#define NV_1189_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_1189_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_1189_FORMAT 0x006E0404 /* -W-4R */
|
|
#define NV_1189_FORMAT_PITCH 15:0 /* -W-SF */
|
|
#define NV_1189_FORMAT_ORIGIN 23:16 /* -W-VF */
|
|
#define NV_1189_FORMAT_ORIGIN_CENTER 0x00000001 /* -W--V */
|
|
#define NV_1189_FORMAT_ORIGIN_CORNER 0x00000002 /* -W--V */
|
|
#define NV_1189_FORMAT_INTERPOLATOR 31:24 /* -W-VF */
|
|
#define NV_1189_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* -W--V */
|
|
#define NV_1189_FORMAT_INTERPOLATOR_FOH 0x00000001 /* -W--V */
|
|
#define NV_1189_OFFSET 0x006E0408 /* -W-4R */
|
|
#define NV_1189_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_1189_POINT 0x006E040C /* -W-4R */
|
|
#define NV_1189_POINT_V_FRACTION 11:0 /* -W-UF */
|
|
#define NV_1189_POINT_V_INT 15:12 /* -W-UF */
|
|
#define NV_1189_POINT_V_VALUE 15:0 /* -W-UF */
|
|
#define NV_1189_POINT_U_FRACTION 19:16 /* -W-UF */
|
|
#define NV_1189_POINT_U_INT 31:20 /* -W-UF */
|
|
#define NV_1189_POINT_U_VALUE 31:0 /* -W-UF */
|
|
/* usr_dvd_subpicture.ref */
|
|
#define NV4_DVD_SUBPICTURE 0x00000038 /* ----C */
|
|
#define NV_038 0x004F1FFF:0x004F0000 /* -W--D */
|
|
#define NV_038_NV4_DVD_SUBPICTURE 0x004F0000 /* -W-4R */
|
|
#define NV_038_NOP 0x004F0100 /* -W-4R */
|
|
#define NV_038_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_038_NOTIFY 0x004f0104 /* -W-4R */
|
|
#define NV_038_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_038_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_038_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_038_NOTIFY__ALIAS_1 NV_038_SET_NOTIFY /* */
|
|
#define NV_038_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_038_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_038_SET_CONTEXT_DMA_NOTIFY 0x004f0180 /* -W-4R */
|
|
#define NV_038_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_038_SET_CONTEXT_DMA_OVERLAY 0x004f0184 /* -W-4R */
|
|
#define NV_038_SET_CONTEXT_DMA_OVERLAY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_038_SET_CONTEXT_DMA_IMAGEIN 0x004f0188 /* -W-4R */
|
|
#define NV_038_SET_CONTEXT_DMA_IMAGEIN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_038_SET_CONTEXT_DMA_IMAGEOUT 0x004f018C /* -W-4R */
|
|
#define NV_038_SET_CONTEXT_DMA_IMAGEOUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_038_IMAGEOUT_POINT 0x004F0300 /* -W-4R */
|
|
#define NV_038_IMAGEOUT_POINT_X 15:0 /* -W-SF */
|
|
#define NV_038_IMAGEOUT_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_038_IMAGEOUT_SIZE 0x004F0304 /* -W-4R */
|
|
#define NV_038_IMAGEOUT_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_038_IMAGEOUT_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_038_IMAGEOUT_FMT 0x004F0308 /* -W-4R */
|
|
#define NV_038_IMAGEOUT_FMT_PITCH 15:0 /* -W-UF */
|
|
#define NV_038_IMAGEOUT_FMT_COLOR 31:16 /* -W-UF */
|
|
#define NV_038_IMAGEOUT_FMT_COLOR_INVALID 0x00000000 /* -W--V */
|
|
#define NV_038_IMAGEOUT_FMT_COLOR_LE_V8YB8U8YA8 0x00000001 /* -W--V */
|
|
#define NV_038_IMAGEOUT_FMT_COLOR_LE_YB8V8YA8U8 0x00000002 /* -W--V */
|
|
#define NV_038_IMAGEOUT_OFFSET 0x004F030C /* -W-4R */
|
|
#define NV_038_IMAGEOUT_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_DELTA_DU_DX 0x004F0310 /* -W-4R */
|
|
#define NV_038_IMAGEIN_DELTA_DU_DX_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_038_IMAGEIN_DELTA_DU_DX_R_INT 31:20 /* -W-UF */
|
|
#define NV_038_IMAGEIN_DELTA_DU_DX_R 31:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_DELTA_DV_DY 0x004F0314 /* -W-4R */
|
|
#define NV_038_IMAGEIN_DELTA_DV_DY_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_038_IMAGEIN_DELTA_DV_DY_R_INT 31:20 /* -W-UF */
|
|
#define NV_038_IMAGEIN_DELTA_DV_DY_R 31:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_SIZE 0x004F0318 /* -W-4R */
|
|
#define NV_038_IMAGEIN_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_038_IMAGEIN_FMT 0x004F031C /* -W-4R */
|
|
#define NV_038_IMAGEIN_FMT_PITCH 15:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_FMT_COLOR 31:16 /* -W-VF */
|
|
#define NV_038_IMAGEIN_FMT_COLOR_INVALID 0x00000000 /* -W--V */
|
|
#define NV_038_IMAGEIN_FMT_COLOR_LE_V8YB8U8YA8 0x00000001 /* -W--V */
|
|
#define NV_038_IMAGEIN_FMT_COLOR_LE_YB8V8YA8U8 0x00000002 /* -W--V */
|
|
#define NV_038_IMAGEIN_OFFSET 0x004F0320 /* -W-4R */
|
|
#define NV_038_IMAGEIN_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_POINT 0x004F0324 /* -W-4R */
|
|
#define NV_038_IMAGEIN_POINT_U_FRACTION 3:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_POINT_U_INT 15:4 /* -W-UF */
|
|
#define NV_038_IMAGEIN_POINT_U_VALUE 15:0 /* -W-UF */
|
|
#define NV_038_IMAGEIN_POINT_V_FRACTION 19:16 /* -W-UF */
|
|
#define NV_038_IMAGEIN_POINT_V_INT 31:20 /* -W-UF */
|
|
#define NV_038_IMAGEIN_POINT_V_VALUE 31:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_DELTA_DU_DX 0x004F0328 /* -W-4R */
|
|
#define NV_038_OVERLAY_DELTA_DU_DX_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_038_OVERLAY_DELTA_DU_DX_R_INT 31:20 /* -W-UF */
|
|
#define NV_038_OVERLAY_DELTA_DU_DX_R 31:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_DELTA_DV_DY 0x004F032C /* -W-4R */
|
|
#define NV_038_OVERLAY_DELTA_DV_DY_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_038_OVERLAY_DELTA_DV_DY_R_INT 31:20 /* -W-UF */
|
|
#define NV_038_OVERLAY_DELTA_DV_DY_R 31:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_SIZE 0x004F0330 /* -W-4R */
|
|
#define NV_038_OVERLAY_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_038_OVERLAY_FMT 0x004F0334 /* -W-4R */
|
|
#define NV_038_OVERLAY_FMT_PITCH 15:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_FMT_COLOR 31:16 /* -W-VF */
|
|
#define NV_038_OVERLAY_FMT_COLOR_INVALID 0x00000000 /* -W--V */
|
|
#define NV_038_OVERLAY_FMT_COLOR_LE_A8V8U8Y8 0x00000001 /* -W--V */
|
|
#define NV_038_OVERLAY_FMT_COLOR_LE_A4V6YB6A4U6YA6 0x00000002 /* -W--V */
|
|
#define NV_038_OVERLAY_FMT_COLOR_LE_TRANSPARENT 0x00000003 /* -W--V */
|
|
#define NV_038_OVERLAY_OFFSET 0x004F0338 /* -W-4R */
|
|
#define NV_038_OVERLAY_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_POINT 0x004F033C /* -W-4R */
|
|
#define NV_038_OVERLAY_POINT_U_FRACTION 3:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_POINT_U_INT 15:4 /* -W-UF */
|
|
#define NV_038_OVERLAY_POINT_U_VALUE 15:0 /* -W-UF */
|
|
#define NV_038_OVERLAY_POINT_V_FRACTION 19:16 /* -W-UF */
|
|
#define NV_038_OVERLAY_POINT_V_INT 31:20 /* -W-UF */
|
|
#define NV_038_OVERLAY_POINT_V_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv10_dvd_subpicture.ref */
|
|
#define NV10_DVD_SUBPICTURE 0x00000088 /* ----C */
|
|
#define NV_088 0x006F1FFF:0x006F0000 /* -W--D */
|
|
#define NV_088_NV4_DVD_SUBPICTURE 0x006F0000 /* -W-4R */
|
|
#define NV_088_NOP 0x006F0100 /* -W-4R */
|
|
#define NV_088_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_088_NOTIFY 0x006F0104 /* -W-4R */
|
|
#define NV_088_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_088_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_088_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_088_NOTIFY__ALIAS_1 NV_088_SET_NOTIFY /* */
|
|
#define NV_088_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_088_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_088_WAIT_FOR_IDLE 0x006F0108 /* -W-4R */
|
|
#define NV_088_WAIT_FOR_IDLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_088_SET_CONTEXT_DMA_NOTIFY 0x006F0180 /* -W-4R */
|
|
#define NV_088_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_088_SET_CONTEXT_DMA_OVERLAY 0x006F0184 /* -W-4R */
|
|
#define NV_088_SET_CONTEXT_DMA_OVERLAY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_088_SET_CONTEXT_DMA_IMAGEIN 0x006F0188 /* -W-4R */
|
|
#define NV_088_SET_CONTEXT_DMA_IMAGEIN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_088_SET_CONTEXT_DMA_IMAGEOUT 0x006F018C /* -W-4R */
|
|
#define NV_088_SET_CONTEXT_DMA_IMAGEOUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_088_IMAGEOUT_POINT 0x006F0300 /* -W-4R */
|
|
#define NV_088_IMAGEOUT_POINT_X 15:0 /* -W-SF */
|
|
#define NV_088_IMAGEOUT_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_088_IMAGEOUT_SIZE 0x006F0304 /* -W-4R */
|
|
#define NV_088_IMAGEOUT_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_088_IMAGEOUT_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_088_IMAGEOUT_FMT 0x006F0308 /* -W-4R */
|
|
#define NV_088_IMAGEOUT_FMT_PITCH 15:0 /* -W-UF */
|
|
#define NV_088_IMAGEOUT_FMT_COLOR 31:16 /* -W-UF */
|
|
#define NV_088_IMAGEOUT_FMT_COLOR_INVALID 0x00000000 /* -W--V */
|
|
#define NV_088_IMAGEOUT_FMT_COLOR_LE_V8YB8U8YA8 0x00000001 /* -W--V */
|
|
#define NV_088_IMAGEOUT_FMT_COLOR_LE_YB8V8YA8U8 0x00000002 /* -W--V */
|
|
#define NV_088_IMAGEOUT_OFFSET 0x006F030C /* -W-4R */
|
|
#define NV_088_IMAGEOUT_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_DELTA_DU_DX 0x006F0310 /* -W-4R */
|
|
#define NV_088_IMAGEIN_DELTA_DU_DX_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_088_IMAGEIN_DELTA_DU_DX_R_INT 31:20 /* -W-UF */
|
|
#define NV_088_IMAGEIN_DELTA_DU_DX_R 31:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_DELTA_DV_DY 0x006F0314 /* -W-4R */
|
|
#define NV_088_IMAGEIN_DELTA_DV_DY_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_088_IMAGEIN_DELTA_DV_DY_R_INT 31:20 /* -W-UF */
|
|
#define NV_088_IMAGEIN_DELTA_DV_DY_R 31:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_SIZE 0x006F0318 /* -W-4R */
|
|
#define NV_088_IMAGEIN_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_088_IMAGEIN_FMT 0x006F031C /* -W-4R */
|
|
#define NV_088_IMAGEIN_FMT_PITCH 15:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_FMT_COLOR 31:16 /* -W-VF */
|
|
#define NV_088_IMAGEIN_FMT_COLOR_INVALID 0x00000000 /* -W--V */
|
|
#define NV_088_IMAGEIN_FMT_COLOR_LE_V8YB8U8YA8 0x00000001 /* -W--V */
|
|
#define NV_088_IMAGEIN_FMT_COLOR_LE_YB8V8YA8U8 0x00000002 /* -W--V */
|
|
#define NV_088_IMAGEIN_OFFSET 0x006F0320 /* -W-4R */
|
|
#define NV_088_IMAGEIN_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_POINT 0x006F0324 /* -W-4R */
|
|
#define NV_088_IMAGEIN_POINT_U_FRACTION 3:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_POINT_U_INT 15:4 /* -W-UF */
|
|
#define NV_088_IMAGEIN_POINT_U_VALUE 15:0 /* -W-UF */
|
|
#define NV_088_IMAGEIN_POINT_V_FRACTION 19:16 /* -W-UF */
|
|
#define NV_088_IMAGEIN_POINT_V_INT 31:20 /* -W-UF */
|
|
#define NV_088_IMAGEIN_POINT_V_VALUE 31:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_DELTA_DU_DX 0x006F0328 /* -W-4R */
|
|
#define NV_088_OVERLAY_DELTA_DU_DX_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_088_OVERLAY_DELTA_DU_DX_R_INT 31:20 /* -W-UF */
|
|
#define NV_088_OVERLAY_DELTA_DU_DX_R 31:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_DELTA_DV_DY 0x006F032C /* -W-4R */
|
|
#define NV_088_OVERLAY_DELTA_DV_DY_R_FRACTION 19:0 /* -W-SF */
|
|
#define NV_088_OVERLAY_DELTA_DV_DY_R_INT 31:20 /* -W-UF */
|
|
#define NV_088_OVERLAY_DELTA_DV_DY_R 31:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_SIZE 0x006F0330 /* -W-4R */
|
|
#define NV_088_OVERLAY_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_088_OVERLAY_FMT 0x006F0334 /* -W-4R */
|
|
#define NV_088_OVERLAY_FMT_PITCH 15:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_FMT_COLOR 31:16 /* -W-VF */
|
|
#define NV_088_OVERLAY_FMT_COLOR_INVALID 0x00000000 /* -W--V */
|
|
#define NV_088_OVERLAY_FMT_COLOR_LE_A8V8U8Y8 0x00000001 /* -W--V */
|
|
#define NV_088_OVERLAY_FMT_COLOR_LE_A4V6YB6A4U6YA6 0x00000002 /* -W--V */
|
|
#define NV_088_OVERLAY_FMT_COLOR_LE_TRANSPARENT 0x00000003 /* -W--V */
|
|
#define NV_088_OVERLAY_OFFSET 0x006F0338 /* -W-4R */
|
|
#define NV_088_OVERLAY_OFFSET_VALUE 31:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_POINT 0x006F033C /* -W-4R */
|
|
#define NV_088_OVERLAY_POINT_U_FRACTION 3:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_POINT_U_INT 15:4 /* -W-UF */
|
|
#define NV_088_OVERLAY_POINT_U_VALUE 15:0 /* -W-UF */
|
|
#define NV_088_OVERLAY_POINT_V_FRACTION 19:16 /* -W-UF */
|
|
#define NV_088_OVERLAY_POINT_V_INT 31:20 /* -W-UF */
|
|
#define NV_088_OVERLAY_POINT_V_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv4_surface.ref */
|
|
#define NV4_SURFACE 0x00000042 /* ----C */
|
|
#define NV_042 0x00611FFF:0x00610000 /* -W--D */
|
|
#define NV_042_NV4_SURFACE 0x00610000 /* -W-4R */
|
|
#define NV_042_NOP 0x00610100 /* -W-4R */
|
|
#define NV_042_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_PM_TRIGGER 0x00610140 /* -W-4R */
|
|
#define NV_042_PM_TRIGGER_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_NOTIFY 0x00610104 /* -W-4R */
|
|
#define NV_042_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_042_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_042_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_042_SET_NOTIFY 0x00610104 /* -W-4R */
|
|
#define NV_042_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_042_SET_CONTEXT_DMA_NOTIFY 0x00610180 /* -W-4R */
|
|
#define NV_042_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_SET_CONTEXT_DMA_IMAGE_SOURCE 0x00610184 /* -W-4R */
|
|
#define NV_042_SET_CONTEXT_DMA_IMAGE_SOURCE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_SET_CONTEXT_DMA_IMAGE_DESTIN 0x00610188 /* -W-4R */
|
|
#define NV_042_SET_CONTEXT_DMA_IMAGE_DESTIN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_SET_IMAGE_OUTPUT_SOURCE 0x00610200 /* -W-4R */
|
|
#define NV_042_SET_IMAGE_OUTPUT_SOURCE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_SET_IMAGE_OUTPUT_DESTIN 0x00610204 /* -W-4R */
|
|
#define NV_042_SET_IMAGE_OUTPUT_DESTIN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_SET_IMAGE_INPUT_DESTIN(i) (0x00610208+(i)*4) /* -W-4A */
|
|
#define NV_042_SET_IMAGE_INPUT_DESTIN__SIZE_1 62 /* */
|
|
#define NV_042_SET_IMAGE_INPUT_DESTIN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_042_FMT 0x00610300 /* -W-4R */
|
|
#define NV_042_FMT_VALUE 31:0 /* -WXUF */
|
|
#define NV_042_FMT_VALUE_LE_Y8 0x00000001 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_X1R5G5B5_Z1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_X1R5G5B5_O1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_R5G6B5 0x00000004 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_Y16 0x00000005 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_X8R8G8B8_Z8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_X8R8G8B8_O8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000009 /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_A8R8G8B8 0x0000000a /* -W--V */
|
|
#define NV_042_FMT_VALUE_LE_Y32 0x0000000b /* -W--V */
|
|
#define NV_042_PITCH 0x00610304 /* -W-4R */
|
|
#define NV_042_PITCH_SOURCE 15:0 /* -WXUF */
|
|
#define NV_042_PITCH_DESTIN 31:16 /* -WXUF */
|
|
#define NV_042_OFFSET_SOURCE 0x00610308 /* -W-4R */
|
|
#define NV_042_OFFSET_SOURCE_LINADRS 31:0 /* -WIUF */
|
|
#define NV_042_OFFSET_SOURCE_LINADRS_0 0x00000000 /* -WI-V */
|
|
#define NV_042_OFFSET_DESTIN 0x0061030C /* -W-4R */
|
|
#define NV_042_OFFSET_DESTIN_LINADRS 31:0 /* -WIUF */
|
|
#define NV_042_OFFSET_DESTIN_LINADRS_0 0x00000000 /* -WI-V */
|
|
/* usr_nv10_surface.ref */
|
|
#define NV10_CONTEXT_SURFACES_2D 0x00000062 /* ----C */
|
|
#define NV_062 0x006D1FFF:0x006D0000 /* -W--D */
|
|
#define NV_062_NV10_CONTEXT_SURFACES_2D 0x006D0000 /* -W-4R */
|
|
#define NV_062_NV10_CONTEXT_SURFACES_2D_HANDLE 31:0 /* -WXVF */
|
|
#define NV_062_NOP 0x006D0100 /* -W-4R */
|
|
#define NV_062_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_PM_TRIGGER 0x006D0140 /* -W-4R */
|
|
#define NV_062_PM_TRIGGER_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_NOTIFY 0x006D0104 /* -W-4R */
|
|
#define NV_062_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_062_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_062_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_062_SET_NOTIFY 0x006D0104 /* -W-4R */
|
|
#define NV_062_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_062_WAIT_FOR_IDLE 0x006D0108 /* -W-4R */
|
|
#define NV_062_WAIT_FOR_IDLE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_SET_CONTEXT_DMA_NOTIFY 0x006D0180 /* -W-4R */
|
|
#define NV_062_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_SET_CONTEXT_DMA_IMAGE_SOURCE 0x006D0184 /* -W-4R */
|
|
#define NV_062_SET_CONTEXT_DMA_IMAGE_SOURCE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_SET_CONTEXT_DMA_IMAGE_DESTIN 0x006D0188 /* -W-4R */
|
|
#define NV_062_SET_CONTEXT_DMA_IMAGE_DESTIN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_062_FMT 0x006D0300 /* -W-4R */
|
|
#define NV_062_FMT_VALUE 31:0 /* -WXUF */
|
|
#define NV_062_FMT_VALUE_LE_Y8 0x00000001 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_X1R5G5B5_Z1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_X1R5G5B5_O1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_R5G6B5 0x00000004 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_Y16 0x00000005 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_X8R8G8B8_Z8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_X8R8G8B8_O8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000009 /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_A8R8G8B8 0x0000000a /* -W--V */
|
|
#define NV_062_FMT_VALUE_LE_Y32 0x0000000b /* -W--V */
|
|
#define NV_062_PITCH 0x006D0304 /* -W-4R */
|
|
#define NV_062_PITCH_SOURCE 15:0 /* -WXUF */
|
|
#define NV_062_PITCH_DESTIN 31:16 /* -WXUF */
|
|
#define NV_062_OFFSET_SOURCE 0x006D0308 /* -W-4R */
|
|
#define NV_062_OFFSET_SOURCE_LINADRS 31:0 /* -WIUF */
|
|
#define NV_062_OFFSET_SOURCE_LINADRS_0 0x00000000 /* -WI-V */
|
|
#define NV_062_OFFSET_DESTIN 0x006D030C /* -W-4R */
|
|
#define NV_062_OFFSET_DESTIN_LINADRS 31:0 /* -WIUF */
|
|
#define NV_062_OFFSET_DESTIN_LINADRS_0 0x00000000 /* -WI-V */
|
|
/* usr_nv4_swizzled_surface.ref */
|
|
#define NV4_SWIZZLED_SURFACE 0x00000052 /* ----C */
|
|
#define NV_052 0x00631FFF:0x00630000 /* -W--D */
|
|
#define NV_052_NV4_SWIZZLED_SURFACE 0x00630000 /* -W-4R */
|
|
#define NV_052_NOP 0x00630100 /* -W-4R */
|
|
#define NV_052_NOP_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_052_NOTIFY 0x00630104 /* -W-4R */
|
|
#define NV_052_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_052_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_052_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_052_NOTIFY__ALIAS_1 NV_052_SET_NOTIFY /* */
|
|
#define NV_052_SET_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_052_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_052_SET_CONTEXT_DMA_NOTIFY 0x00630180 /* -W-4R */
|
|
#define NV_052_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_052_SET_CONTEXT_DMA_IMAGE 0x00630184 /* -W-4R */
|
|
#define NV_052_SET_CONTEXT_DMA_IMAGE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_052_SET_IMAGE_OUTPUT 0x00630200 /* -W-4R */
|
|
#define NV_052_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_052_SET_IMAGE_INPUT(i) (0x00630204+(i)*4) /* -W-4A */
|
|
#define NV_052_SET_IMAGE_INPUT__SIZE_1 63 /* */
|
|
#define NV_052_SET_IMAGE_INPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_052_SET_FORMAT 0x00630300 /* -W-4R */
|
|
#define NV_052_SET_FORMAT_COLOR 15:0 /* -WXVF */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_Y8 0x00000001 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_R5G6B5 0x00000004 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_Y16 0x00000005 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000008 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000009 /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_A8R8G8B8 0x0000000a /* -W--V */
|
|
#define NV_052_SET_FORMAT_COLOR_LE_Y32 0x0000000b /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH 23:16 /* -WXVF */
|
|
#define NV_052_SET_FORMAT_WIDTH_1 0x00000000 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_2 0x00000001 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_4 0x00000002 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_8 0x00000003 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_16 0x00000004 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_32 0x00000005 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_64 0x00000006 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_128 0x00000007 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_256 0x00000008 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_512 0x00000009 /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_1024 0x0000000a /* -W--V */
|
|
#define NV_052_SET_FORMAT_WIDTH_2048 0x0000000b /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT 31:24 /* -WXVF */
|
|
#define NV_052_SET_FORMAT_HEIGHT_1 0x00000000 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_2 0x00000001 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_4 0x00000002 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_8 0x00000003 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_16 0x00000004 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_32 0x00000005 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_64 0x00000006 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_128 0x00000007 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_256 0x00000008 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_512 0x00000009 /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_1024 0x0000000a /* -W--V */
|
|
#define NV_052_SET_FORMAT_HEIGHT_2048 0x0000000b /* -W--V */
|
|
#define NV_052_SET_OFFSET 0x00630304 /* -W-4R */
|
|
#define NV_052_SET_OFFSET_LINADRS 31:0 /* -WIUF */
|
|
#define NV_052_SET_OFFSET_LINADRS_0 0x00000000 /* -WI-V */
|
|
/* usr_nv3_surface.ref */
|
|
#define NV3_SURFACE_0 0x00000058 /* ----C */
|
|
#define NV3_SURFACE_1 0x00000059 /* ----C */
|
|
#define NV3_SURFACE_2 0x0000005A /* ----C */
|
|
#define NV3_SURFACE_3 0x0000005B /* ----C */
|
|
#define NV_UINMEM 0x005C1FFF:0x005C0000 /* -W--D */
|
|
#define NV_UINMEM_CTX_SWITCH 0x005C0000 /* -W-4R */
|
|
#define NV_UINMEM_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_UINMEM_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_UINMEM_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_UINMEM_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_UINMEM_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_UINMEM_NOP 0x005C0100 /* -W-4R */
|
|
#define NV_UINMEM_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UINMEM_NOTIFY 0x005C0104 /* -W-4R */
|
|
#define NV_UINMEM_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UINMEM_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UINMEM_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UINMEM_SET_NOTIFY 0x005C0104 /* -W-4R */
|
|
#define NV_UINMEM_SET_NOTIFY__ALIAS_1 NV_UINMEM_NOTIFY /* */
|
|
#define NV_UINMEM_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UINMEM_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UINMEM_SET_CONTEXT_DMA_NOTIFY 0x005C0180 /* -W-4R */
|
|
#define NV_UINMEM_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UINMEM_SET_CONTEXT_DMA_IMAGE 0x005C0184 /* -W-4R */
|
|
#define NV_UINMEM_SET_CONTEXT_DMA_IMAGE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UINMEM_SET_IMAGE_OUTPUT 0x005C0200 /* -W-4R */
|
|
#define NV_UINMEM_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UINMEM_SET_IMAGE_INPUT(i) (0x005C0204+(i)*4) /* -W-4A */
|
|
#define NV_UINMEM_SET_IMAGE_INPUT__SIZE_1 63 /* */
|
|
#define NV_UINMEM_SET_IMAGE_INPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UINMEM_FORMAT 0x005C0300 /* -W-4R */
|
|
#define NV_UINMEM_FORMAT_VALUE 31:0 /* -WXUF */
|
|
#define NV_UINMEM_FORMAT_VALUE_LE_Y8 0x01010000 /* -W--V */
|
|
#define NV_UINMEM_FORMAT_VALUE_LE_Y16 0x01010001 /* -W--V */
|
|
#define NV_UINMEM_FORMAT_VALUE_LE_X1R5G5B5_Z1R5G5B5 0x01000000 /* -W--V */
|
|
#define NV_UINMEM_FORMAT_VALUE_LE_X8R8G8B8_Z8R8G8B8 0x00000001 /* -W--V */
|
|
#define NV_UINMEM_PITCH 0x005C0308 /* -W-4R */
|
|
#define NV_UINMEM_PITCH_VALUE 15:0 /* -WXUF */
|
|
#define NV_UINMEM_OFFSET 0x005C030C /* -W-4R */
|
|
#define NV_UINMEM_OFFSET_LINADRS 22:0 /* -WIUF */
|
|
#define NV_UINMEM_OFFSET_LINADRS_0 0x00000000 /* -WI-V */
|
|
/* usr_nv4_gdi_rectangle_text.ref */
|
|
#define NV4_GDI_RECTANGLE_TEXT 0x0000004A /* ----C */
|
|
#define NV_04A 0x004C1FFF:0x004C0000 /* -W--D */
|
|
#define NV_04A_NV4_GDI_RECTANGLE_TEXT 0x004C0000 /* -W-4R */
|
|
#define NV_04A_NOP 0x004C0100 /* -W-4R */
|
|
#define NV_04A_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04A_PM_TRIGGER 0x004C0140 /* -W-4R */
|
|
#define NV_04A_PM_TRIGGER_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04A_NOTIFY 0x004C0104 /* -W-4R */
|
|
#define NV_04A_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_04A_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_04A_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_04A_SET_PATCH 0x004C010C /* -W-4R */
|
|
#define NV_04A_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04A_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_04A_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_04A_SET_CONTEXT_DMA_NOTIFY 0x004C0180 /* -W-4R */
|
|
#define NV_04A_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04A_SET_CONTEXT_DMA_FONTS 0x004C0184 /* -W-4R */
|
|
#define NV_04A_SET_CONTEXT_DMA_FONTS_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04A_SET_IMAGE_OUTPUT 0x004C0200 /* -W-4R */
|
|
#define NV_04A_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04A_SET_COLOR_FORMAT 0x004C0300 /* -W-4R */
|
|
#define NV_04A_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_04A_SET_COLOR_FORMAT_LE_X16R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_04A_SET_COLOR_FORMAT_LE_X17R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_04A_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_04A_SET_MONOCHROME_FORMAT 0x004C0304 /* -W-4R */
|
|
#define NV_04A_SET_MONOCHROME_FORMAT_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_SET_MONOCHROME_FORMAT_VALUE_CGA6_M1 0x00000001 /* -W--V */
|
|
#define NV_04A_SET_MONOCHROME_FORMAT_VALUE_LE_M1 0x00000002 /* -W--V */
|
|
#define NV_04A_COLOR1_A 0x004C03FC /* -W-4R */
|
|
#define NV_04A_COLOR1_A_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_POINT(i) (0x004C0400+(i)*8) /* -W-4A */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_POINT__SIZE_1 32 /* */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_POINT_Y 15:0 /* -W-SF */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_POINT_X 31:16 /* -W-SF */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_SIZE(i) (0x004C0404+(i)*8) /* -W-4A */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_SIZE__SIZE_1 32 /* */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_SIZE_HEIGHT 15:0 /* -W-UF */
|
|
#define NV_04A_UNCLIPPED_RECTANGLE_SIZE_WIDTH 31:16 /* -W-UF */
|
|
#define NV_04A_CLIP_B_POINT0 0x004C05F4 /* -W-4R */
|
|
#define NV_04A_CLIP_B_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_B_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04A_CLIP_B_POINT1 0x004C05F8 /* -W-4R */
|
|
#define NV_04A_CLIP_B_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_B_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04A_COLOR1_B 0x004C05FC /* -W-4R */
|
|
#define NV_04A_COLOR1_B_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_0(i) (0x004C0600+(i)*8) /* -W-4A */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_0__SIZE_1 32 /* */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_0_TOP 31:16 /* -W-SF */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_1(i) (0x004C0604+(i)*8) /* -W-4A */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_1__SIZE_1 32 /* */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIPPED_RECTANGLE_POINT_1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04A_CLIP_C_POINT0 0x004C07EC /* -W-4R */
|
|
#define NV_04A_CLIP_C_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_C_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04A_CLIP_C_POINT1 0x004C07F0 /* -W-4R */
|
|
#define NV_04A_CLIP_C_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_C_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04A_COLOR1_C 0x004C07F4 /* -W-4R */
|
|
#define NV_04A_COLOR1_C_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_SIZE_C 0x004C07F8 /* -W-4R */
|
|
#define NV_04A_SIZE_C_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04A_SIZE_C_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04A_POINT_C 0x004C07FC /* -W-4R */
|
|
#define NV_04A_POINT_C_X 15:0 /* -W-SF */
|
|
#define NV_04A_POINT_C_Y 31:16 /* -W-SF */
|
|
#define NV_04A_MONOCHROME_COLOR1_C(i) (0x004C0800+(i)*4) /* -W-4A */
|
|
#define NV_04A_MONOCHROME_COLOR1_C__SIZE_1 128 /* */
|
|
#define NV_04A_MONOCHROME_COLOR1_C_BITMAP 31:0 /* -W-VF */
|
|
#define NV_04A_CLIP_E_POINT0 0x004C0BE4 /* -W-4R */
|
|
#define NV_04A_CLIP_E_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_E_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04A_CLIP_E_POINT1 0x004C0BE8 /* -W-4R */
|
|
#define NV_04A_CLIP_E_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_E_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04A_COLOR0_E 0x004C0BEC /* -W-4R */
|
|
#define NV_04A_COLOR0_E_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_COLOR1_E 0x004C0BF0 /* -W-4R */
|
|
#define NV_04A_COLOR1_E_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_SIZE_IN_E 0x004C0BF4 /* -W-4R */
|
|
#define NV_04A_SIZE_IN_E_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04A_SIZE_IN_E_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04A_SIZE_OUT_E 0x004C0BF8 /* -W-4R */
|
|
#define NV_04A_SIZE_OUT_E_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04A_SIZE_OUT_E_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04A_POINT_E 0x004C0BFC /* -W-4R */
|
|
#define NV_04A_POINT_E_X 15:0 /* -W-SF */
|
|
#define NV_04A_POINT_E_Y 31:16 /* -W-SF */
|
|
#define NV_04A_MONOCHROME_COLOR01_E(i) (0x004C0C00+(i)*4) /* -W-4A */
|
|
#define NV_04A_MONOCHROME_COLOR01_E__SIZE_1 128 /* */
|
|
#define NV_04A_MONOCHROME_COLOR01_E_BITMAP 31:0 /* -W-VF */
|
|
#define NV_04A_FONT_F 0x004C0FF0 /* -W-4R */
|
|
#define NV_04A_FONT_F_OFFSET 27:0 /* -W-UF */
|
|
#define NV_04A_FONT_F_PITCH 31:28 /* -W-VF */
|
|
#define NV_04A_FONT_F_PITCH_8 0x00000003 /* -W--V */
|
|
#define NV_04A_FONT_F_PITCH_16 0x00000004 /* -W--V */
|
|
#define NV_04A_FONT_F_PITCH_32 0x00000005 /* -W--V */
|
|
#define NV_04A_FONT_F_PITCH_64 0x00000006 /* -W--V */
|
|
#define NV_04A_FONT_F_PITCH_128 0x00000007 /* -W--V */
|
|
#define NV_04A_FONT_F_PITCH_256 0x00000008 /* -W--V */
|
|
#define NV_04A_FONT_F_PITCH_512 0x00000009 /* -W--V */
|
|
#define NV_04A_CLIP_F_POINT0 0x004C0FF4 /* -W-4R */
|
|
#define NV_04A_CLIP_F_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_F_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04A_CLIP_F_POINT1 0x004C0FF8 /* -W-4R */
|
|
#define NV_04A_CLIP_F_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_F_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04A_COLOR1_F 0x004C0FFC /* -W-4A */
|
|
#define NV_04A_COLOR1_F_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_CHARACTER_COLOR1_F(i) (0x004C1000+(i)*4) /* -W-4A */
|
|
#define NV_04A_CHARACTER_COLOR1_F__SIZE_1 256 /* */
|
|
#define NV_04A_CHARACTER_COLOR1_F_INDEX 7:0 /* -W-UF */
|
|
#define NV_04A_CHARACTER_COLOR1_F_X 19:8 /* -W-SF */
|
|
#define NV_04A_CHARACTER_COLOR1_F_Y 31:20 /* -W-SF */
|
|
#define NV_04A_FONT_G 0x004C17F0 /* -W-4R */
|
|
#define NV_04A_FONT_G_OFFSET 27:0 /* -W-UF */
|
|
#define NV_04A_FONT_G_PITCH 31:28 /* -W-VF */
|
|
#define NV_04A_FONT_G_PITCH_8 0x00000003 /* -W--V */
|
|
#define NV_04A_FONT_G_PITCH_16 0x00000004 /* -W--V */
|
|
#define NV_04A_FONT_G_PITCH_32 0x00000005 /* -W--V */
|
|
#define NV_04A_FONT_G_PITCH_64 0x00000006 /* -W--V */
|
|
#define NV_04A_FONT_G_PITCH_128 0x00000007 /* -W--V */
|
|
#define NV_04A_FONT_G_PITCH_256 0x00000008 /* -W--V */
|
|
#define NV_04A_FONT_G_PITCH_512 0x00000009 /* -W--V */
|
|
#define NV_04A_CLIP_G_POINT0 0x004C17F4 /* -W-4R */
|
|
#define NV_04A_CLIP_G_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_G_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04A_CLIP_G_POINT1 0x004C17F8 /* -W-4R */
|
|
#define NV_04A_CLIP_G_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04A_CLIP_G_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04A_COLOR1_G 0x004C17FC /* -W-4A */
|
|
#define NV_04A_COLOR1_G_VALUE 31:0 /* -W-VF */
|
|
#define NV_04A_CHARACTER_COLOR1_G_POINT(i) (0x004C1800+(i)*8) /* -W-4A */
|
|
#define NV_04A_CHARACTER_COLOR1_G_POINT__SIZE_1 256 /* */
|
|
#define NV_04A_CHARACTER_COLOR1_G_POINT_X 15:0 /* -W-SF */
|
|
#define NV_04A_CHARACTER_COLOR1_G_POINT_Y 31:16 /* -W-SF */
|
|
#define NV_04A_CHARACTER_COLOR1_G_INDEX(i) (0x004C1804+(i)*8) /* -W-4A */
|
|
#define NV_04A_CHARACTER_COLOR1_G_INDEX__SIZE_1 256 /* */
|
|
#define NV_04A_CHARACTER_COLOR1_G_INDEX_VALUE 31:0 /* -W-UF */
|
|
/* usr_mem_to_mem.ref */
|
|
#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 /* ----C */
|
|
#define NV_UMEMFMT 0x004D1FFF:0x004D0000 /* -W--D */
|
|
#define NV_UMEMFMT_CTX_SWITCH 0x004D0000 /* -W-4R */
|
|
#define NV_UMEMFMT_NOP 0x004D0100 /* -W-4R */
|
|
#define NV_UMEMFMT_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UMEMFMT_NOTIFY 0x004D0104 /* -W-4R */
|
|
#define NV_UMEMFMT_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_UMEMFMT_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_UMEMFMT_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_UMEMFMT_SET_NOTIFY 0x004D0104 /* -W-4R */
|
|
#define NV_UMEMFMT_SET_NOTIFY__ALIAS_1 NV_UMEMFMT_NOTIFY /* */
|
|
#define NV_UMEMFMT_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_UMEMFMT_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_UMEMFMT_SET_CONTEXT_DMA_NOTIFY 0x004D0180 /* -W-4R */
|
|
#define NV_UMEMFMT_SET_CONTEXT_DMA_NOTIFY_INSTANCE 15:0 /* -W-VF */
|
|
#define NV_UMEMFMT_SET_CONTEXT_DMA_BUFFER_IN 0x004D0184 /* -W-4R */
|
|
#define NV_UMEMFMT_SET_CONTEXT_DMA_BUFFER_IN_INSTANCE 15:0 /* -W-VF */
|
|
#define NV_UMEMFMT_SET_CONTEXT_DMA_BUFFER_OUT 0x004D0188 /* -W-4R */
|
|
#define NV_UMEMFMT_SET_CONTEXT_DMA_BUFFER_OUT_INSTANCE 15:0 /* -W-VF */
|
|
#define NV_UMEMFMT_OFFSET_IN 0x004D030C /* -W-4R */
|
|
#define NV_UMEMFMT_OFFSET_IN_VALUE 31:0 /* -W-UF */
|
|
#define NV_UMEMFMT_OFFSET_OUT 0x004D0310 /* -W-4R */
|
|
#define NV_UMEMFMT_OFFSET_OUT_VALUE 31:0 /* -W-UF */
|
|
#define NV_UMEMFMT_PITCH_IN 0x004D0314 /* -W-4R */
|
|
#define NV_UMEMFMT_PITCH_IN_VALUE 31:0 /* -W-SF */
|
|
#define NV_UMEMFMT_PITCH_OUT 0x004D0318 /* -W-4R */
|
|
#define NV_UMEMFMT_PITCH_OUT_VALUE 31:0 /* -W-SF */
|
|
#define NV_UMEMFMT_LINE_LENGTH_IN 0x004D031C /* -W-4R */
|
|
#define NV_UMEMFMT_LINE_LENGTH_IN_VALUE 31:0 /* -W-UF */
|
|
#define NV_UMEMFMT_LINE_COUNT 0x004D0320 /* -W-4R */
|
|
#define NV_UMEMFMT_LINE_COUNT_VALUE 31:0 /* -W-UF */
|
|
#define NV_UMEMFMT_FORMAT 0x004D0324 /* -W-4R */
|
|
#define NV_UMEMFMT_FORMAT_INPUT_INC 2:0 /* -W-UF */
|
|
#define NV_UMEMFMT_FORMAT_INPUT_INC_1 0x00000001 /* -WIUV */
|
|
#define NV_UMEMFMT_FORMAT_INPUT_INC_2 0x00000002 /* -W-UV */
|
|
#define NV_UMEMFMT_FORMAT_INPUT_INC_4 0x00000004 /* -W-UV */
|
|
#define NV_UMEMFMT_FORMAT_OUTPUT_INC 10:8 /* -W-UF */
|
|
#define NV_UMEMFMT_FORMAT_OUTPUT_INC_1 0x00000001 /* -WIUV */
|
|
#define NV_UMEMFMT_FORMAT_OUTPUT_INC_2 0x00000002 /* -W-UV */
|
|
#define NV_UMEMFMT_FORMAT_OUTPUT_INC_4 0x00000004 /* -W-UV */
|
|
#define NV_UMEMFMT_BUF_NOTIFY 0x004D0328 /* -W-4R */
|
|
#define NV_UMEMFMT_BUF_NOTIFY_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv4_stretched_image_from_cpu.ref */
|
|
#define NV_STRETCHED_IMAGE_FROM_CPU 0x00000076 /* ----C */
|
|
#define NV_USTRTCH 0x00551FFF:0x00550000 /* -W--D */
|
|
#define NV_USTRTCH_CTX_SWITCH 0x00550000 /* -W-4R */
|
|
#define NV_USTRTCH_CTX_SWITCH_INSTANCE 15:0 /* -W-UF */
|
|
#define NV_USTRTCH_CTX_SWITCH_CHID 22:16 /* -W-UF */
|
|
#define NV_USTRTCH_CTX_SWITCH_VOLATILE 31:31 /* -W-VF */
|
|
#define NV_USTRTCH_CTX_SWITCH_VOLATILE_IGNORE 0x00000000 /* -W--V */
|
|
#define NV_USTRTCH_CTX_SWITCH_VOLATILE_RESET 0x00000001 /* -W--V */
|
|
#define NV_USTRTCH_NOP 0x00550100 /* -W-4R */
|
|
#define NV_USTRTCH_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_NOTIFY 0x00550104 /* -W-4R */
|
|
#define NV_USTRTCH_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_USTRTCH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_USTRTCH_SET_NOTIFY 0x00550104 /* -W-4R */
|
|
#define NV_USTRTCH_SET_NOTIFY__ALIAS_1 NV_USTRTCH_NOTIFY /* */
|
|
#define NV_USTRTCH_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_USTRTCH_SET_PATCH 0x0055010C /* -W-4R */
|
|
#define NV_USTRTCH_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_USTRTCH_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_USTRTCH_SET_CONTEXT_DMA_NOTIFY 0x00550180 /* -W-4R */
|
|
#define NV_USTRTCH_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_SET_IMAGE_OUTPUT 0x00550200 /* -W-4R */
|
|
#define NV_USTRTCH_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT 0x00550300 /* -W-4R */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_USTRTCH_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_USTRTCH_SIZE_IN 0x00550304 /* -W-4R */
|
|
#define NV_USTRTCH_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_USTRTCH_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_USTRTCH_DELTA_DX_DU 0x00550308 /* -W-4R */
|
|
#define NV_USTRTCH_DELTA_DX_DU_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_USTRTCH_DELTA_DX_DU_R_INT 31:20 /* -W-UF */
|
|
#define NV_USTRTCH_DELTA_DX_DU_R 31:0 /* -W-UF */
|
|
#define NV_USTRTCH_DELTA_DY_DV 0x0055030C /* -W-4R */
|
|
#define NV_USTRTCH_DELTA_DY_DV_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_USTRTCH_DELTA_DY_DV_R_INT 31:20 /* -W-UF */
|
|
#define NV_USTRTCH_DELTA_DY_DV_R 31:0 /* -W-UF */
|
|
#define NV_USTRTCH_CLIP_0 0x00550310 /* -W-4R */
|
|
#define NV_USTRTCH_CLIP_0_X 15:0 /* -W-SF */
|
|
#define NV_USTRTCH_CLIP_0_Y 31:16 /* -W-SF */
|
|
#define NV_USTRTCH_CLIP_1 0x00550314 /* -W-4R */
|
|
#define NV_USTRTCH_CLIP_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_USTRTCH_CLIP_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_USTRTCH_POINT12D4 0x00550318 /* -W-4R */
|
|
#define NV_USTRTCH_POINT12D4_X_FRACTION 3:0 /* -W-SF */
|
|
#define NV_USTRTCH_POINT12D4_X_INT 15:4 /* -W-SF */
|
|
#define NV_USTRTCH_POINT12D4_X 15:0 /* -W-SF */
|
|
#define NV_USTRTCH_POINT12D4_Y_FRACTION 19:16 /* -W-SF */
|
|
#define NV_USTRTCH_POINT12D4_Y_INT 31:20 /* -W-SF */
|
|
#define NV_USTRTCH_POINT12D4_Y 31:16 /* -W-SF */
|
|
#define NV_USTRTCH_COLOR(i) (0x00550400+(i)*4) /* -W-4A */
|
|
#define NV_USTRTCH_COLOR__SIZE_1 1792 /* */
|
|
#define NV_USTRTCH_COLOR_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv5_stretched_image_from_cpu.ref */
|
|
#define NV5_STRETCHED_IMAGE_FROM_CPU 0x00000066 /* ----C */
|
|
#define NV_066 0x00671FFF:0x00670000 /* -W--D */
|
|
#define NV_066_NV5_STRETCHED_IMAGE_FROM_CPU 0x00670000 /* -W-4R */
|
|
#define NV_066_NV5_STRETCHED_IMAGE_FROM_CPU_HANDLE 31:0 /* -WXVF */
|
|
#define NV_066_NOP 0x00670100 /* -W-4R */
|
|
#define NV_066_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_NOTIFY 0x00670104 /* -W-4R */
|
|
#define NV_066_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_066_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_066_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_066_SET_NOTIFY 0x00670104 /* -W-4R */
|
|
#define NV_066_SET_NOTIFY__ALIAS_1 NV_066_NOTIFY /* */
|
|
#define NV_066_SET_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_NOTIFY_PARAMETER_WRITE 0x00000000 /* -W--V */
|
|
#define NV_066_SET_CONTEXT_DMA_NOTIFY 0x00670180 /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_CONTEXT_COLOR_KEY 0x00670184 /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_COLOR_KEY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_CONTEXT_PATTERN 0x00670188 /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_PATTERN_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_CONTEXT_ROP 0x0067018C /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_ROP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_CONTEXT_BETA1 0x00670190 /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_BETA1_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_CONTEXT_BETA4 0x00670194 /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_BETA4_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_CONTEXT_SURFACE 0x00670198 /* -W-4R */
|
|
#define NV_066_SET_CONTEXT_SURFACE_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_066_SET_COLOR_CONVERSION 0x006702F8 /* -W-4R */
|
|
#define NV_066_SET_COLOR_CONVERSION_TYPE 31:0 /* -W-VF */
|
|
#define NV_066_SET_COLOR_CONVERSION_TYPE_DITHER 0x00000000 /* -W--V */
|
|
#define NV_066_SET_COLOR_CONVERSION_TYPE_TRUNCATE 0x00000001 /* -W--V */
|
|
#define NV_066_SET_COLOR_CONVERSION_TYPE_SUBTR_TRUNCATE 0x00000002 /* -W--V */
|
|
#define NV_066_SET_OPERATION 0x006702FC /* -W-4R */
|
|
#define NV_066_SET_OPERATION_MODE 31:0 /* -W-VF */
|
|
#define NV_066_SET_OPERATION_MODE_SRCCOPY_AND 0x00000000 /* -W--V */
|
|
#define NV_066_SET_OPERATION_MODE_ROP_AND 0x00000001 /* -W--V */
|
|
#define NV_066_SET_OPERATION_MODE_BLEND_AND 0x00000002 /* -W--V */
|
|
#define NV_066_SET_OPERATION_MODE_SRCCOPY 0x00000003 /* -W--V */
|
|
#define NV_066_SET_OPERATION_MODE_SRCCOPY_PREMULT 0x00000004 /* -W--V */
|
|
#define NV_066_SET_OPERATION_MODE_BLEND_PREMULT 0x00000005 /* -W--V */
|
|
#define NV_066_SET_COLOR_FORMAT 0x00670300 /* -W-4R */
|
|
#define NV_066_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_066_SET_COLOR_FORMAT_LE_R5G6B5 0x00000001 /* -W--V */
|
|
#define NV_066_SET_COLOR_FORMAT_LE_A1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_066_SET_COLOR_FORMAT_LE_X1R5G5B5 0x00000003 /* -W--V */
|
|
#define NV_066_SET_COLOR_FORMAT_LE_A8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_066_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_066_SIZE_IN 0x00670304 /* -W-4R */
|
|
#define NV_066_SIZE_IN_WIDTH 15:0 /* -W-UF */
|
|
#define NV_066_SIZE_IN_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_066_DELTA_DX_DU 0x00670308 /* -W-4R */
|
|
#define NV_066_DELTA_DX_DU_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_066_DELTA_DX_DU_R_INT 31:20 /* -W-UF */
|
|
#define NV_066_DELTA_DX_DU_R 31:0 /* -W-UF */
|
|
#define NV_066_DELTA_DY_DV 0x0067030C /* -W-4R */
|
|
#define NV_066_DELTA_DY_DV_R_FRACTION 19:0 /* -W-UF */
|
|
#define NV_066_DELTA_DY_DV_R_INT 31:20 /* -W-UF */
|
|
#define NV_066_DELTA_DY_DV_R 31:0 /* -W-UF */
|
|
#define NV_066_CLIP_0 0x00670310 /* -W-4R */
|
|
#define NV_066_CLIP_0_X 15:0 /* -W-SF */
|
|
#define NV_066_CLIP_0_Y 31:16 /* -W-SF */
|
|
#define NV_066_CLIP_1 0x00670314 /* -W-4R */
|
|
#define NV_066_CLIP_1_WIDTH 15:0 /* -W-UF */
|
|
#define NV_066_CLIP_1_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_066_POINT12D4 0x00670318 /* -W-4R */
|
|
#define NV_066_POINT12D4_X_FRACTION 3:0 /* -W-SF */
|
|
#define NV_066_POINT12D4_X_INT 15:4 /* -W-SF */
|
|
#define NV_066_POINT12D4_X 15:0 /* -W-SF */
|
|
#define NV_066_POINT12D4_Y_FRACTION 19:16 /* -W-SF */
|
|
#define NV_066_POINT12D4_Y_INT 31:20 /* -W-SF */
|
|
#define NV_066_POINT12D4_Y 31:16 /* -W-SF */
|
|
#define NV_066_COLOR(i) (0x00670400+(i)*4) /* -W-4A */
|
|
#define NV_066_COLOR__SIZE_1 1792 /* */
|
|
#define NV_066_COLOR_VALUE 31:0 /* -W-VF */
|
|
/* usr_nv3_gdi_rectangle_text.ref */
|
|
#define NV3_GDI_RECTANGLE_TEXT 0x0000004B /* ----C */
|
|
#define NV_04B 0x006B1FFF:0x006B0000 /* -W--D */
|
|
#define NV_04B_NV3_GDI_RECTANGLE_TEXT 0x006B0000 /* -W-4R */
|
|
#define NV_04B_NOP 0x006B0100 /* -W-4R */
|
|
#define NV_04B_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04B_NOTIFY 0x006B0104 /* -W-4R */
|
|
#define NV_04B_NOTIFY_STYLE 31:0 /* -W-VF */
|
|
#define NV_04B_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_04B_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_04B_SET_PATCH 0x006B010C /* -W-4R */
|
|
#define NV_04B_SET_PATCH_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04B_SET_PATCH_PARAMETER_INVALIDATE 0x00000000 /* -W--V */
|
|
#define NV_04B_SET_PATCH_PARAMETER_VALIDATE 0x00000001 /* -W--V */
|
|
#define NV_04B_SET_CONTEXT_DMA_NOTIFY 0x006B0180 /* -W-4R */
|
|
#define NV_04B_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04B_SET_IMAGE_OUTPUT 0x006B0200 /* -W-4R */
|
|
#define NV_04B_SET_IMAGE_OUTPUT_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_04B_SET_COLOR_FORMAT 0x006B0300 /* -W-4R */
|
|
#define NV_04B_SET_COLOR_FORMAT_LE 31:0 /* -W-VF */
|
|
#define NV_04B_SET_COLOR_FORMAT_LE_X24Y8 0x00000001 /* -W--V */
|
|
#define NV_04B_SET_COLOR_FORMAT_LE_X17R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_04B_SET_COLOR_FORMAT_LE_X8R8G8B8 0x00000003 /* -W--V */
|
|
#define NV_04B_SET_MONOCHROME_FORMAT 0x006B0304 /* -W-4R */
|
|
#define NV_04B_SET_MONOCHROME_FORMAT_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_SET_MONOCHROME_FORMAT_VALUE_CGA6_M1 0x00000001 /* -W--V */
|
|
#define NV_04B_SET_MONOCHROME_FORMAT_VALUE_LE_M1 0x00000002 /* -W--V */
|
|
#define NV_04B_COLOR1_A 0x006B03FC /* -W-4R */
|
|
#define NV_04B_COLOR1_A_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_POINT(i) (0x006B0400+(i)*8) /* -W-4A */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_POINT__SIZE_1 64 /* */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_POINT_Y 15:0 /* -W-SF */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_POINT_X 31:16 /* -W-SF */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_SIZE(i) (0x006B0404+(i)*8) /* -W-4A */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_SIZE__SIZE_1 64 /* */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_SIZE_HEIGHT 15:0 /* -W-UF */
|
|
#define NV_04B_UNCLIPPED_RECTANGLE_SIZE_WIDTH 31:16 /* -W-UF */
|
|
#define NV_04B_CLIP_B_POINT0 0x006B07F4 /* -W-4R */
|
|
#define NV_04B_CLIP_B_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_B_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04B_CLIP_B_POINT1 0x006B07F8 /* -W-4R */
|
|
#define NV_04B_CLIP_B_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_B_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04B_COLOR1_B 0x006B07FC /* -W-4R */
|
|
#define NV_04B_COLOR1_B_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_0(i) (0x006B0800+(i)*8) /* -W-4A */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_0__SIZE_1 64 /* */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_0_TOP 31:16 /* -W-SF */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_1(i) (0x006B0804+(i)*8) /* -W-4A */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_1__SIZE_1 64 /* */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIPPED_RECTANGLE_POINT_1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04B_CLIP_C_POINT0 0x006B0BEC /* -W-4R */
|
|
#define NV_04B_CLIP_C_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_C_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04B_CLIP_C_POINT1 0x006B0BF0 /* -W-4R */
|
|
#define NV_04B_CLIP_C_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_C_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04B_COLOR1_C 0x006B0BF4 /* -W-4R */
|
|
#define NV_04B_COLOR1_C_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_SIZE_C 0x006B0BF8 /* -W-4R */
|
|
#define NV_04B_SIZE_C_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04B_SIZE_C_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04B_POINT_C 0x006B0BFC /* -W-4R */
|
|
#define NV_04B_POINT_C_X 15:0 /* -W-SF */
|
|
#define NV_04B_POINT_C_Y 31:16 /* -W-SF */
|
|
#define NV_04B_MONOCHROME_COLOR1_C(i) (0x006B0C00+(i)*4) /* -W-4A */
|
|
#define NV_04B_MONOCHROME_COLOR1_C__SIZE_1 128 /* */
|
|
#define NV_04B_MONOCHROME_COLOR1_C_BITMAP 31:0 /* -W-VF */
|
|
#define NV_04B_CLIP_D_POINT0 0x006B0FE8 /* -W-4R */
|
|
#define NV_04B_CLIP_D_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_D_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04B_CLIP_D_POINT1 0x006B0FEC /* -W-4R */
|
|
#define NV_04B_CLIP_D_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_D_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04B_COLOR1_D 0x006B0FF0 /* -W-4R */
|
|
#define NV_04B_COLOR1_D_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_SIZE_IN_D 0x006B0FF4 /* -W-4R */
|
|
#define NV_04B_SIZE_IN_D_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04B_SIZE_IN_D_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04B_SIZE_OUT_D 0x006B0FF8 /* -W-4R */
|
|
#define NV_04B_SIZE_OUT_D_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04B_SIZE_OUT_D_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04B_POINT_D 0x006B0FFC /* -W-4R */
|
|
#define NV_04B_POINT_D_X 15:0 /* -W-SF */
|
|
#define NV_04B_POINT_D_Y 31:16 /* -W-SF */
|
|
#define NV_04B_MONOCHROME_COLOR1_D(i) (0x006B1000+(i)*4) /* -W-4A */
|
|
#define NV_04B_MONOCHROME_COLOR1_D__SIZE_1 128 /* */
|
|
#define NV_04B_MONOCHROME_COLOR1_D_BITMAP 31:0 /* -W-VF */
|
|
#define NV_04B_CLIP_E_POINT0 0x006B13E4 /* -W-4R */
|
|
#define NV_04B_CLIP_E_POINT0_LEFT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_E_POINT0_TOP 31:16 /* -W-SF */
|
|
#define NV_04B_CLIP_E_POINT1 0x006B13E8 /* -W-4R */
|
|
#define NV_04B_CLIP_E_POINT1_RIGHT 15:0 /* -W-SF */
|
|
#define NV_04B_CLIP_E_POINT1_BOTTOM 31:16 /* -W-SF */
|
|
#define NV_04B_COLOR0_E 0x006B13EC /* -W-4R */
|
|
#define NV_04B_COLOR0_E_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_COLOR1_E 0x006B13F0 /* -W-4R */
|
|
#define NV_04B_COLOR1_E_VALUE 31:0 /* -W-VF */
|
|
#define NV_04B_SIZE_IN_E 0x006B13F4 /* -W-4R */
|
|
#define NV_04B_SIZE_IN_E_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04B_SIZE_IN_E_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04B_SIZE_OUT_E 0x006B13F8 /* -W-4R */
|
|
#define NV_04B_SIZE_OUT_E_WIDTH 15:0 /* -W-UF */
|
|
#define NV_04B_SIZE_OUT_E_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_04B_POINT_E 0x006B13FC /* -W-4R */
|
|
#define NV_04B_POINT_E_X 15:0 /* -W-SF */
|
|
#define NV_04B_POINT_E_Y 31:16 /* -W-SF */
|
|
#define NV_04B_MONOCHROME_COLOR01_E(i) (0x006B1400+(i)*4) /* -W-4A */
|
|
#define NV_04B_MONOCHROME_COLOR01_E__SIZE_1 128 /* */
|
|
#define NV_04B_MONOCHROME_COLOR01_E_BITMAP 31:0 /* -W-VF */
|
|
/* usr_context_surfaces_argb_zs.ref */
|
|
#define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000053 /* ----C */
|
|
#define NV_053 0x00601FFF:0x00600000 /* -W--D */
|
|
#define NV_053_NV4_CONTEXT_SURFACES_ARGB_ZS 0x00600000 /* -W-4R */
|
|
#define NV_053_NOP 0x00600100 /* -W-4R */
|
|
#define NV_053_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_053_NOTIFY 0x00600104 /* -W-4R */
|
|
#define NV_053_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_053_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_053_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_053_SET_CONTEXT_DMA_NOTIFY 0x00600180 /* -W-4R */
|
|
#define NV_053_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_053_SET_CONTEXT_DMA_COLOR 0x00600184 /* -W-4R */
|
|
#define NV_053_SET_CONTEXT_DMA_COLOR_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_053_SET_CONTEXT_DMA_ZETA 0x00600188 /* -W-4R */
|
|
#define NV_053_SET_CONTEXT_DMA_ZETA_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_053_SET_CLIP_HORIZONTAL 0x006002f8 /* -W-4R */
|
|
#define NV_053_SET_CLIP_HORIZONTAL_X 15:0 /* -W-UF */
|
|
#define NV_053_SET_CLIP_HORIZONTAL_WIDTH 31:16 /* -W-UF */
|
|
#define NV_053_SET_CLIP_VERTICAL 0x006002fc /* -W-4R */
|
|
#define NV_053_SET_CLIP_VERTICAL_Y 15:0 /* -W-UF */
|
|
#define NV_053_SET_CLIP_VERTICAL_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_053_SET_FORMAT 0x00600300 /* -W-4R */
|
|
#define NV_053_SET_FORMAT_COLOR 7:0 /* -W-VF */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x00000001 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_R5G6B5 0x00000003 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_053_SET_FORMAT_COLOR_LE_A8R8G8B8 0x00000008 /* -W--V */
|
|
#define NV_053_SET_FORMAT_TYPE 15:8 /* -W-VF */
|
|
#define NV_053_SET_FORMAT_TYPE_PITCH 0x00000001 /* -W--V */
|
|
#define NV_053_SET_FORMAT_TYPE_SWIZZLE 0x00000002 /* -W--V */
|
|
#define NV_053_SET_FORMAT_WIDTH 23:16 /* -W-VF */
|
|
#define NV_053_SET_FORMAT_HEIGHT 31:24 /* -W-VF */
|
|
#define NV_053_SET_CLIP_SIZE 0x00600304 /* -W-4R */
|
|
#define NV_053_SET_CLIP_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_053_SET_CLIP_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_053_SET_PITCH 0x00600308 /* -W-4R */
|
|
#define NV_053_SET_PITCH_COLOR 15:0 /* -W-UF */
|
|
#define NV_053_SET_PITCH_ZETA 31:16 /* -W-UF */
|
|
#define NV_053_SET_OFFSET_COLOR 0x0060030C /* -W-4R */
|
|
#define NV_053_SET_OFFSET_COLOR_VALUE 31:0 /* -W-UF */
|
|
#define NV_053_SET_OFFSET_ZETA 0x00600310 /* -W-4R */
|
|
#define NV_053_SET_OFFSET_ZETA_VALUE 31:0 /* -W-UF */
|
|
/* usr_nv10_context_surfaces_argb_zs.ref */
|
|
#define NV10_CONTEXT_SURFACES_ARGB_ZS 0x00000093 /* ----C */
|
|
#define NV_093 0x00581FFF:0x00580000 /* -W--D */
|
|
#define NV_093_NV10_CONTEXT_SURFACES_ARGB_ZS 0x00580000 /* -W-4R */
|
|
#define NV_093_NOP 0x00580100 /* -W-4R */
|
|
#define NV_093_NOP_PARAMETER 31:0 /* -W-VF */
|
|
#define NV_093_NOTIFY 0x00580104 /* -W-4R */
|
|
#define NV_093_NOTIFY_STYLE 31:0 /* -WXVF */
|
|
#define NV_093_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* -W--V */
|
|
#define NV_093_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* -W--V */
|
|
#define NV_093_SET_CONTEXT_DMA_NOTIFY 0x00580180 /* -W-4R */
|
|
#define NV_093_SET_CONTEXT_DMA_NOTIFY_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_093_SET_CONTEXT_DMA_COLOR 0x00580184 /* -W-4R */
|
|
#define NV_093_SET_CONTEXT_DMA_COLOR_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_093_SET_CONTEXT_DMA_ZETA 0x00580188 /* -W-4R */
|
|
#define NV_093_SET_CONTEXT_DMA_ZETA_PARAMETER 31:0 /* -WXVF */
|
|
#define NV_093_SET_CLIP_HORIZONTAL 0x005802f8 /* -W-4R */
|
|
#define NV_093_SET_CLIP_HORIZONTAL_X 15:0 /* -W-UF */
|
|
#define NV_093_SET_CLIP_HORIZONTAL_WIDTH 31:16 /* -W-UF */
|
|
#define NV_093_SET_CLIP_VERTICAL 0x005802fc /* -W-4R */
|
|
#define NV_093_SET_CLIP_VERTICAL_Y 15:0 /* -W-UF */
|
|
#define NV_093_SET_CLIP_VERTICAL_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_093_SET_FORMAT 0x00580300 /* -W-4R */
|
|
#define NV_093_SET_FORMAT_COLOR 7:0 /* -W-VF */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_X1R5G5B5_Z1R5G5B5 0x00000001 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_X1R5G5B5_O1R5G5B5 0x00000002 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_R5G6B5 0x00000003 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_X8R8G8B8_Z8R8G8B8 0x00000004 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_X8R8G8B8_O8R8G8B8 0x00000005 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_X1A7R8G8B8_Z1A7R8G8B8 0x00000006 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_X1A7R8G8B8_O1A7R8G8B8 0x00000007 /* -W--V */
|
|
#define NV_093_SET_FORMAT_COLOR_LE_A8R8G8B8 0x00000008 /* -W--V */
|
|
#define NV_093_SET_FORMAT_TYPE 15:8 /* -W-VF */
|
|
#define NV_093_SET_FORMAT_TYPE_PITCH 0x00000001 /* -W--V */
|
|
#define NV_093_SET_FORMAT_TYPE_SWIZZLE 0x00000002 /* -W--V */
|
|
#define NV_093_SET_FORMAT_WIDTH 23:16 /* -W-VF */
|
|
#define NV_093_SET_FORMAT_HEIGHT 31:24 /* -W-VF */
|
|
#define NV_093_SET_CLIP_SIZE 0x00580304 /* -W-4R */
|
|
#define NV_093_SET_CLIP_SIZE_WIDTH 15:0 /* -W-UF */
|
|
#define NV_093_SET_CLIP_SIZE_HEIGHT 31:16 /* -W-UF */
|
|
#define NV_093_SET_PITCH 0x00580308 /* -W-4R */
|
|
#define NV_093_SET_PITCH_COLOR 15:0 /* -W-UF */
|
|
#define NV_093_SET_PITCH_ZETA 31:16 /* -W-UF */
|
|
#define NV_093_SET_OFFSET_COLOR 0x0058030C /* -W-4R */
|
|
#define NV_093_SET_OFFSET_COLOR_VALUE 31:0 /* -W-UF */
|
|
#define NV_093_SET_OFFSET_ZETA 0x00580310 /* -W-4R */
|
|
#define NV_093_SET_OFFSET_ZETA_VALUE 31:0 /* -W-UF */
|
|
/* usr_context_dma.ref */
|
|
#define NV_CONTEXT_DMA_IN_MEMORY 0x0000003D /* ----C */
|
|
#define NV_CONTEXT_DMA_FROM_MEMORY 0x00000002 /* ----C */
|
|
#define NV_CONTEXT_DMA_TO_MEMORY 0x00000003 /* ----C */
|
|
#define NV4_CONTEXT_SURFACES_ARGB_ZS 0x00000053 /* ----C */
|
|
/* usr_null_class.ref */
|
|
#define NV_NULL_CLASS 0x00000030 /* ----C */
|
|
/* usr_notifications.ref */
|
|
#define NV_STATUS_IN_PROGRESS (0x8000) /* not done */
|
|
#define NV_STATUS_ERROR_PROTECTION_FAULT (0x4000) /* fatal error */
|
|
#define NV_STATUS_ERROR_BAD_ARGUMENT (0x2000) /* fatal error */
|
|
#define NV_STATUS_ERROR_INVALID_STATE (0x1000) /* fatal error */
|
|
#define NV_STATUS_ERROR_STATE_IN_USE (0x0800) /* fatal error */
|
|
#define NV_STATUS_ERROR_BAD_PATCH (0x0400) /* fatal error */
|
|
#define NV_STATUS_ERROR_FLOW_CONTROL (0x0200) /* fatal error */
|
|
#define NV_STATUS_WARNING_INVALID_DATA (0x0001) /* warning */
|
|
#define NV_STATUS_NO_ERRORS_OR_WARNINGS (0x0000) /* done all ok */
|
|
/* dev_pm.ref */
|
|
#define NV_PPM 0x0000AFFF:0x0000A000 /* RW--D */
|
|
#define NV_PPM_NV_TRIG0_SEL 0x0000A400 /* RW-4R */
|
|
#define NV_PPM_NV_TRIG0_SEL_SEL0 7:0 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG0_SEL_SEL1 15:8 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG0_SEL_SEL2 23:16 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG0_SEL_SEL3 31:24 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG0_OP 0x0000A404 /* RW-4R */
|
|
#define NV_PPM_NV_TRIG0_OP_FUNC 15:0 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG0_OP_DSEL0 16:16 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG0_OP_DSEL1 17:17 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_SEL 0x0000A408 /* RW-4R */
|
|
#define NV_PPM_NV_TRIG1_SEL_SEL0 7:0 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_SEL_SEL1 15:8 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_SEL_SEL2 23:16 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_SEL_SEL3 31:24 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_OP 0x0000A40C /* RW-4R */
|
|
#define NV_PPM_NV_TRIG1_OP_FUNC 15:0 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_OP_DSEL0 16:16 /* RWXUF */
|
|
#define NV_PPM_NV_TRIG1_OP_DSEL1 17:17 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_SEL 0x0000A410 /* RW-4R */
|
|
#define NV_PPM_NV_EVENT_SEL_SEL0 7:0 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_SEL_SEL1 15:8 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_SEL_SEL2 23:16 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_SEL_SEL3 31:24 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_OP 0x0000A414 /* RW-4R */
|
|
#define NV_PPM_NV_EVENT_OP_FUNC 15:0 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_OP_DSEL0 16:16 /* RWXUF */
|
|
#define NV_PPM_NV_EVENT_OP_DSEL1 17:17 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_SEL 0x0000A418 /* RW-4R */
|
|
#define NV_PPM_NV_SAMPLE_SEL_SEL0 7:0 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_SEL_SEL1 15:8 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_SEL_SEL2 23:16 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_SEL_SEL3 31:24 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_OP 0x0000A41C /* RW-4R */
|
|
#define NV_PPM_NV_SAMPLE_OP_FUNC 15:0 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_OP_DSEL0 16:16 /* RWXUF */
|
|
#define NV_PPM_NV_SAMPLE_OP_DSEL1 17:17 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_SEL 0x0000A420 /* RW-4R */
|
|
#define NV_PPM_NV_SETFLAG_SEL_SEL0 7:0 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_SEL_SEL1 15:8 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_SEL_SEL2 23:16 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_SEL_SEL3 31:24 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_OP 0x0000A424 /* RW-4R */
|
|
#define NV_PPM_NV_SETFLAG_OP_FUNC 15:0 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_OP_DSEL0 16:16 /* RWXUF */
|
|
#define NV_PPM_NV_SETFLAG_OP_DSEL1 17:17 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_SEL 0x0000A428 /* RW-4R */
|
|
#define NV_PPM_NV_CLRFLAG_SEL_SEL0 7:0 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_SEL_SEL1 15:8 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_SEL_SEL2 23:16 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_SEL_SEL3 31:24 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_OP 0x0000A42C /* RW-4R */
|
|
#define NV_PPM_NV_CLRFLAG_OP_FUNC 15:0 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_OP_DSEL0 16:16 /* RWXUF */
|
|
#define NV_PPM_NV_CLRFLAG_OP_DSEL1 17:17 /* RWXUF */
|
|
#define NV_PPM_NV_ELAPSED_0 0x0000A600 /* RR-4R */
|
|
#define NV_PPM_NV_ELAPSED_0_VAL 31:0 /* RR-UF */
|
|
#define NV_PPM_NV_ELAPSED_1 0x0000A604 /* RR-4R */
|
|
#define NV_PPM_NV_ELAPSED_1_VAL 7:0 /* RR-UF */
|
|
#define NV_PPM_NV_CYCLECNT_0 0x0000A608 /* RR-4R */
|
|
#define NV_PPM_NV_CYCLECNT_0_VAL 31:0 /* RR-UF */
|
|
#define NV_PPM_NV_CYCLECNT_1 0x0000A60C /* RR-4R */
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#define NV_PPM_NV_CYCLECNT_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_NV_EVENTCNT_0 0x0000A610 /* RR-4R */
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#define NV_PPM_NV_EVENTCNT_0_VAL 31:0 /* RR-UF */
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#define NV_PPM_NV_EVENTCNT_1 0x0000A614 /* RR-4R */
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#define NV_PPM_NV_EVENTCNT_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_NV_THRESHCNT_0 0x0000A618 /* RR-4R */
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#define NV_PPM_NV_THRESHCNT_0_VAL 31:0 /* RR-UF */
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#define NV_PPM_NV_THRESHCNT_1 0x0000A61C /* RR-4R */
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#define NV_PPM_NV_THRESHCNT_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_NV_TRIGGERCNT 0x0000A620 /* RW-4R */
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#define NV_PPM_NV_TRIGGERCNT_VAL 31:0 /* RWXUF */
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#define NV_PPM_NV_SAMPLECNT 0x0000A624 /* RW-4R */
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#define NV_PPM_NV_SAMPLECNT_VAL 31:0 /* RWXUF */
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#define NV_PPM_NV_THRESHOLD_0 0x0000A628 /* RW-4R */
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#define NV_PPM_NV_THRESHOLD_0_VAL 31:0 /* RWXUF */
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#define NV_PPM_NV_THRESHOLD_1 0x0000A62C /* RW-4R */
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#define NV_PPM_NV_THRESHOLD_1_VAL 7:0 /* RWXUF */
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#define NV_PPM_M_TRIG0_SEL 0x0000A500 /* RW-4R */
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#define NV_PPM_M_TRIG0_SEL_SEL0 5:0 /* RWXUF */
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#define NV_PPM_M_TRIG0_SEL_SEL1 13:8 /* RWXUF */
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#define NV_PPM_M_TRIG0_SEL_SEL2 21:16 /* RWXUF */
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#define NV_PPM_M_TRIG0_SEL_SEL3 29:24 /* RWXUF */
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#define NV_PPM_M_TRIG0_OP 0x0000A504 /* RW-4R */
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#define NV_PPM_M_TRIG0_OP_FUNC 15:0 /* RWXUF */
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#define NV_PPM_M_TRIG0_OP_DSEL0 16:16 /* RWXUF */
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#define NV_PPM_M_TRIG0_OP_DSEL1 17:17 /* RWXUF */
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#define NV_PPM_M_TRIG1_SEL 0x0000A508 /* RW-4R */
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#define NV_PPM_M_TRIG1_SEL_SEL0 5:0 /* RWXUF */
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#define NV_PPM_M_TRIG1_SEL_SEL1 13:8 /* RWXUF */
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#define NV_PPM_M_TRIG1_SEL_SEL2 21:16 /* RWXUF */
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#define NV_PPM_M_TRIG1_SEL_SEL3 29:24 /* RWXUF */
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#define NV_PPM_M_TRIG1_OP 0x0000A50C /* RW-4R */
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#define NV_PPM_M_TRIG1_OP_FUNC 15:0 /* RWXUF */
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#define NV_PPM_M_TRIG1_OP_DSEL0 16:16 /* RWXUF */
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#define NV_PPM_M_TRIG1_OP_DSEL1 17:17 /* RWXUF */
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#define NV_PPM_M_EVENT_SEL 0x0000A510 /* RW-4R */
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#define NV_PPM_M_EVENT_SEL_SEL0 5:0 /* RWXUF */
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#define NV_PPM_M_EVENT_SEL_SEL1 13:8 /* RWXUF */
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#define NV_PPM_M_EVENT_SEL_SEL2 21:16 /* RWXUF */
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#define NV_PPM_M_EVENT_SEL_SEL3 29:24 /* RWXUF */
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#define NV_PPM_M_EVENT_OP 0x0000A514 /* RW-4R */
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#define NV_PPM_M_EVENT_OP_FUNC 15:0 /* RWXUF */
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#define NV_PPM_M_EVENT_OP_DSEL0 16:16 /* RWXUF */
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#define NV_PPM_M_EVENT_OP_DSEL1 17:17 /* RWXUF */
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#define NV_PPM_M_SAMPLE_SEL 0x0000A518 /* RW-4R */
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#define NV_PPM_M_SAMPLE_SEL_SEL0 5:0 /* RWXUF */
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#define NV_PPM_M_SAMPLE_SEL_SEL1 13:8 /* RWXUF */
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#define NV_PPM_M_SAMPLE_SEL_SEL2 21:16 /* RWXUF */
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#define NV_PPM_M_SAMPLE_SEL_SEL3 29:24 /* RWXUF */
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#define NV_PPM_M_SAMPLE_OP 0x0000A51C /* RW-4R */
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#define NV_PPM_M_SAMPLE_OP_FUNC 15:0 /* RWXUF */
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#define NV_PPM_M_SAMPLE_OP_DSEL0 16:16 /* RWXUF */
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#define NV_PPM_M_SAMPLE_OP_DSEL1 17:17 /* RWXUF */
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#define NV_PPM_M_SETFLAG_SEL 0x0000A520 /* RW-4R */
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#define NV_PPM_M_SETFLAG_SEL_SEL0 5:0 /* RWXUF */
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#define NV_PPM_M_SETFLAG_SEL_SEL1 13:8 /* RWXUF */
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#define NV_PPM_M_SETFLAG_SEL_SEL2 21:16 /* RWXUF */
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#define NV_PPM_M_SETFLAG_SEL_SEL3 29:24 /* RWXUF */
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#define NV_PPM_M_SETFLAG_OP 0x0000A524 /* RW-4R */
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#define NV_PPM_M_SETFLAG_OP_FUNC 15:0 /* RWXUF */
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#define NV_PPM_M_SETFLAG_OP_DSEL0 16:16 /* RWXUF */
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#define NV_PPM_M_SETFLAG_OP_DSEL1 17:17 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_SEL 0x0000A528 /* RW-4R */
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#define NV_PPM_M_CLRFLAG_SEL_SEL0 5:0 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_SEL_SEL1 13:8 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_SEL_SEL2 21:16 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_SEL_SEL3 29:24 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_OP 0x0000A52C /* RW-4R */
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#define NV_PPM_M_CLRFLAG_OP_FUNC 15:0 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_OP_DSEL0 16:16 /* RWXUF */
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#define NV_PPM_M_CLRFLAG_OP_DSEL1 17:17 /* RWXUF */
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#define NV_PPM_M_ELAPSED_0 0x0000A700 /* RR-4R */
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#define NV_PPM_M_ELAPSED_0_VAL 31:0 /* RR-UF */
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#define NV_PPM_M_ELAPSED_1 0x0000A704 /* RR-4R */
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#define NV_PPM_M_ELAPSED_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_M_CYCLECNT_0 0x0000A708 /* RR-4R */
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#define NV_PPM_M_CYCLECNT_0_VAL 31:0 /* RR-UF */
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#define NV_PPM_M_CYCLECNT_1 0x0000A70C /* RR-4R */
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#define NV_PPM_M_CYCLECNT_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_M_EVENTCNT_0 0x0000A710 /* RR-4R */
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#define NV_PPM_M_EVENTCNT_0_VAL 31:0 /* RR-UF */
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#define NV_PPM_M_EVENTCNT_1 0x0000A714 /* RR-4R */
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#define NV_PPM_M_EVENTCNT_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_M_THRESHCNT_0 0x0000A718 /* RR-4R */
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#define NV_PPM_M_THRESHCNT_0_VAL 31:0 /* RR-UF */
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#define NV_PPM_M_THRESHCNT_1 0x0000A71C /* RR-4R */
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#define NV_PPM_M_THRESHCNT_1_VAL 7:0 /* RR-UF */
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#define NV_PPM_M_TRIGGERCNT 0x0000A720 /* RW-4R */
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#define NV_PPM_M_TRIGGERCNT_VAL 31:0 /* RWXUF */
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#define NV_PPM_M_SAMPLECNT 0x0000A724 /* RW-4R */
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#define NV_PPM_M_SAMPLECNT_VAL 31:0 /* RWXUF */
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#define NV_PPM_M_THRESHOLD_0 0x0000A728 /* RW-4R */
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#define NV_PPM_M_THRESHOLD_0_VAL 31:0 /* RWXUF */
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#define NV_PPM_M_THRESHOLD_1 0x0000A72C /* RW-4R */
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#define NV_PPM_M_THRESHOLD_1_VAL 7:0 /* RWXUF */
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#define NV_PPM_NV_WATCH0 0x0000A430 /* RR-4R */
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#define NV_PPM_NV_WATCH0_GR_XBAR2FE_PIXCOUNT_REPORT_REQ_NV 0: 0 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2CBUF_READY3 1: 1 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2CBUF_READY2 2: 2 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2CBUF_READY1 3: 3 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2CBUF_READY0 4: 4 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2CBUF_STALL 5: 5 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_FEFLUSHACTIVE 6: 6 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_BACKEND_IDLE 7: 7 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2FE_SEMAPHORE_RELEASE_REQ 8: 8 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2R2D_BUSY 9: 9 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_PROP2CMB_READY 10:10 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_CMB2PROP_VALID 11:11 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_CMB2RSTR_VALID 12:12 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_RECIRC_CYCLE 13:13 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_CMB2SHDBE_BUSY 14:14 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_SHDBE2SHD_VALID 15:15 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_SHDBE2TEX_BUSY 16:16 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_SHDBE2CMB_VALID 17:17 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TFAB_TPB_BUSY 18:18 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TFAB_TPA_BUSY 19:19 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TC2FB_P3_STALL 20:20 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TC2FB_P2_STALL 21:21 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TC2FB_P1_STALL 22:22 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TC2FB_P0_STALL 23:23 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TCDMA2FB_STALL 24:24 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_DXP_UNALIGN_XFER 25:25 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_DXP_DXT_XFER 26:26 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_DXP_PAL_XFER 27:27 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_DXP_PAL_LOAD 28:28 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_DXP_XFER1 29:29 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_DXP_XFER0 30:30 /* RR-UF */
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#define NV_PPM_NV_WATCH0_GR_TPB_STATUS 31:31 /* RR-UF */
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#define NV_PPM_NV_WATCH1 0x0000A434 /* RR-4R */
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#define NV_PPM_NV_WATCH1_GR_TPB_RBFR_FULL 0: 0 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPB_INUSE_STALL 1: 1 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPB_XBFR_STALL 2: 2 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_STATUS 3: 3 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_RBFR_FULL 4: 4 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_INUSE_STALL 5: 5 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_XBFR_STALL 6: 6 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_M_TPB_SYNC_BUSY 7: 7 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPB_M_SYNC_VALID 8: 8 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_M_TPA_SYNC_BUSY 9: 9 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_M_SYNC_VALID 10:10 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_M_TPB_BUSY 11:11 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPB_M_VALID 12:12 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_M_TPA_BUSY 13:13 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_M_VALID 14:14 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPB_TMAB_BUSY 15:15 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TMAB_TPB_VALID 16:16 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TPA_TMAB_BUSY 17:17 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TMAB_TPA_VALID 18:18 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TEX2SHD_BUSY 19:19 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_TEX2SHDBE_VALID 20:20 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_CACHE_IDLE 21:21 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_FBI_RDFA_FULL 22:22 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_FBI_RDFB_FULL 23:23 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SPF_FULL 24:24 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_PMI_RDF_FULL 25:25 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SHD2SHDBE_BUSY 26:26 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SHD2SHDBE_VALID 27:27 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SHD_IDLE 28:28 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SP3_BUSY 29:29 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SP2_BUSY 30:30 /* RR-UF */
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#define NV_PPM_NV_WATCH1_GR_SP1_BUSY 31:31 /* RR-UF */
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#define NV_PPM_NV_WATCH2 0x0000A438 /* RR-4R */
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#define NV_PPM_NV_WATCH2_GR_SP0_BUSY 0: 0 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_SHD2TEX_VALID 1: 1 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_SHD2RSTR_BUSY 2: 2 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_SHD2CAS_BUSY 3: 3 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CAS2SHD_LAST 4: 4 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CAS2SHD_VALID 5: 5 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CASIDLE 6: 6 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CAS2STP_BUSY 7: 7 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CAS2VTX_BUSY 8: 8 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2PROP_OUTPUT_REQ 9: 9 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2PROP_OUTPUT_NOP 10:10 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_RSTR2D_IDLE 11:11 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2TEX_IM_RIGHT_DV 12:12 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2TEX_IM_LEFT_DV 13:13 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2TEX_IM_NEWLINE 14:14 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2FE_RSTR2D_BUSY 15:15 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_R2D2PM_FE_REQ 16:16 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_RSTR2PROP_ZCULL_COMPRESSED 17:17 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_RSTR2PROP_ZCULL_VALID 18:18 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_RSTR2SHD_EOPRIM 19:19 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_RSTR2SHD_VALID 20:20 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_FRSTR2CULL_READY 21:21 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_PIXCNT_0 22:22 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_PIXCNT_1 23:23 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_PIXCNT_2 24:24 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_FINE_EDGE_EVAL 25:25 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_FINE_ALIASED 26:26 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_ZOCL2FB_REQ 27:27 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CULL2PM_ZCULL3 28:28 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CULL2PM_ZCULL2 29:29 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CULL2PM_ZCULL1 30:30 /* RR-UF */
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#define NV_PPM_NV_WATCH2_GR_CULL2FRSTR_ZST_COMPRESS 31:31 /* RR-UF */
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#define NV_PPM_NV_WATCH3 0x0000A43C /* RR-4R */
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#define NV_PPM_NV_WATCH3_GR_CULL2FRSTR_DV 0: 0 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_CULL2FRSTR_NULLZ 1: 1 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_CULL2CRSTR_READY 2: 2 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_CRSTR2CULL_VALID 3: 3 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_RSTR2PM_SEARCH_MODE 4: 4 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_RSTR2STP_READY 5: 5 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_STP_IDLE 6: 6 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2VTX_NOT_BUSY 7: 7 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2RSTR_VALID 8: 8 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2RSTR_DO_SWATHS 9: 9 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2CAS_VALID 10:10 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_START_PRIM 11:11 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_POLYMODE 12:12 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_DO_POINT 13:13 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_DO_LINE 14:14 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_CULL_REASON_0 15:15 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_CULL_REASON_1 16:16 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_STP2PM_CULL_REASON_2 17:17 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_VTX2STP_STATEVALID 18:18 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_VTX2STP_PRIMVALID 19:19 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_VTX2CAS_VALID 20:20 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_VTXIDLE 21:21 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_VTX2XF_LAUNCHBUSY 22:22 /* RR-UF */
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#define NV_PPM_NV_WATCH3_GR_VTX2FD_BYPBUSY 23:23 /* RR-UF */
|
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#define NV_PPM_NV_WATCH3_GR_XF_FETCH_BUSY 24:24 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_XF_ISSUE_VALID 25:25 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_XF_IDLE 26:26 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_XF2VTX_LAUNCH_VALID 27:27 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_XF2VTX_LAST 28:28 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_XF2VTX_VALID 29:29 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_XF2FD_BUSY 30:30 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH3_GR_FD_PROCESS1 31:31 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4 0x0000A630 /* RR-4R */
|
|
#define NV_PPM_NV_WATCH4_GR_FD_PROCESS0 0: 0 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2XF_LAUNCH 1: 1 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2XF_INIT 2: 2 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2XF_ACTIVE 3: 3 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2XF_VALID 4: 4 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2VTX_BYPVALID 5: 5 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2IDX_BYPBUSY 6: 6 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FD2IDX_BUSY 7: 7 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2FD_LAUNCH 8: 8 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2FD_BYPVALID 9: 9 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2FD_VALID 10:10 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_INTALIGN 11:11 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_COMPOVFL 12:12 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_PTEBUSY 13:13 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_BYPASSFULL 14:14 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDXIDLE 15:15 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_SLOTHIT 16:16 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_SLOTMISS 17:17 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_CACHEHIT 18:18 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_CACHEMISS 19:19 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_CACHEUSAGEWAIT 20:20 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_CACHEUSAGEFULL 21:21 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_PTEUSAGEWAIT 22:22 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2PMI_VALID 23:23 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2DEC_BUSY 24:24 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2FBI_INST 25:25 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_IDX2FBI_VALID 26:26 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FBI2IDX_BUSY 27:27 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FE2PM_FBI_REQ_BURST 28:28 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FE2PM_FBI_REQ 29:29 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FE2PM_FBI_RD 30:30 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH4_GR_FE2PM_FBI_INST 31:31 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5 0x0000A634 /* RR-4R */
|
|
#define NV_PPM_NV_WATCH5_GR_FE2XBAR_PIXELCOUNT_REPORT_BUSY 0: 0 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_FE2PROP_SEMAPHORE_RELEASE_BUSY 1: 1 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_FE2PM_CACHE_INVALIDATE 2: 2 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_NVINTR_GR 3: 3 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_WAIT_GR_IDLE 4: 4 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_GR_IDLE 5: 5 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_DEC2IDX_VALID_0 6: 6 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_DEC2IDX_VALID_1 7: 7 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_FF_GR_RDY 8: 8 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_GR_FF_GR_B2B 9: 9 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_VSYNC1 10:10 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_FB2ZOCL_BUSY 11:11 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_COALESCE_0 12:12 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_COALESCE_1 13:13 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_COALESCE_2 14:14 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_BUSY3 15:15 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_BUSY2 16:16 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_BUSY1 17:17 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_CBUF_BUSY0 18:18 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_PMI2IDX_BUSY 19:19 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_FF_GR_MDV 20:20 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_FF_DHV 21:21 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_FF_CHSW 22:22 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_BR2PM_DEVSEL_ 23:23 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_BR2PM_STOP_ 24:24 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_BR2PM_TRDY_ 25:25 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_BR2PM_IRDY_ 26:26 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_TOP_BR2PM_FRAME_ 27:27 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0 0x0000A530 /* RR-4R */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE0_0 0: 0 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE0_1 1: 1 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE0_2 2: 2 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE1_0 3: 3 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE1_1 4: 4 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE1_2 5: 5 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE2_0 6: 6 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE2_1 7: 7 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE2_2 8: 8 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE3_0 9: 9 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE3_1 10:10 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBARSTATE3_2 11:11 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBAR2ZROP_BUSY0 12:12 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBAR2ZROP_BUSY1 13:13 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBAR2ZROP_BUSY2 14:14 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBAR2ZROP_BUSY3 15:15 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_GR_XBAR2ZROP_IDLE 16:16 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2ZRD_P0_BUSY 17:17 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2ZWR_P0_BUSY 18:18 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2CRD_P0_BUSY 19:19 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2CWR_P0_BUSY 20:20 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2ZRD_P0_QEMPTY 21:21 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2ZWR_P0_QEMPTY 22:22 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2CRD_P0_QEMPTY 23:23 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_FB2CWR_P0_QEMPTY 24:24 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_MC_BUSY_D 25:25 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_A1_ANY_GNT_VALID 26:26 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_A1_NX_CONT_GNT 27:27 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_A1_GNT_BANK_0 28:28 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_A1_GNT_BANK_1 29:29 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_A1_ZW_GNT_COMPRESS 30:30 /* RR-UF */
|
|
#define NV_PPM_M_WATCH0_TOP_P0_FARB_A1_GNT_CLOSE_PAGE 31:31 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1 0x0000A534 /* RR-4R */
|
|
#define NV_PPM_M_WATCH1_TOP_P0_FARB_A1_GNT_RD 0: 0 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CWR2FB_REQ 1: 1 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CROP2PM_BURST_STALL_RD 2: 2 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CROP2PM_SB_STALL 3: 3 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CROP2PM_HASH_STALL 4: 4 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CROP2XBAR_BUSY 5: 5 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZWR2FB_REQ 6: 6 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZROP2XBAR_REQ 7: 7 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZWR_WAIT4CSUBPKT 8: 8 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZWR2ZRD_ZSUBPKT_BUSY 9: 9 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZWR2ZRD_PKT_BUSY 10:10 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZROP2CBUF_CSUBPKT_BUSY 11:11 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZRD2FB_REQ 12:12 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ILOCK_STALL 13:13 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_TAG_STALL 14:14 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_TOSS_CULL 15:15 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZRD2ZWR_ZSUBPKT_RDY 16:16 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZRD2ZWR_PKT_RDY 17:17 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZROP2CBUF_ZSUBPKT_BUSY 18:18 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_ZROP2CBUF_PKT_BUSY 19:19 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CBUF2ZROP_ZSUBPKT_RDY 20:20 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CBUF2ZROP_CSUBPKT_RDY 21:21 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_TOP_CBUF2ZROP_PKT_RDY 22:22 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_ZEROBIT 28:28 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_FE2PM_TRIGGER 29:29 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_MFLAG_SYNC 30:30 /* RR-UF */
|
|
#define NV_PPM_NV_WATCH5_NVFLAG 31:31 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_ZEROBIT 28:28 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_FE2PM_TRIGGER 29:29 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_MFLAG 30:30 /* RR-UF */
|
|
#define NV_PPM_M_WATCH1_NVFLAG_SYNC 31:31 /* RR-UF */
|
|
#define NV_PPM_CONTROL 0x0000A73C /* RW-4R */
|
|
#define NV_PPM_CONTROL_M_ADDTOEVENT 0:0 /* RWXUF */
|
|
#define NV_PPM_CONTROL_M_ADDTOEVENT_INCR 0x00000000 /* RWI-V */
|
|
#define NV_PPM_CONTROL_M_ADDTOEVENT_ADDTRIG1 0x00000001 /* RWI-V */
|
|
#define NV_PPM_CONTROL_DRIVE_OUT 1:1 /* RWXUF */
|
|
#define NV_PPM_CONTROL_DRIVE_OUT_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PPM_CONTROL_DRIVE_OUT_OBSERVE 0x00000001 /* RWI-V */
|
|
#define NV_PPM_CONTROL_NV_ADDTOEVENT 2:2 /* RWXUF */
|
|
#define NV_PPM_CONTROL_NV_ADDTOEVENT_INCR 0x00000000 /* RWI-V */
|
|
#define NV_PPM_CONTROL_NV_ADDTOEVENT_ADDTRIG1 0x00000001 /* RWI-V */
|
|
#define NV_PPM_CONTROL_NV_STATE 4:3 /* RRIUF */
|
|
#define NV_PPM_CONTROL_M_STATE 6:5 /* RRIUF */
|
|
#define NV_PPM_CONTROL_STATE_IDLE 0x00000000 /* RRI-V */
|
|
#define NV_PPM_CONTROL_STATE_WAIT_TRIG0 0x00000001 /* RRI-V */
|
|
#define NV_PPM_CONTROL_STATE_WAIT_TRIG1 0x00000002 /* RRI-V */
|
|
#define NV_PPM_CONTROL_STATE_CAPTURE 0x00000003 /* RRI-V */
|
|
#define NV_PPM_CONTROL_NV_CLEAR_EVENT_ONCE 8:8 /* RWXUF */
|
|
#define NV_PPM_CONTROL_NV_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PPM_CONTROL_NV_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PPM_CONTROL_M_CLEAR_EVENT_ONCE 9:9 /* RWXUF */
|
|
#define NV_PPM_CONTROL_M_CLEAR_EVENT_ONCE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PPM_CONTROL_M_CLEAR_EVENT_ONCE_ENABLE 0x00000001 /* RWI-V */
|
|
/* dev_ram.ref */
|
|
#define NV_PNVM 0x3FFFFFFF:0x20000000 /* RW--M */
|
|
#define NV_PNVM_DATA032(i) (0x20000000+(i)*4) /* RW-4A */
|
|
#define NV_PNVM_DATA032__SIZE_1 33554432 /* */
|
|
#define NV_PNVM_DATA032_VALUE 31:0 /* RWXUF */
|
|
#define NV_PNVM_DATA016(i) (0x20000000+((i)/3)*4+((i)%3)) /* RW-2A */
|
|
#define NV_PNVM_DATA016__SIZE_1 67108864 /* */
|
|
#define NV_PNVM_DATA016_VALUE 15:0 /* RWXUF */
|
|
#define NV_PNVM_DATA008(i) (0x20000000+(i)) /* RW-1A */
|
|
#define NV_PNVM_DATA008__SIZE_1 134217728 /* */
|
|
#define NV_PNVM_DATA008_VALUE 7:0 /* RWXUF */
|
|
/* dev_ram.ref */
|
|
#define NV_PDFB 0x3FFFFFFF:0x20000000 /* RW--D */
|
|
/* dev_ram.ref */
|
|
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
|
|
#define NV_PRAMIN_CONTEXT_0 ( 0*32+31):( 0*32+ 0) /* */
|
|
#define NV_PRAMIN_CONTEXT_1 ( 1*32+31):( 1*32+ 0) /* */
|
|
#define NV_PRAMIN_CONTEXT_2 ( 2*32+31):( 2*32+ 0) /* */
|
|
#define NV_PRAMIN_CONTEXT_3 ( 3*32+31):( 3*32+ 0) /* */
|
|
#define NV_PRAMIN_RAMHT_0 0x00710FFF:0x00710000 /* RW--M */
|
|
#define NV_PRAMIN_RAMFC_0 0x007113FF:0x00711000 /* RW--M */
|
|
#define NV_PRAMIN_RAMRO_0 0x007115FF:0x00711400 /* RW--M */
|
|
#define NV_PRAMIN_CTX_0(i) (0x00700000 + (i)*16) /* RW--M */
|
|
#define NV_PRAMIN_CTX_0__SIZE_1 0x10000 /* */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS 11:0 /* RWXUF */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_NV_ROOT 0x00000000 /* RWD-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_012 0x00000012 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_017 0x00000017 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_018 0x00000018 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_019 0x00000019 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_01C 0x0000001C /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_01D 0x0000001D /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_01E 0x0000001E /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_01F 0x0000001F /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_021 0x00000021 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_030 0x00000030 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_036 0x00000036 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_037 0x00000037 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_038 0x00000038 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_039 0x00000039 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_042 0x00000042 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_043 0x00000043 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_044 0x00000044 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_048 0x00000048 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_04A 0x0000004A /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_04B 0x0000004B /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_052 0x00000052 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_053 0x00000053 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_054 0x00000054 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_055 0x00000055 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_057 0x00000057 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_058 0x00000058 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_059 0x00000059 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_05A 0x0000005A /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_05B 0x0000005B /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_05C 0x0000005C /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_05E 0x0000005E /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_05F 0x0000005F /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_060 0x00000060 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_061 0x00000061 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_064 0x00000064 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_065 0x00000065 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_066 0x00000066 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_0_NVCLASS_067 0x00000067 /* RWC-V */
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#define NV_PRAMIN_CTX_0_NVCLASS_072 0x00000072 /* RWC-V */
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#define NV_PRAMIN_CTX_0_NVCLASS_076 0x00000076 /* RWC-V */
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#define NV_PRAMIN_CTX_0_NVCLASS_077 0x00000077 /* RWC-V */
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#define NV_PRAMIN_CTX_0_CHROMA_KEY 12:12 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CHROMA_KEY_DISABLE 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_USER_CLIP 13:13 /* RWXUF */
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#define NV_PRAMIN_CTX_0_USER_CLIP_DISABLE 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_USER_CLIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_SWIZZLE 14:14 /* RWXUF */
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#define NV_PRAMIN_CTX_0_SWIZZLE_DISABLE 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_SWIZZLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG 17:15 /* RWXUF */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */
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#define NV_PRAMIN_CTX_0_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */
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#define NV_PRAMIN_CTX_0_SYNCHRONIZE 18:18 /* RWXUF */
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#define NV_PRAMIN_CTX_0_SYNCHRONIZE_DISABLE 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_SYNCHRONIZE_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_ENDIAN_MODE 19:19 /* RWXUF */
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#define NV_PRAMIN_CTX_0_ENDIAN_MODE_LITTLE 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_ENDIAN_MODE_BIG 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_DITHER_MODE 21:20 /* RWXUF */
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#define NV_PRAMIN_CTX_0_DITHER_MODE_COMPATIBILITY 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_DITHER_MODE_DITHER 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_DITHER_MODE_TRUNCATE 0x00000002 /* RW--V */
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#define NV_PRAMIN_CTX_0_DITHER_MODE_SUBTRACT_TRUNCATE 0x00000003 /* RW--V */
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#define NV_PRAMIN_CTX_0_SINGLE_STEP 23:23 /* RWXUF */
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#define NV_PRAMIN_CTX_0_SINGLE_STEP_DISABLE 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_SINGLE_STEP_ENABLE 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_PATCH_STATUS 24:24 /* RWXUF */
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#define NV_PRAMIN_CTX_0_PATCH_STATUS_INVALID 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_PATCH_STATUS_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_CONTEXT_SURFACE0 25:25 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CONTEXT_SURFACE0_INVALID 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_CONTEXT_SURFACE0_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_CONTEXT_SURFACE1 26:26 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CONTEXT_SURFACE1_INVALID 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_CONTEXT_SURFACE1_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_CONTEXT_PATTERN 27:27 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CONTEXT_PATTERN_INVALID 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_CONTEXT_PATTERN_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_CONTEXT_ROP 28:28 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CONTEXT_ROP_INVALID 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_CONTEXT_ROP_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_CONTEXT_BETA1 29:29 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CONTEXT_BETA1_INVALID 0x00000000 /* RWD-V */
|
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#define NV_PRAMIN_CTX_0_CONTEXT_BETA1_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_0_CONTEXT_BETA4 30:30 /* RWXUF */
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#define NV_PRAMIN_CTX_0_CONTEXT_BETA4_INVALID 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_0_CONTEXT_BETA4_VALID 0x00000001 /* RW--V */
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#define NV_PRAMIN_CTX_1(i) (0x00700004 + (i)*16) /* RW--M */
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#define NV_PRAMIN_CTX_1__SIZE_1 0x10000 /* */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT 7:0 /* RWXUF */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_INVALID 0x00 /* RWD-V */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_LE_M1 0x02 /* RW--V */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_018 0x01 /* RWC-V */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_044 0x01 /* RWC-V */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_04A 0x01 /* RWC-V */
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#define NV_PRAMIN_CTX_1_MONO_FORMAT_04B 0x01 /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT 15:8 /* RWXUF */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_INVALID 0x00 /* RWD-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */
|
|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */
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|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */
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|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */
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|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */
|
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */
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|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_017 0x00000002 /* RWC-V */
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|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_018 0x00000002 /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_01C 0x00000003 /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_01D 0x00000003 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_01E 0x00000003 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_021 0x00000001 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_036 0x00000001 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_037 0x00000006 /* RWC-V */
|
|
#define NV_PRAMIN_CTX_1_COLOR_FORMAT_044 0x0000000B /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_04A 0x0000000C /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_04B 0x00000003 /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_057 0x0000000B /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_05C 0x0000000C /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_05D 0x0000000C /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_05E 0x0000000C /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_060 0x0000000A /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_061 0x0000000A /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_076 0x0000000A /* RWC-V */
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#define NV_PRAMIN_CTX_1_COLOR_FORMAT_077 0x00000006 /* RWC-V */
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#define NV_PRAMIN_CTX_1_NOTIFY_INSTANCE 31:16 /* RWXUF */
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#define NV_PRAMIN_CTX_1_NOTIFY_INSTANCE_INVALID 0x0000 /* RWD-V */
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#define NV_PRAMIN_CTX_2(i) (0x00700008 + (i)*16) /* RW--M */
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#define NV_PRAMIN_CTX_2__SIZE_1 0x10000 /* */
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#define NV_PRAMIN_CTX_2_DMA_0_INSTANCE 15:0 /* RWXUF */
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#define NV_PRAMIN_CTX_2_DMA_0_INSTANCE_INVALID 0x0000 /* RWD-V */
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#define NV_PRAMIN_CTX_2_DMA_1_INSTANCE 31:16 /* RWXUF */
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#define NV_PRAMIN_CTX_2_DMA_1_INSTANCE_INVALID 0x0000 /* RWD-V */
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#define NV_PRAMIN_CTX_3(i) (0x0070000C + (i)*16) /* RW--M */
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#define NV_PRAMIN_CTX_3__SIZE_1 0x10000 /* */
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#define NV_PRAMIN_CTX_3_METHOD_TRAPS 31:0 /* RWXUF */
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|
#define NV_PRAMIN_CTX_3_METHOD_TRAPS_DISABLED 0x00000000 /* RWD-V */
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#define NV_PRAMIN_CTX_4(i) (0x00700010 + (i)*16) /* RW--M */
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#define NV_PRAMIN_DATA032(i) (0x00700000+(i)*4) /* RW-4A */
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#define NV_PRAMIN_DATA032__SIZE_1 524288 /* */
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#define NV_PRAMIN_DATA032_VALUE 31:0 /* RWXUF */
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#define NV_PRAMIN_DATA016(i) (0x00700000+((i)/3)*4+((i)%3)) /* RW-2A */
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#define NV_PRAMIN_DATA016__SIZE_1 1572864 /* */
|
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#define NV_PRAMIN_DATA016_VALUE 15:0 /* RWXUF */
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#define NV_PRAMIN_DATA008(i) (0x00700000+(i)) /* RW-1A */
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#define NV_PRAMIN_DATA008__SIZE_1 2097152 /* */
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#define NV_PRAMIN_DATA008_VALUE 7:0 /* RWXUF */
|
|
/* dev_ram.ref */
|
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#define NV_FIFO_DMA_OPCODE ( 0*32+31):( 0*32+29) /* RWXUF */
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#define NV_FIFO_DMA_OPCODE_METHOD 0x00000000 /* ----V */
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#define NV_FIFO_DMA_OPCODE_JUMP 0x00000001 /* ----V */
|
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#define NV_FIFO_DMA_OPCODE_NONINC_METHOD 0x00000002 /* ----V */
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#define NV_FIFO_DMA_OPCODE2 ( 0*32+ 1):( 0*32+ 0) /* RWXUF */
|
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#define NV_FIFO_DMA_OPCODE2_NONE 0x00000000 /* ----V */
|
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#define NV_FIFO_DMA_OPCODE2_JUMP_LONG 0x00000001 /* ----V */
|
|
#define NV_FIFO_DMA_OPCODE2_CALL 0x00000002 /* ----V */
|
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#define NV_FIFO_DMA_OPCODE ( 0*32+31):( 0*32+29) /* RWXUF */
|
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#define NV_FIFO_DMA_OPCODE_METHOD 0x00000000 /* ----V */
|
|
#define NV_FIFO_DMA_OPCODE_NONINC_METHOD 0x00000002 /* ----V */
|
|
#define NV_FIFO_DMA_METHOD_COUNT ( 0*32+28):( 0*32+18) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE3 ( 0*32+17):( 0*32+16) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE3_NONE 0x00000000 /* ----V */
|
|
#define NV_FIFO_DMA_METHOD_SUBCHANNEL ( 0*32+15):( 0*32+13) /* RWXUF */
|
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#define NV_FIFO_DMA_METHOD_ADDRESS ( 0*32+12):( 0*32+ 2) /* RWXUF */
|
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#define NV_FIFO_DMA_OPCODE2 ( 0*32+ 1):( 0*32+ 0) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE2_NONE 0x00000000 /* ----V */
|
|
#define NV_FIFO_DMA_DATA ( 1*32+31):( 1*32+ 0) /* RWXUF */
|
|
#define NV_FIFO_DMA_NOP 0x00000000 /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE ( 0*32+31):( 0*32+29) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE_JUMP 0x00000001 /* ----V */
|
|
#define NV_FIFO_DMA_OPCODE2 ( 0*32+ 1):( 0*32+ 0) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE2_NONE 0x00000000 /* ----V */
|
|
#define NV_FIFO_DMA_JUMP_OFFSET ( 0*32+28):( 0*32+ 2) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE2 ( 0*32+ 1):( 0*32+ 0) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE2_JUMP_LONG 0x00000001 /* ----V */
|
|
#define NV_FIFO_DMA_JUMP_LONG_OFFSET ( 0*32+31):( 0*32+ 2) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE2 ( 0*32+ 1):( 0*32+ 0) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE2_CALL 0x00000002 /* ----V */
|
|
#define NV_FIFO_DMA_CALL_OFFSET ( 0*32+31):( 0*32+ 2) /* RWXUF */
|
|
#define NV_FIFO_DMA_RETURN 0x00020000 /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE3 ( 0*32+17):( 0*32+16) /* RWXUF */
|
|
#define NV_FIFO_DMA_OPCODE3_RETURN 0x00000002 /* ----V */
|
|
/* dev_ram.ref */
|
|
#define NV_PRAM 0x00006FFF:0x00006000 /* RW--D */
|
|
/* dev_fb.ref */
|
|
#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */
|
|
#define NV_PFB_DEBUG_0 0x00100080 /* RW-4R */
|
|
#define NV_PFB_DEBUG_0_FINE_SEL 2:0 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_FINE_SEL_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_MRS 4:4 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_MRS_256 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_MRS_2 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_SPARE0 8:8 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_SPARE0_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_SPARE0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2NV 16:16 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2NV_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2NV_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2CPU 17:17 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2CPU_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2CPU_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2AGP 18:18 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2AGP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2AGP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2LDT 19:19 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2LDT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_RR_M2LDT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_FA 24:24 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_FA_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_XTRA_SETTLE_FA_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_BURST_INTERRUPT 27:27 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_BURST_INTERRUPT_ENABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_BURST_INTERRUPT_DISABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_SPARE1 28:28 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_SPARE1_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_SPARE1_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_SPARE2 29:29 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_SPARE2_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_SPARE2_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_SPARE3 30:30 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_SPARE3_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_SPARE3_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_DEBUG_0_SPARE4 31:31 /* RWIVF */
|
|
#define NV_PFB_DEBUG_0_SPARE4_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_DEBUG_0_SPARE4_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX 0x001000F0 /* RW-4R */
|
|
#define NV_PFB_RDI_INDEX_ADDRESS 12:6 /* RWIVF */
|
|
#define NV_PFB_RDI_INDEX_ADDRESS_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_RDI_INDEX_SELECT 24:16 /* RWIVF */
|
|
#define NV_PFB_RDI_INDEX_SELECT_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_LPQ_P0 0x00000100 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_LPQ_P1 0x00000101 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_LPQ_P2 0x00000102 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_LPQ_P3 0x00000103 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_ZOQ_P0 0x00000104 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_ZOQ_P1 0x00000105 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_ZOQ_P2 0x00000106 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_ZOQ_P3 0x00000107 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T0Q_P0 0x00000108 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T0Q_P1 0x00000109 /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T0Q_P2 0x0000010A /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T0Q_P3 0x0000010B /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T1Q_P0 0x0000010C /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T1Q_P1 0x0000010D /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T1Q_P2 0x0000010E /* RW--V */
|
|
#define NV_PFB_RDI_INDEX_SELECT_FA_T1Q_P3 0x0000010F /* RW--V */
|
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZRQ_P0 0x00000110 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZRQ_P1 0x00000111 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZRQ_P2 0x00000112 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZRQ_P3 0x00000113 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQ_P0 0x00000114 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQ_P1 0x00000115 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQ_P2 0x00000116 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQ_P3 0x00000117 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CRQ_P0 0x00000118 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CRQ_P1 0x00000119 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CRQ_P2 0x0000011A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CRQ_P3 0x0000011B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQ_P0 0x0000011C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQ_P1 0x0000011D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQ_P2 0x0000011E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQ_P3 0x0000011F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_EXTQ_P0 0x00000120 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_EXTQ_P1 0x00000121 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_EXTQ_P2 0x00000122 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_EXTQ_P3 0x00000123 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_HP_HPQ_P0 0x00000124 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_HP_HPQ_P1 0x00000125 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_HP_HPQ_P2 0x00000126 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_HP_HPQ_P3 0x00000127 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_AGP_D 0x00000128 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_AGP_BE 0x00000129 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_ISO_D 0x0000012A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_ISO_BE 0x0000012B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_NONISO_D 0x0000012C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_NONISO_BE 0x0000012D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_CPU_D 0x0000012E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_SNQ_CPU_BE 0x0000012F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_ZTAG_P0 0x00000130 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_ZTAG_P1 0x00000131 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_ZTAG_P2 0x00000132 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_ZTAG_P3 0x00000133 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_GART_INTFC_CPU_D 0x00000134 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_GART_INTFC_CPU_BE 0x00000135 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_WBC_DATA 0x00000136 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_CPUQ_P0 0x00000138 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_CPUQ_P1 0x00000139 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_CPUQ_P2 0x0000013A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_CPUQ_P3 0x0000013B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_LDTQ_P0 0x0000013C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_LDTQ_P1 0x0000013D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_LDTQ_P2 0x0000013E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_PA_RTARB_LDTQ_P3 0x0000013F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_RWAQ_P0 0x00000140 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_RWAQ_P1 0x00000141 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_RWAQ_P2 0x00000142 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_RWAQ_P3 0x00000143 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_PRQ_P0 0x00000148 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_PRQ_P1 0x00000149 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_PRQ_P2 0x0000014A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_PRQ_P3 0x0000014B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_ACQ_P0 0x0000014C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_ACQ_P1 0x0000014D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_ACQ_P2 0x0000014E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQHP_ACQ_P3 0x0000014F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_LPQW_P0 0x00000150 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_LPQW_P1 0x00000151 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_LPQW_P2 0x00000152 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_LPQW_P3 0x00000153 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQW_P0 0x00000154 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQW_P1 0x00000155 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQW_P2 0x00000156 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_ZWQW_P3 0x00000157 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQW_P0 0x00000158 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQW_P1 0x00000159 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQW_P2 0x0000015A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_FA_CWQW_P3 0x0000015B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_AGP_P0 0x0000015C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_AGP_P1 0x0000015D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_AGP_P2 0x0000015E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_AGP_P3 0x0000015F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_ISO_P0 0x00000160 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_ISO_P1 0x00000161 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_ISO_P2 0x00000162 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_ISO_P3 0x00000163 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_NONISO_P0 0x00000164 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_NONISO_P1 0x00000165 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_NONISO_P2 0x00000166 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_NONISO_P3 0x00000167 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_CPU_P0 0x00000168 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_CPU_P1 0x00000169 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_CPU_P2 0x0000016A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_CPU_P3 0x0000016B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0HP_P0 0x0000016C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0HP_P1 0x0000016D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0HP_P2 0x0000016E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0HP_P3 0x0000016F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0LP_P0 0x00000170 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0LP_P1 0x00000171 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0LP_P2 0x00000172 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W0LP_P3 0x00000173 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W1LP_P0 0x00000174 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W1LP_P1 0x00000175 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W1LP_P2 0x00000176 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W1LP_P3 0x00000177 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W2LP_P0 0x00000178 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W2LP_P1 0x00000179 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W2LP_P2 0x0000017A /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W2LP_P3 0x0000017B /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W3HP_P0 0x0000017C /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W3HP_P1 0x0000017D /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W3HP_P2 0x0000017E /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_RR_W3HP_P3 0x0000017F /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWAQ_P0 0x000001A0 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWAQ_P1 0x000001A1 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWAQ_P2 0x000001A2 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWAQ_P3 0x000001A3 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWDQ_P0 0x000001A4 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWDQ_P1 0x000001A5 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWDQ_P2 0x000001A6 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_RWDQ_P3 0x000001A7 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_PRQ_P0 0x000001A8 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_PRQ_P1 0x000001A9 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_PRQ_P2 0x000001AA /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_PRQ_P3 0x000001AB /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_ACQ_P0 0x000001AC /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_ACQ_P1 0x000001AD /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_ACQ_P2 0x000001AE /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQFA_ACQ_P3 0x000001AF /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWAQ_P0 0x000001B0 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWAQ_P1 0x000001B1 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWAQ_P2 0x000001B2 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWAQ_P3 0x000001B3 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWDQ_P0 0x000001B4 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWDQ_P1 0x000001B5 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWDQ_P2 0x000001B6 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_RWDQ_P3 0x000001B7 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_PRQ_P0 0x000001B8 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_PRQ_P1 0x000001B9 /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_PRQ_P2 0x000001BA /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_PRQ_P3 0x000001BB /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_ACQ_P0 0x000001BC /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_ACQ_P1 0x000001BD /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_ACQ_P2 0x000001BE /* RW--V */
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#define NV_PFB_RDI_INDEX_SELECT_MC_CMDQRT_ACQ_P3 0x000001BF /* RW--V */
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#define NV_PFB_RDI_DATA(i) (0x00100100+(i)*4) /* RW-4A */
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#define NV_PFB_RDI_DATA__SIZE_1 16 /* */
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#define NV_PFB_RDI_DATA_FIELD 31:0 /* RW-VF */
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#define NV_PFB_CFG0 0x00100200 /* RW-4R */
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#define NV_PFB_CFG0_PART 1:0 /* RWIVF */
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#define NV_PFB_CFG0_PART_4 0x00000003 /* RWI-V */
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#define NV_PFB_CFG0_PART_1 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_PART_2 0x00000001 /* RW--V */
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#define NV_PFB_CFG0_EXTBANK 8:8 /* RWIVF */
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#define NV_PFB_CFG0_EXTBANK_0 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_EXTBANK_1 0x00000001 /* RWI-V */
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#define NV_PFB_CFG0_BURST_INT_RD2RD 16:16 /* RWIVF */
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#define NV_PFB_CFG0_BURST_INT_RD2RD_DISABLED 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_BURST_INT_RD2RD_ENABLED 0x00000001 /* RWI-V */
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#define NV_PFB_CFG0_BURST_INT_WR2WR 17:17 /* RWIVF */
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#define NV_PFB_CFG0_BURST_INT_WR2WR_DISABLED 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_BURST_INT_WR2WR_ENABLED 0x00000001 /* RWI-V */
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#define NV_PFB_CFG0_BURST_INT_RD2PRE 18:18 /* RWIVF */
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#define NV_PFB_CFG0_BURST_INT_RD2PRE_DISABLED 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_BURST_INT_RD2PRE_ENABLED 0x00000001 /* RWI-V */
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#define NV_PFB_CFG0_SPARE0 19:19 /* RWIVF */
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#define NV_PFB_CFG0_SPARE0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFB_CFG0_SPARE0_ENABLED 0x00000001 /* RW--V */
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#define NV_PFB_CFG0_AUTO_PRE_RD 24:24 /* RWIVF */
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#define NV_PFB_CFG0_AUTO_PRE_RD_DISABLED 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_AUTO_PRE_RD_ENABLED 0x00000001 /* RWI-V */
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#define NV_PFB_CFG0_AUTO_PRE_WR 25:25 /* RWIVF */
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#define NV_PFB_CFG0_AUTO_PRE_WR_DISABLED 0x00000000 /* RW--V */
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#define NV_PFB_CFG0_AUTO_PRE_WR_ENABLED 0x00000001 /* RWI-V */
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#define NV_PFB_CFG0_SYNC_MODE 26:26 /* RWIVF */
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#define NV_PFB_CFG0_SYNC_MODE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFB_CFG0_SYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PFB_CFG0_TWO_CLK_ADDR 27:27 /* RWIVF */
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#define NV_PFB_CFG0_TWO_CLK_ADDR_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFB_CFG0_TWO_CLK_ADDR_ENABLE 0x00000001 /* RW--V */
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#define NV_PFB_CFG1 0x00100204 /* RW-4R */
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#define NV_PFB_CFG1_APA 6:4 /* RWIVF */
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#define NV_PFB_CFG1_APA_A8 0x00000000 /* RWI-V */
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#define NV_PFB_CFG1_APA_A9 0x00000001 /* RW--V */
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#define NV_PFB_CFG1_APA_A10 0x00000002 /* RW--V */
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#define NV_PFB_CFG1_APA_A11 0x00000003 /* RW--V */
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#define NV_PFB_CFG1_APA_A12 0x00000004 /* RW--V */
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#define NV_PFB_CFG1_APB 10:8 /* RWIVF */
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#define NV_PFB_CFG1_APB_A8 0x00000000 /* RWI-V */
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#define NV_PFB_CFG1_APB_A9 0x00000001 /* RW--V */
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#define NV_PFB_CFG1_APB_A10 0x00000002 /* RW--V */
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#define NV_PFB_CFG1_APB_A11 0x00000003 /* RW--V */
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#define NV_PFB_CFG1_APB_A12 0x00000004 /* RW--V */
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#define NV_PFB_CFG1_COL 15:12 /* RWIVF */
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#define NV_PFB_CFG1_COL_8 0x00000008 /* RWI-V */
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#define NV_PFB_CFG1_COL_9 0x00000009 /* RW--V */
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#define NV_PFB_CFG1_COL_7 0x00000007 /* RW--V */
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#define NV_PFB_CFG1_COL_10 0x0000000A /* RW--V */
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#define NV_PFB_CFG1_ROWA 19:16 /* RWIVF */
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#define NV_PFB_CFG1_ROWA_11 0x00000003 /* RWI-V */
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#define NV_PFB_CFG1_ROWA_12 0x00000004 /* RW--V */
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#define NV_PFB_CFG1_ROWA_9 0x00000001 /* RW--V */
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#define NV_PFB_CFG1_ROWA_10 0x00000002 /* RW--V */
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#define NV_PFB_CFG1_ROWA_13 0x00000005 /* RW--V */
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#define NV_PFB_CFG1_ROWB 23:20 /* RWIVF */
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#define NV_PFB_CFG1_ROWB_11 0x00000003 /* RWI-V */
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#define NV_PFB_CFG1_ROWB_12 0x00000004 /* RW--V */
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#define NV_PFB_CFG1_ROWB_9 0x00000001 /* RW--V */
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#define NV_PFB_CFG1_ROWB_10 0x00000002 /* RW--V */
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#define NV_PFB_CFG1_ROWB_13 0x00000005 /* RW--V */
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#define NV_PFB_CFG1_BANKA 24:24 /* RWIVF */
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#define NV_PFB_CFG1_BANKA_2 0x00000001 /* RWI-V */
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#define NV_PFB_CFG1_BANKA_1 0x00000000 /* RW--V */
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#define NV_PFB_CFG1_BANKB 28:28 /* RWIVF */
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#define NV_PFB_CFG1_BANKB_2 0x00000001 /* RWI-V */
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#define NV_PFB_CFG1_BANKB_1 0x00000000 /* RW--V */
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#define NV_PFB_CSTATUS 0x0010020C /* R--4R */
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#define NV_PFB_CSTATUS_RAMAMOUNT_MS 0:0 /* R--VF */
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#define NV_PFB_CSTATUS_RAMAMOUNT_LS 31:20 /* R--VF */
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#define NV_PFB_REFCTRL 0x00100210 /* RW-4R */
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#define NV_PFB_REFCTRL_PUT 6:0 /* RWIVF */
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#define NV_PFB_REFCTRL_PUT_0 0x00000000 /* RWI-V */
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#define NV_PFB_REFCTRL_GET 14:8 /* RWIVF */
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#define NV_PFB_REFCTRL_GET_0 0x00000000 /* RWI-V */
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#define NV_PFB_REFCTRL_VALID 31:31 /* RWIVF */
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#define NV_PFB_REFCTRL_VALID_0 0x00000000 /* RWI-V */
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#define NV_PFB_REFCTRL_VALID_1 0x00000001 /* RW--V */
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#define NV_PFB_NVM 0x00100214 /* RW-4R */
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#define NV_PFB_NVM_MODE 0:0 /* RWIVF */
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#define NV_PFB_NVM_MODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFB_NVM_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PFB_NVM_LIMIT 7:4 /* RW-VF */
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#define NV_PFB_NVM_LIMIT_64K 0x00000000 /* RW--V */
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#define NV_PFB_NVM_LIMIT_128K 0x00000001 /* RW--V */
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#define NV_PFB_NVM_LIMIT_192K 0x00000002 /* RW--V */
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#define NV_PFB_NVM_LIMIT_256K 0x00000003 /* RW--V */
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#define NV_PFB_NVM_LIMIT_320K 0x00000004 /* RW--V */
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#define NV_PFB_NVM_LIMIT_384K 0x00000005 /* RW--V */
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#define NV_PFB_NVM_LIMIT_448K 0x00000006 /* RW--V */
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#define NV_PFB_NVM_LIMIT_512K 0x00000007 /* RW--V */
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#define NV_PFB_NVM_LIMIT_576K 0x00000008 /* RW--V */
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#define NV_PFB_NVM_LIMIT_640K 0x00000009 /* RW--V */
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#define NV_PFB_NVM_LIMIT_704K 0x0000000A /* RW--V */
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#define NV_PFB_NVM_LIMIT_768K 0x0000000B /* RW--V */
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#define NV_PFB_NVM_LIMIT_832K 0x0000000C /* RW--V */
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#define NV_PFB_NVM_LIMIT_896K 0x0000000D /* RW--V */
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#define NV_PFB_NVM_LIMIT_960K 0x0000000E /* RW--V */
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#define NV_PFB_NVM_LIMIT_1024K 0x0000000F /* RW--V */
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#define NV_PFB_PIN 0x00100218 /* RW-4R */
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#define NV_PFB_PIN_CKE 0:0 /* RWIVF */
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#define NV_PFB_PIN_CKE_POWERDOWN 0x00000000 /* RWI-V */
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#define NV_PFB_PIN_CKE_NORMAL 0x00000001 /* RW--V */
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#define NV_PFB_PIN_DQM 4:4 /* RWIVF */
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#define NV_PFB_PIN_DQM_NORMAL 0x00000000 /* RWI-V */
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#define NV_PFB_PIN_DQM_INACTIVE 0x00000001 /* RW--V */
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#define NV_PFB_PAD 0x0010021C /* RW-4R */
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#define NV_PFB_PAD_CKE 0:0 /* RWIVF */
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#define NV_PFB_PAD_CKE_TRISTATE 0x00000000 /* RWI-V */
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#define NV_PFB_PAD_CKE_NORMAL 0x00000001 /* RW--V */
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#define NV_PFB_TIMING0 0x00100220 /* RW-4R */
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#define NV_PFB_TIMING0_RC 4:0 /* RWIVF */
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#define NV_PFB_TIMING0_RC_12 0x0000000C /* RWI-V */
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#define NV_PFB_TIMING0_RC_31 0x0000001F /* RW--V */
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#define NV_PFB_TIMING0_RFC 12:8 /* RWIVF */
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#define NV_PFB_TIMING0_RFC_14 0x0000000E /* RWI-V */
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#define NV_PFB_TIMING0_RFC_31 0x0000001F /* RW--V */
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#define NV_PFB_TIMING0_RAS 19:15 /* RWIVF */
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#define NV_PFB_TIMING0_RAS_8 0x00000008 /* RWI-V */
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#define NV_PFB_TIMING0_RAS_31 0x0000001F /* RW--V */
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#define NV_PFB_TIMING0_RD_RCD 23:20 /* RWIVF */
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#define NV_PFB_TIMING0_RD_RCD_4 0x00000004 /* RWI-V */
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#define NV_PFB_TIMING0_RD_RCD_15 0x0000000F /* RW--V */
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#define NV_PFB_TIMING0_WR_RCD 27:24 /* RWIVF */
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#define NV_PFB_TIMING0_WR_RCD_4 0x00000004 /* RWI-V */
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#define NV_PFB_TIMING0_WR_RCD_15 0x0000000F /* RW--V */
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#define NV_PFB_TIMING0_RP 31:28 /* RWIVF */
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#define NV_PFB_TIMING0_RP_4 0x00000004 /* RWI-V */
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#define NV_PFB_TIMING0_RP_15 0x0000000F /* RW--V */
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#define NV_PFB_TIMING1 0x00100224 /* RW-4R */
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#define NV_PFB_TIMING1_R2W 7:4 /* RWIVF */
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#define NV_PFB_TIMING1_R2W_5 0x00000005 /* RWI-V */
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#define NV_PFB_TIMING1_R2W_7 0x00000007 /* RW--V */
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#define NV_PFB_TIMING1_R2P 11:8 /* RWIVF */
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#define NV_PFB_TIMING1_R2P_1 0x00000001 /* RW--V */
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#define NV_PFB_TIMING1_R2P_2 0x00000002 /* RWI-V */
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#define NV_PFB_TIMING1_R2P_3 0x00000003 /* RW--V */
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#define NV_PFB_TIMING1_R2P_7 0x00000007 /* RW--V */
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#define NV_PFB_TIMING1_REXT 14:12 /* RWIVF */
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#define NV_PFB_TIMING1_REXT_1 0x00000001 /* RW--V */
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#define NV_PFB_TIMING1_REXT_2 0x00000002 /* RWI-V */
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#define NV_PFB_TIMING1_W2R 19:16 /* RWIVF */
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#define NV_PFB_TIMING1_W2R_3 0x00000003 /* RW--V */
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#define NV_PFB_TIMING1_W2R_4 0x00000004 /* RWI-V */
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#define NV_PFB_TIMING1_W2R_7 0x00000007 /* RW--V */
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#define NV_PFB_TIMING1_W2P 23:20 /* RWIVF */
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#define NV_PFB_TIMING1_W2P_4 0x00000004 /* RW--V */
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#define NV_PFB_TIMING1_W2P_5 0x00000005 /* RWI-V */
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#define NV_PFB_TIMING1_W2P_7 0x00000007 /* RW--V */
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#define NV_PFB_TIMING1_RRD 26:24 /* RWIVF */
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#define NV_PFB_TIMING1_RRD_1 0x00000001 /* RW--V */
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#define NV_PFB_TIMING1_RRD_2 0x00000002 /* RWI-V */
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#define NV_PFB_TIMING1_RRD_7 0x00000007 /* RW--V */
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#define NV_PFB_TIMING1_DOE_TYPE 27:27 /* RWIVF */
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#define NV_PFB_TIMING1_DOE_TYPE_0 0x00000000 /* RWI-V */
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#define NV_PFB_TIMING1_DOE_DLY 30:28 /* RWIVF */
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#define NV_PFB_TIMING1_DOE_DLY_7 0x00000007 /* RWI-V */
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#define NV_PFB_TIMING2 0x00100228 /* RW-4R */
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#define NV_PFB_TIMING2_REFRESH_LO 4:0 /* C-IVF */
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#define NV_PFB_TIMING2_REFRESH_LO_1F 0x0000001F /* C-I-V */
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#define NV_PFB_TIMING2_REFRESH 15:5 /* RWIVF */
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#define NV_PFB_TIMING2_REFRESH_0 0x00000000 /* RW--V */
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#define NV_PFB_TIMING2_REFRESH_47 0x0000002F /* RWI-V */
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#define NV_PFB_TIMING2_QUSE 18:16 /* RWIVF */
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#define NV_PFB_TIMING2_QUSE_2 0x00000002 /* RWI-V */
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#define NV_PFB_TIMING2_QUSE_MIN 0x00000000 /* RW--V */
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#define NV_PFB_TIMING2_QUSE_MAX 0x00000007 /* RW--V */
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#define NV_PFB_TIMING2_QINC 23:20 /* RWIVF */
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#define NV_PFB_TIMING2_QINC_1 0x00000001 /* RWI-V */
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#define NV_PFB_TIMING2_QINC_MIN 0x00000000 /* RW--V */
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#define NV_PFB_TIMING2_QINC_MAX 0x0000000F /* RW--V */
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#define NV_PFB_TIMING2_RDV 27:24 /* RWIVF */
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#define NV_PFB_TIMING2_RDV_7 0x00000007 /* RW--V */
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#define NV_PFB_TIMING2_RDV_8 0x00000008 /* RWI-V */
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#define NV_PFB_TIMING2_RDV_MIN 0x00000002 /* RW--V */
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#define NV_PFB_TIMING2_RDV_MAX 0x0000000E /* RW--V */
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#define NV_PFB_TILE(i) (0x00100240+(i)*16) /* RW-4A */
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#define NV_PFB_TILE__SIZE_1 8 /* */
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#define NV_PFB_TILE_REGION 0:0 /* RWIVF */
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#define NV_PFB_TILE_REGION_INVALID 0x00000000 /* RWI-V */
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#define NV_PFB_TILE_REGION_VALID 0x00000001 /* RW--V */
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#define NV_PFB_TILE_BANK0_SENSE 1:1 /* RWIVF */
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#define NV_PFB_TILE_BANK0_SENSE_0 0x00000000 /* RWI-V */
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#define NV_PFB_TILE_BANK0_SENSE_1 0x00000001 /* RW--V */
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#define NV_PFB_TILE_ADR 31:14 /* RW-UF */
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#define NV_PFB_TLIMIT(i) (0x00100244+(i)*16) /* RW-4A */
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#define NV_PFB_TLIMIT__SIZE_1 8 /* */
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#define NV_PFB_TLIMIT_ADR 31:14 /* RW-UF */
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#define NV_PFB_TLIMIT_ADR_LO 13:0 /* C-IVF */
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#define NV_PFB_TLIMIT_ADR_LO_3FFF 0x000003FFF /* C-I-V */
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#define NV_PFB_TSIZE(i) (0x00100248+(i)*16) /* RW-4A */
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#define NV_PFB_TSIZE__SIZE_1 8 /* */
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#define NV_PFB_TSIZE_PITCH 15:8 /* RW-UF */
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#define NV_PFB_TSIZE_PITCH_0200 0x00000002 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0300 0x00000003 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0400 0x00000004 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0500 0x00000005 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0600 0x00000006 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0700 0x00000007 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0800 0x00000008 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0A00 0x0000000A /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0C00 0x0000000C /* RW--V */
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#define NV_PFB_TSIZE_PITCH_0E00 0x0000000E /* RW--V */
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#define NV_PFB_TSIZE_PITCH_1000 0x00000010 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_1400 0x00000014 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_1800 0x00000018 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_1C00 0x0000001C /* RW--V */
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#define NV_PFB_TSIZE_PITCH_2000 0x00000020 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_2800 0x00000028 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_3000 0x00000030 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_3800 0x00000038 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_4000 0x00000040 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_5000 0x00000050 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_6000 0x00000060 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_7000 0x00000070 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_8000 0x00000080 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_A000 0x000000A0 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_C000 0x000000C0 /* RW--V */
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#define NV_PFB_TSIZE_PITCH_E000 0x000000E0 /* RW--V */
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#define NV_PFB_TSTATUS(i) (0x0010024C+(i)*16) /* R--4A */
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#define NV_PFB_TSTATUS__SIZE_1 8 /* */
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#define NV_PFB_TSTATUS_PRIME 1:0 /* R--VF */
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#define NV_PFB_TSTATUS_PRIME_1 0x00000000 /* R---V */
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#define NV_PFB_TSTATUS_PRIME_3 0x00000001 /* R---V */
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#define NV_PFB_TSTATUS_PRIME_5 0x00000002 /* R---V */
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#define NV_PFB_TSTATUS_PRIME_7 0x00000003 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR 6:4 /* R--VF */
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#define NV_PFB_TSTATUS_FACTOR_1 0x00000000 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_2 0x00000001 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_4 0x00000002 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_8 0x00000003 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_16 0x00000004 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_32 0x00000005 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_64 0x00000006 /* R---V */
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#define NV_PFB_TSTATUS_FACTOR_128 0x00000007 /* R---V */
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#define NV_PFB_TSTATUS_REGION 31:31 /* R-IVF */
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#define NV_PFB_TSTATUS_REGION_INVALID 0x00000000 /* R-I-V */
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#define NV_PFB_TSTATUS_REGION_VALID 0x00000001 /* R---V */
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#define NV_PFB_MRS 0x001002C0 /* RW-4R */
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#define NV_PFB_MRS_A0 0:0 /* RWIVF */
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#define NV_PFB_MRS_A0_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A0_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A1 1:1 /* RWIVF */
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#define NV_PFB_MRS_A1_0 0x00000000 /* RW--V */
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#define NV_PFB_MRS_A1_1 0x00000001 /* RWI-V */
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#define NV_PFB_MRS_A2 2:2 /* RWIVF */
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#define NV_PFB_MRS_A2_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A2_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A3 3:3 /* RWIVF */
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#define NV_PFB_MRS_A3_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A3_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A4 4:4 /* RWIVF */
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#define NV_PFB_MRS_A4_0 0x00000000 /* RW--V */
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#define NV_PFB_MRS_A4_1 0x00000001 /* RWI-V */
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#define NV_PFB_MRS_A5 5:5 /* RWIVF */
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#define NV_PFB_MRS_A5_0 0x00000000 /* RW--V */
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#define NV_PFB_MRS_A5_1 0x00000001 /* RWI-V */
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#define NV_PFB_MRS_A6 6:6 /* RWIVF */
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#define NV_PFB_MRS_A6_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A6_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A7 7:7 /* RWIVF */
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#define NV_PFB_MRS_A7_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A7_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A8 8:8 /* RWIVF */
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#define NV_PFB_MRS_A8_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A8_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A9 9:9 /* RWIVF */
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#define NV_PFB_MRS_A9_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A9_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A10 10:10 /* RWIVF */
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#define NV_PFB_MRS_A10_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A10_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A11 11:11 /* RWIVF */
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#define NV_PFB_MRS_A11_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A11_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_A12 12:12 /* RWIVF */
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#define NV_PFB_MRS_A12_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_A12_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_BA0 20:20 /* RWIVF */
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#define NV_PFB_MRS_BA0_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_BA0_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_BA1 21:21 /* RWIVF */
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#define NV_PFB_MRS_BA1_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_BA1_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS 0x001002C4 /* RW-4R */
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#define NV_PFB_EMRS_A0 0:0 /* RWIVF */
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#define NV_PFB_EMRS_A0_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A0_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A1 1:1 /* RWIVF */
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#define NV_PFB_EMRS_A1_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A1_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A2 2:2 /* RWIVF */
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#define NV_PFB_EMRS_A2_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A2_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A3 3:3 /* RWIVF */
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#define NV_PFB_EMRS_A3_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A3_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A4 4:4 /* RWIVF */
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#define NV_PFB_EMRS_A4_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A4_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A5 5:5 /* RWIVF */
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#define NV_PFB_EMRS_A5_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A5_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A6 6:6 /* RWIVF */
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#define NV_PFB_EMRS_A6_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A6_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_A7 7:7 /* RWIVF */
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#define NV_PFB_EMRS_A7_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A7_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A8 8:8 /* RWIVF */
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#define NV_PFB_EMRS_A8_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A8_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A9 9:9 /* RWIVF */
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#define NV_PFB_EMRS_A9_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_A9_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_A10 10:10 /* RWIVF */
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#define NV_PFB_EMRS_A10_0 0x00000000 /* RWI-V */
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|
#define NV_PFB_EMRS_A10_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_A11 11:11 /* RWIVF */
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#define NV_PFB_EMRS_A11_0 0x00000000 /* RWI-V */
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|
#define NV_PFB_EMRS_A11_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_A12 12:12 /* RWIVF */
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#define NV_PFB_EMRS_A12_0 0x00000000 /* RWI-V */
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|
#define NV_PFB_EMRS_A12_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_BA0 20:20 /* RWIVF */
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#define NV_PFB_EMRS_BA0_0 0x00000000 /* RW--V */
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|
#define NV_PFB_EMRS_BA0_1 0x00000001 /* RWI-V */
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|
#define NV_PFB_EMRS_BA1 21:21 /* RWIVF */
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#define NV_PFB_EMRS_BA1_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_BA1_1 0x00000001 /* RW--V */
|
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#define NV_PFB_MRS_EXT 0x001002C8 /* RW-4R */
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#define NV_PFB_MRS_EXT_A0 0:0 /* RWIVF */
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#define NV_PFB_MRS_EXT_A0_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A0_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A1 1:1 /* RWIVF */
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#define NV_PFB_MRS_EXT_A1_0 0x00000000 /* RW--V */
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#define NV_PFB_MRS_EXT_A1_1 0x00000001 /* RWI-V */
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#define NV_PFB_MRS_EXT_A2 2:2 /* RWIVF */
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#define NV_PFB_MRS_EXT_A2_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A2_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A3 3:3 /* RWIVF */
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#define NV_PFB_MRS_EXT_A3_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A3_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A4 4:4 /* RWIVF */
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#define NV_PFB_MRS_EXT_A4_0 0x00000000 /* RW--V */
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#define NV_PFB_MRS_EXT_A4_1 0x00000001 /* RWI-V */
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#define NV_PFB_MRS_EXT_A5 5:5 /* RWIVF */
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#define NV_PFB_MRS_EXT_A5_0 0x00000000 /* RW--V */
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#define NV_PFB_MRS_EXT_A5_1 0x00000001 /* RWI-V */
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#define NV_PFB_MRS_EXT_A6 6:6 /* RWIVF */
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#define NV_PFB_MRS_EXT_A6_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A6_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A7 7:7 /* RWIVF */
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#define NV_PFB_MRS_EXT_A7_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A7_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A8 8:8 /* RWIVF */
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#define NV_PFB_MRS_EXT_A8_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A8_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A9 9:9 /* RWIVF */
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#define NV_PFB_MRS_EXT_A9_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A9_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A10 10:10 /* RWIVF */
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#define NV_PFB_MRS_EXT_A10_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A10_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A11 11:11 /* RWIVF */
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#define NV_PFB_MRS_EXT_A11_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A11_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_A12 12:12 /* RWIVF */
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#define NV_PFB_MRS_EXT_A12_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_A12_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_BA0 20:20 /* RWIVF */
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#define NV_PFB_MRS_EXT_BA0_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_BA0_1 0x00000001 /* RW--V */
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#define NV_PFB_MRS_EXT_BA1 21:21 /* RWIVF */
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#define NV_PFB_MRS_EXT_BA1_0 0x00000000 /* RWI-V */
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#define NV_PFB_MRS_EXT_BA1_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT 0x001002CC /* RW-4R */
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#define NV_PFB_EMRS_EXT_A0 0:0 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A0_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A0_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT_A1 1:1 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A1_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A1_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT_A2 2:2 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A2_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A2_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT_A3 3:3 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A3_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A3_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT_A4 4:4 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A4_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A4_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT_A5 5:5 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A5_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A5_1 0x00000001 /* RW--V */
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#define NV_PFB_EMRS_EXT_A6 6:6 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_A6_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A6_1 0x00000001 /* RW--V */
|
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#define NV_PFB_EMRS_EXT_A7 7:7 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A7_0 0x00000000 /* RWI-V */
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#define NV_PFB_EMRS_EXT_A7_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_EXT_A8 8:8 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_A8_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_EMRS_EXT_A8_1 0x00000001 /* RW--V */
|
|
#define NV_PFB_EMRS_EXT_A9 9:9 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_A9_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_EMRS_EXT_A9_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_EXT_A10 10:10 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_A10_0 0x00000000 /* RWI-V */
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|
#define NV_PFB_EMRS_EXT_A10_1 0x00000001 /* RW--V */
|
|
#define NV_PFB_EMRS_EXT_A11 11:11 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_A11_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_EMRS_EXT_A11_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_EXT_A12 12:12 /* RWIVF */
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#define NV_PFB_EMRS_EXT_A12_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_EMRS_EXT_A12_1 0x00000001 /* RW--V */
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|
#define NV_PFB_EMRS_EXT_BA0 20:20 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_BA0_0 0x00000000 /* RW--V */
|
|
#define NV_PFB_EMRS_EXT_BA0_1 0x00000001 /* RWI-V */
|
|
#define NV_PFB_EMRS_EXT_BA1 21:21 /* RWIVF */
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|
#define NV_PFB_EMRS_EXT_BA1_0 0x00000000 /* RWI-V */
|
|
#define NV_PFB_EMRS_EXT_BA1_1 0x00000001 /* RW--V */
|
|
#define NV_PFB_REF 0x001002D0 /* -W-4R */
|
|
#define NV_PFB_REF_CMD 0:0 /* -WIVF */
|
|
#define NV_PFB_REF_CMD_REFRESH 0x00000000 /* -WI-V */
|
|
#define NV_PFB_REF_CMD_REFRESH_1 0x00000001 /* -W--T */
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|
#define NV_PFB_PRE 0x001002D4 /* -W-4R */
|
|
#define NV_PFB_PRE_CMD 0:0 /* -WIVF */
|
|
#define NV_PFB_PRE_CMD_PRECHARGE 0x00000000 /* -WI-V */
|
|
#define NV_PFB_PRE_CMD_PRECHARGE_1 0x00000001 /* -W--T */
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#define NV_PFB_ZCOMP(i) (0x00100300+(i)*4) /* RW-4A */
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|
#define NV_PFB_ZCOMP__SIZE_1 8 /* */
|
|
#define NV_PFB_ZCOMP_BASE_TAG_ADR 17:6 /* RW-UF */
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|
#define NV_PFB_ZCOMP_MODE 26:26 /* RWIVF */
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|
#define NV_PFB_ZCOMP_MODE_16 0x00000000 /* RW--V */
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#define NV_PFB_ZCOMP_MODE_32 0x00000001 /* RWI-V */
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|
#define NV_PFB_ZCOMP_ENDIAN 27:27 /* RWIVF */
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#define NV_PFB_ZCOMP_ENDIAN_LITTLE 0x00000000 /* RWI-V */
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#define NV_PFB_ZCOMP_ENDIAN_BIG 0x00000001 /* RW--V */
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#define NV_PFB_ZCOMP_AA 29:28 /* RWIVF */
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#define NV_PFB_ZCOMP_AA_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFB_ZCOMP_AA_CENTER_1 0x00000001 /* RW--V */
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#define NV_PFB_ZCOMP_AA_CENTER_CORNER_2 0x00000002 /* RW--V */
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#define NV_PFB_ZCOMP_AA_SQUARE_OFFSET_4 0x00000003 /* RW--V */
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#define NV_PFB_ZCOMP_EN 31:31 /* RWIVF */
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#define NV_PFB_ZCOMP_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_PFB_ZCOMP_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PFB_ZCOMP_MAX_TAG 0x00100320 /* R-X4R */
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#define NV_PFB_ZCOMP_MAX_TAG_ADR_LO 5:0 /* C-IVF */
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#define NV_PFB_ZCOMP_MAX_TAG_ADR_LO_3F 0x0000003F /* C-I-V */
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#define NV_PFB_ZCOMP_MAX_TAG_ADR 17:6 /* C-IVF */
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#define NV_PFB_ZCOMP_MAX_TAG_ADR_VALUE 0x0000012B /* C-I-V */
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#define NV_PFB_ZCOMP_OFFSET 0x00100324 /* RW-4R */
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#define NV_PFB_ZCOMP_OFFSET_ADR_SPACE 3:0 /* RW-UF */
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#define NV_PFB_ZCOMP_OFFSET_ZCULL_COMP_ONLY_EN 4:4 /* RWIVF */
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#define NV_PFB_ZCOMP_OFFSET_ZCULL_COMP_ONLY_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFB_ZCOMP_OFFSET_ZCULL_COMP_ONLY_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PFB_ZCOMP_OFFSET_ADR 25:14 /* RW-UF */
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#define NV_PFB_ZCOMP_OFFSET_EN 31:31 /* RWIVF */
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#define NV_PFB_ZCOMP_OFFSET_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_PFB_ZCOMP_OFFSET_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PFB_ARB_PREDIVIDER 0x00100328 /* RW-4R */
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#define NV_PFB_ARB_PREDIVIDER_DIV 7:0 /* RWIUF */
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#define NV_PFB_ARB_PREDIVIDER_DIV_0 0x00000000 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_1 0x00000001 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_2 0x00000002 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_3 0x00000003 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_4 0x00000004 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_5 0x00000005 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_6 0x00000006 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_7 0x00000007 /* RWIUV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_8 0x00000008 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_9 0x00000009 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_10 0x0000000A /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_11 0x0000000B /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_12 0x0000000C /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_13 0x0000000D /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_14 0x0000000E /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_15 0x0000000F /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_16 0x00000010 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_DIV_20 0x00000014 /* RW-UV */
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#define NV_PFB_ARB_PREDIVIDER_TIMEOUT_CONT_GNT 12:12 /* RWIUF */
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#define NV_PFB_ARB_PREDIVIDER_TIMEOUT_CONT_GNT_DISABLE 0x00000000 /* RWIUV */
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#define NV_PFB_ARB_PREDIVIDER_TIMEOUT_CONT_GNT_ENABLE 0x00000001 /* RW-UV */
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#define NV_PFB_ARB_TIMEOUT 0x0010032C /* RW-4R */
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#define NV_PFB_ARB_TIMEOUT_EXT 3:0 /* RWIUF */
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|
#define NV_PFB_ARB_TIMEOUT_EXT_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_EXT_14 0x0000000E /* RWIUV */
|
|
#define NV_PFB_ARB_TIMEOUT_EXT_DISABLE 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_LP 7:4 /* RWIUF */
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#define NV_PFB_ARB_TIMEOUT_LP_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_LP_DISABLE 0x0000000F /* RWIUV */
|
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#define NV_PFB_ARB_TIMEOUT_ZO 11:8 /* RWIUF */
|
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#define NV_PFB_ARB_TIMEOUT_ZO_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_ZO_DISABLE 0x0000000F /* RWIUV */
|
|
#define NV_PFB_ARB_TIMEOUT_TX 15:12 /* RWIUF */
|
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#define NV_PFB_ARB_TIMEOUT_TX_3 0x00000003 /* RWIUV */
|
|
#define NV_PFB_ARB_TIMEOUT_TX_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_TX_12 0x0000000C /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_TX_DISABLE 0x0000000F /* RW-UV */
|
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#define NV_PFB_ARB_TIMEOUT_ZR 19:16 /* RWIUF */
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|
#define NV_PFB_ARB_TIMEOUT_ZR_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_ZR_DISABLE 0x0000000F /* RWIUV */
|
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#define NV_PFB_ARB_TIMEOUT_ZW 23:20 /* RWIUF */
|
|
#define NV_PFB_ARB_TIMEOUT_ZW_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_ZW_DISABLE 0x0000000F /* RWIUV */
|
|
#define NV_PFB_ARB_TIMEOUT_CR 27:24 /* RWIUF */
|
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#define NV_PFB_ARB_TIMEOUT_CR_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_CR_DISABLE 0x0000000F /* RWIUV */
|
|
#define NV_PFB_ARB_TIMEOUT_CW 31:28 /* RWIUF */
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|
#define NV_PFB_ARB_TIMEOUT_CW_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_TIMEOUT_CW_DISABLE 0x0000000F /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ 0x00100330 /* RW-4R */
|
|
#define NV_PFB_ARB_XFER_SZ_EXT 3:0 /* RWIUF */
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|
#define NV_PFB_ARB_XFER_SZ_EXT_4 0x00000002 /* RW-UV */
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|
#define NV_PFB_ARB_XFER_SZ_EXT_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_EXT_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_EXT_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_LP 7:4 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_LP_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_LP_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_LP_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZO 11:8 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_ZO_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZO_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZO_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_TX 15:12 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_TX_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_TX_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_TX_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZR 19:16 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_ZR_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZR_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZR_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZW 23:20 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_ZW_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZW_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_ZW_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_CR 27:24 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_CR_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_CR_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_CR_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_CW 31:28 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_SZ_CW_8 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_SZ_CW_MIN 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_SZ_CW_INF 0x0000000F /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM 0x00100334 /* RW-4R */
|
|
#define NV_PFB_ARB_XFER_REM_EXT 3:0 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_EXT_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_EXT_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_EXT_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_LP 7:4 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_LP_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_LP_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_LP_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_ZO 11:8 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_ZO_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_ZO_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_ZO_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_TX 15:12 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_TX_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_TX_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_TX_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_ZR 19:16 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_ZR_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_ZR_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_ZR_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_ZW 23:20 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_ZW_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_ZW_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_ZW_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_CR 27:24 /* RWIUF */
|
|
#define NV_PFB_ARB_XFER_REM_CR_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_CR_4 0x00000004 /* RWIUV */
|
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#define NV_PFB_ARB_XFER_REM_CR_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_ARB_XFER_REM_CW 31:28 /* RWIUF */
|
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#define NV_PFB_ARB_XFER_REM_CW_0 0x00000000 /* RW-UV */
|
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#define NV_PFB_ARB_XFER_REM_CW_4 0x00000004 /* RWIUV */
|
|
#define NV_PFB_ARB_XFER_REM_CW_8 0x00000008 /* RW-UV */
|
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#define NV_PFB_ARB_DIFF_BANK 0x00100338 /* RW-4R */
|
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#define NV_PFB_ARB_DIFF_BANK_EXT 0:0 /* RWIUF */
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#define NV_PFB_ARB_DIFF_BANK_EXT_DISABLED 0x00000000 /* RW-UV */
|
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#define NV_PFB_ARB_DIFF_BANK_EXT_ENABLED 0x00000001 /* RWIUV */
|
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#define NV_PFB_ARB_DIFF_BANK_LP 1:1 /* RWIUF */
|
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#define NV_PFB_ARB_DIFF_BANK_LP_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_DIFF_BANK_LP_ENABLED 0x00000001 /* RWIUV */
|
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#define NV_PFB_ARB_DIFF_BANK_ZO 2:2 /* RWIUF */
|
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#define NV_PFB_ARB_DIFF_BANK_ZO_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_DIFF_BANK_ZO_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_ARB_DIFF_BANK_TX 3:3 /* RWIUF */
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#define NV_PFB_ARB_DIFF_BANK_TX_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_DIFF_BANK_TX_ENABLED 0x00000001 /* RWIUV */
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#define NV_PFB_ARB_DIFF_BANK_ZR 4:4 /* RWIUF */
|
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#define NV_PFB_ARB_DIFF_BANK_ZR_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_ARB_DIFF_BANK_ZR_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_ARB_DIFF_BANK_ZW 5:5 /* RWIUF */
|
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#define NV_PFB_ARB_DIFF_BANK_ZW_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_ARB_DIFF_BANK_ZW_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_ARB_DIFF_BANK_CR 6:6 /* RWIUF */
|
|
#define NV_PFB_ARB_DIFF_BANK_CR_DISABLED 0x00000000 /* RW-UV */
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|
#define NV_PFB_ARB_DIFF_BANK_CR_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_ARB_DIFF_BANK_CW 7:7 /* RWIUF */
|
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#define NV_PFB_ARB_DIFF_BANK_CW_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_ARB_DIFF_BANK_CW_ENABLED 0x00000001 /* RWIUV */
|
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#define NV_PFB_CLOSE_PAGE0 0x00100340 /* RW-4R */
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#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_EXT 0:0 /* RWIUF */
|
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#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_EXT_DISABLED 0x00000000 /* RW-UV */
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|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_EXT_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_LP 1:1 /* RWIUF */
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|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_LP_DISABLED 0x00000000 /* RW-UV */
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|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_LP_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZO 2:2 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZO_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZO_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_TX 3:3 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_TX_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_TX_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZR 4:4 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZR_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZR_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZW 5:5 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZW_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_ZW_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CR 6:6 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CR_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CR_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CW 7:7 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CW_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CW_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_HP 8:8 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_HP_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_HP_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CPU 9:9 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CPU_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_CPU_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_LDT 10:10 /* RWIUF */
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|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_LDT_DISABLED 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE0_DIFF_ROW_LDT_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1 0x00100344 /* RW-4R */
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|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_EXT 0:0 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_EXT_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_EXT_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_LP 1:1 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_LP_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_LP_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZO 2:2 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZO_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZO_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_TX 3:3 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_TX_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_TX_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZR 4:4 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZR_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZR_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZW 5:5 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZW_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_ZW_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CR 6:6 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CR_DISABLED 0x00000000 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CR_ENABLED 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CW 7:7 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CW_DISABLED 0x00000000 /* RWIUV */
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|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CW_ENABLED 0x00000001 /* RW-UV */
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|
#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_HP 8:8 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_HP_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_HP_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CPU 9:9 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CPU_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_CPU_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_LDT 10:10 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_LDT_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE1_DIFF_BANK_LDT_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2 0x00100348 /* RW-4R */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_EXT 0:0 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_EXT_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_EXT_ENABLED 0x00000001 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_LP 1:1 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_LP_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_LP_ENABLED 0x00000001 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZO 2:2 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZO_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZO_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_TX 3:3 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_TX_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_TX_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZR 4:4 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZR_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZR_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZW 5:5 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZW_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_ZW_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CR 6:6 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CR_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CR_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CW 7:7 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CW_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CW_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_HP 8:8 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_HP_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_HP_ENABLED 0x00000001 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CPU 9:9 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CPU_DISABLED 0x00000000 /* RWIUV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_CPU_ENABLED 0x00000001 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_LDT 10:10 /* RWIUF */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_LDT_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_Q_EMPTY_LDT_ENABLED 0x00000001 /* RWIUV */
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|
#define NV_PFB_CLOSE_PAGE2_ALWAYS_GART 11:11 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE2_ALWAYS_GART_DISABLED 0x00000000 /* RW-UV */
|
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#define NV_PFB_CLOSE_PAGE2_ALWAYS_GART_ENABLED 0x00000001 /* RWIUV */
|
|
#define NV_PFB_CLOSE_PAGE2_ALWAYS_WBC_LP 12:12 /* RWIUF */
|
|
#define NV_PFB_CLOSE_PAGE2_ALWAYS_WBC_LP_DISABLED 0x00000000 /* RW-UV */
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#define NV_PFB_CLOSE_PAGE2_ALWAYS_WBC_LP_ENABLED 0x00000001 /* RWIUV */
|
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#define NV_PFB_CLOSE_PAGE2_ALWAYS_WBC_HP 13:13 /* RWIUF */
|
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#define NV_PFB_CLOSE_PAGE2_ALWAYS_WBC_HP_DISABLED 0x00000000 /* RWIUV */
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|
#define NV_PFB_CLOSE_PAGE2_ALWAYS_WBC_HP_ENABLED 0x00000001 /* RW-UV */
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|
#define NV_PFB_BPARB 0x0010034C /* RW-4R */
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#define NV_PFB_BPARB_HP_ARB_MODE 2:0 /* RWIUF */
|
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#define NV_PFB_BPARB_HP_ARB_MODE_REL_WTRMRK_10 0x00000000 /* RWIUV */
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#define NV_PFB_BPARB_HP_ARB_MODE_REL_WTRMRK_8 0x00000001 /* RW-UV */
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|
#define NV_PFB_BPARB_HP_ARB_MODE_REL_WTRMRK_6 0x00000002 /* RW-UV */
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|
#define NV_PFB_BPARB_HP_ARB_MODE_REL_WTRMRK_4 0x00000003 /* RW-UV */
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#define NV_PFB_BPARB_HP_ARB_MODE_KEEP_NEVER 0x00000004 /* RW-UV */
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#define NV_PFB_CMDQ0 0x00100350 /* RW-4R */
|
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#define NV_PFB_CMDQ0_FA_RW 4:0 /* RWIUF */
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#define NV_PFB_CMDQ0_FA_RW_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_RW_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_RW_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_RW_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_RW_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_RW_16 0x00000010 /* RWIUV */
|
|
#define NV_PFB_CMDQ0_FA_ACT 11:8 /* RWIUF */
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|
#define NV_PFB_CMDQ0_FA_ACT_1 0x00000001 /* RW-UV */
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|
#define NV_PFB_CMDQ0_FA_ACT_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_ACT_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_ACT_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_ACT_8 0x00000008 /* RWIUV */
|
|
#define NV_PFB_CMDQ0_FA_PRE 15:12 /* RWIUF */
|
|
#define NV_PFB_CMDQ0_FA_PRE_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_PRE_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_PRE_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_PRE_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_FA_PRE_8 0x00000008 /* RWIUV */
|
|
#define NV_PFB_CMDQ0_HP_RW 20:16 /* RWIUF */
|
|
#define NV_PFB_CMDQ0_HP_RW_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_RW_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_RW_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_RW_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_RW_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_RW_16 0x00000010 /* RWIUV */
|
|
#define NV_PFB_CMDQ0_HP_ACT 27:24 /* RWIUF */
|
|
#define NV_PFB_CMDQ0_HP_ACT_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_ACT_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_ACT_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_ACT_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_ACT_8 0x00000008 /* RWIUV */
|
|
#define NV_PFB_CMDQ0_HP_PRE 31:28 /* RWIUF */
|
|
#define NV_PFB_CMDQ0_HP_PRE_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_PRE_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_PRE_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_PRE_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ0_HP_PRE_8 0x00000008 /* RWIUV */
|
|
#define NV_PFB_CMDQ1 0x00100354 /* RW-4R */
|
|
#define NV_PFB_CMDQ1_RT_RW 4:0 /* RWIUF */
|
|
#define NV_PFB_CMDQ1_RT_RW_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_RW_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_RW_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_RW_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_RW_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_RW_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_RW_10 0x0000000A /* RWIUV */
|
|
#define NV_PFB_CMDQ1_RT_RW_16 0x00000010 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_ACT 11:8 /* RWIUF */
|
|
#define NV_PFB_CMDQ1_RT_ACT_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_ACT_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_ACT_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_ACT_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_ACT_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_ACT_8 0x00000008 /* RWIUV */
|
|
#define NV_PFB_CMDQ1_RT_PRE 15:12 /* RWIUF */
|
|
#define NV_PFB_CMDQ1_RT_PRE_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_PRE_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_PRE_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_PRE_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_PRE_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_CMDQ1_RT_PRE_8 0x00000008 /* RWIUV */
|
|
#define NV_PFB_ILL_INSTR(i) (0x00100360+(i)*4) /* R--4A */
|
|
#define NV_PFB_ILL_INSTR__SIZE_1 4 /* */
|
|
#define NV_PFB_ILL_INSTR_REQID 4:0 /* R--VF */
|
|
#define NV_PFB_ILL_INSTR_CMD 26:5 /* R--VF */
|
|
#define NV_PFB_ILL_INSTR_CODE 30:27 /* R--VF */
|
|
#define NV_PFB_ILL_INSTR_TRAPPED 31:31 /* R--VF */
|
|
#define NV_PFB_RT 0x00100400 /* RW-4R */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP 2:0 /* RWIUF */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_2 0x00000002 /* RW-UV */
|
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#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_3 0x00000003 /* RWIUV */
|
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#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_RT_CPU_GNT_BLOCKS_LP_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_AUTOCLOSE 0x00100404 /* RW-4R */
|
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#define NV_PFB_AUTOCLOSE_ACTIVE 0:0 /* RWIVF */
|
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#define NV_PFB_AUTOCLOSE_ACTIVE_FALSE 0x00000000 /* RW--V */
|
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#define NV_PFB_AUTOCLOSE_ACTIVE_TRUE 0x00000001 /* RWI-V */
|
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#define NV_PFB_AUTOCLOSE_RT 4:4 /* RWIVF */
|
|
#define NV_PFB_AUTOCLOSE_RT_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PFB_AUTOCLOSE_RT_ENABLED 0x00000001 /* RWI-V */
|
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#define NV_PFB_AUTOCLOSE_HP 5:5 /* RWIVF */
|
|
#define NV_PFB_AUTOCLOSE_HP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_AUTOCLOSE_HP_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PFB_AUTOCLOSE_FA 6:6 /* RWIVF */
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#define NV_PFB_AUTOCLOSE_FA_DISABLED 0x00000000 /* RWI-V */
|
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#define NV_PFB_AUTOCLOSE_FA_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PFB_AUTOCLOSE_TIMEOUT 12:8 /* RWIUF */
|
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#define NV_PFB_AUTOCLOSE_TIMEOUT_MIN 0x00000000 /* RW-UV */
|
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#define NV_PFB_AUTOCLOSE_TIMEOUT_15 0x0000000F /* RWIUV */
|
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#define NV_PFB_AUTOCLOSE_TIMEOUT_MAX 0x0000001F /* RW-UV */
|
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#define NV_PFB_AUTOCLOSE_DRAMC_DEBUG 31:16 /* RWIVF */
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#define NV_PFB_AUTOCLOSE_DRAMC_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PFB_WBC 0x00100410 /* RW-4R */
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#define NV_PFB_WBC_HWM 4:0 /* RWIUF */
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#define NV_PFB_WBC_HWM_0 0x00000000 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_1 0x00000001 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_2 0x00000002 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_3 0x00000003 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_4 0x00000004 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_5 0x00000005 /* RW-UV */
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#define NV_PFB_WBC_HWM_6 0x00000006 /* RW-UV */
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#define NV_PFB_WBC_HWM_7 0x00000007 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_8 0x00000008 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_9 0x00000009 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_10 0x0000000A /* RW-UV */
|
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#define NV_PFB_WBC_HWM_11 0x0000000B /* RW-UV */
|
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#define NV_PFB_WBC_HWM_12 0x0000000C /* RW-UV */
|
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#define NV_PFB_WBC_HWM_13 0x0000000D /* RW-UV */
|
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#define NV_PFB_WBC_HWM_14 0x0000000E /* RW-UV */
|
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#define NV_PFB_WBC_HWM_15 0x0000000F /* RW-UV */
|
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#define NV_PFB_WBC_HWM_16 0x00000010 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_17 0x00000011 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_18 0x00000012 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_19 0x00000013 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_20 0x00000014 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_21 0x00000015 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_22 0x00000016 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_23 0x00000017 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_24 0x00000018 /* RWIUV */
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#define NV_PFB_WBC_HWM_25 0x00000019 /* RW-UV */
|
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#define NV_PFB_WBC_HWM_26 0x0000001A /* RW-UV */
|
|
#define NV_PFB_WBC_HWM_27 0x0000001B /* RW-UV */
|
|
#define NV_PFB_WBC_HWM_28 0x0000001C /* RW-UV */
|
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#define NV_PFB_WBC_HWM_29 0x0000001D /* RW-UV */
|
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#define NV_PFB_WBC_HWM_30 0x0000001E /* RW-UV */
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#define NV_PFB_WBC_HWM_31 0x0000001F /* RW-UV */
|
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#define NV_PFB_WBC_LWM 12:8 /* RWIUF */
|
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#define NV_PFB_WBC_LWM_0 0x00000000 /* RW-UV */
|
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#define NV_PFB_WBC_LWM_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_2 0x00000002 /* RW-UV */
|
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#define NV_PFB_WBC_LWM_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_9 0x00000009 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_10 0x0000000A /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_11 0x0000000B /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_12 0x0000000C /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_13 0x0000000D /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_14 0x0000000E /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_15 0x0000000F /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_16 0x00000010 /* RWIUV */
|
|
#define NV_PFB_WBC_LWM_17 0x00000011 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_18 0x00000012 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_19 0x00000013 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_20 0x00000014 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_21 0x00000015 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_22 0x00000016 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_23 0x00000017 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_24 0x00000018 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_25 0x00000019 /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_26 0x0000001A /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_27 0x0000001B /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_28 0x0000001C /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_29 0x0000001D /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_30 0x0000001E /* RW-UV */
|
|
#define NV_PFB_WBC_LWM_31 0x0000001F /* RW-UV */
|
|
#define NV_PFB_WBC_FLUSH 16:16 /* RWIVF */
|
|
#define NV_PFB_WBC_FLUSH_NOT_PENDING 0x00000000 /* RWI-V */
|
|
#define NV_PFB_WBC_FLUSH_PENDING 0x00000001 /* -W--T */
|
|
#define NV_PFB_WBC_FULL_BLOCKS_ISOLDT_READ 20:20 /* RWIVF */
|
|
#define NV_PFB_WBC_FULL_BLOCKS_ISOLDT_READ_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PFB_WBC_FULL_BLOCKS_ISOLDT_READ_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PFB_WBC_FULL_BLOCKS_NONISOLDT_READ 21:21 /* RWIVF */
|
|
#define NV_PFB_WBC_FULL_BLOCKS_NONISOLDT_READ_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PFB_WBC_FULL_BLOCKS_NONISOLDT_READ_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PFB_WBC_ATOMIC_CPU_READS 24:24 /* RWIVF */
|
|
#define NV_PFB_WBC_ATOMIC_CPU_READS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PFB_WBC_ATOMIC_CPU_READS_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PFB_WBC_ATOMIC_AGP_READS 25:25 /* RWIVF */
|
|
#define NV_PFB_WBC_ATOMIC_AGP_READS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_WBC_ATOMIC_AGP_READS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_WBC_ATOMIC_LDT_READS 26:26 /* RWIVF */
|
|
#define NV_PFB_WBC_ATOMIC_LDT_READS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_WBC_ATOMIC_LDT_READS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_WBC_32B_WRITE_BLOCKS_READS 28:28 /* RWIVF */
|
|
#define NV_PFB_WBC_32B_WRITE_BLOCKS_READS_DISABLED 0x00000000 /* RW--V */
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|
#define NV_PFB_WBC_32B_WRITE_BLOCKS_READS_ENABLED 0x00000001 /* RWI-V */
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#define NV_PFB_CMDQ_PRT 0x00100418 /* RW-4R */
|
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#define NV_PFB_CMDQ_PRT_DISABLE 0:0 /* RWIVF */
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#define NV_PFB_CMDQ_PRT_DISABLE_OFF 0x00000000 /* RWI-V */
|
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#define NV_PFB_CMDQ_PRT_DISABLE_ON 0x00000001 /* RW--V */
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#define NV_PFB_CMDQ_PRT_HP_MIN 5:2 /* RWIUF */
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#define NV_PFB_CMDQ_PRT_HP_MIN_0 0x00000000 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_1 0x00000001 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_2 0x00000002 /* RWIUV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_3 0x00000003 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_4 0x00000004 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_5 0x00000005 /* RW-UV */
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|
#define NV_PFB_CMDQ_PRT_HP_MIN_6 0x00000006 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_7 0x00000007 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_8 0x00000008 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_9 0x00000009 /* RW-UV */
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#define NV_PFB_CMDQ_PRT_HP_MIN_10 0x0000000a /* RW-UV */
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|
#define NV_PFB_CMDQ_PRT_HP_MIN_11 0x0000000b /* RW-UV */
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|
#define NV_PFB_CMDQ_PRT_HP_MIN_12 0x0000000c /* RW-UV */
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|
#define NV_PFB_CMDQ_PRT_HP_MIN_13 0x0000000d /* RW-UV */
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|
#define NV_PFB_CMDQ_PRT_HP_MIN_14 0x0000000e /* RW-UV */
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|
#define NV_PFB_CMDQ_PRT_HP_MIN_15 0x0000000f /* RW-UV */
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#define NV_PFB_CMDQ_PRT_RT_MIN 14:11 /* RWIUF */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_2 0x00000002 /* RWIUV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_9 0x00000009 /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_10 0x0000000a /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_11 0x0000000b /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_12 0x0000000c /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_13 0x0000000d /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_14 0x0000000e /* RW-UV */
|
|
#define NV_PFB_CMDQ_PRT_RT_MIN_15 0x0000000f /* RW-UV */
|
|
#define NV_PFB_CPU_RRQ 0x00100420 /* RW-4R */
|
|
#define NV_PFB_CPU_RRQ_BYPASS 0:0 /* RWIVF */
|
|
#define NV_PFB_CPU_RRQ_BYPASS_DISABLED 0x00000000 /* R-I-V */
|
|
#define NV_PFB_CPU_RRQ_BYPASS_ENABLED 0x00000001 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY 7:4 /* RWIUF */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_MIN 0x00000000 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_0 0x00000000 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_1 0x00000001 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_2 0x00000002 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_3 0x00000003 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_4 0x00000004 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_5 0x00000005 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_6 0x00000006 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_LATENCY_MAX 0x00000006 /* R-I-V */
|
|
#define NV_PFB_CPU_RRQ_FWP 11:8 /* RWIUF */
|
|
#define NV_PFB_CPU_RRQ_FWP_MIN 0x00000003 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_FWP_3 0x00000003 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_FWP_4 0x00000004 /* R---V */
|
|
#define NV_PFB_CPU_RRQ_FWP_MAX 0x00000004 /* R-I-V */
|
|
#define NV_PFB_BYPASS 0x00100424 /* RW-4R */
|
|
#define NV_PFB_BYPASS_FAST_READ 0:0 /* RWIVF */
|
|
#define NV_PFB_BYPASS_FAST_READ_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_BYPASS_FAST_READ_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_BYPASS_SINGLE_CYCLE 4:4 /* RWIVF */
|
|
#define NV_PFB_BYPASS_SINGLE_CYCLE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_BYPASS_SINGLE_CYCLE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_BYPASS_BLOCK_WBC_AUTOPRE 5:5 /* RWIVF */
|
|
#define NV_PFB_BYPASS_BLOCK_WBC_AUTOPRE_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PFB_BYPASS_BLOCK_WBC_AUTOPRE_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PFB_BYPASS_ALLOW_CPUREAD_DURING_BYPASS 8:8 /* RWIVF */
|
|
#define NV_PFB_BYPASS_ALLOW_CPUREAD_DURING_BYPASS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PFB_BYPASS_ALLOW_CPUREAD_DURING_BYPASS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PFB_BYPASS_DEBUG 15:9 /* RWIVF */
|
|
#define NV_PFB_BYPASS_DEBUG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY 19:16 /* RWIUF */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_5 0x00000005 /* RWIUV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_8 0x00000008 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_9 0x00000009 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_10 0x0000000a /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_CPU_LATENCY_11 0x0000000b /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY 22:20 /* RWIUF */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_BYPASS_MAX_MEM_LATENCY_7 0x00000007 /* RWIUV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED 26:24 /* RWIUF */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_2 0x00000002 /* RWIUV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_4 0x00000004 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_5 0x00000005 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_6 0x00000006 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RR_SLOTS_NEEDED_7 0x00000007 /* RW-UV */
|
|
#define NV_PFB_BYPASS_ROW_EARLY_NONSPEC 28:28 /* RWIVF */
|
|
#define NV_PFB_BYPASS_ROW_EARLY_NONSPEC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_BYPASS_ROW_EARLY_NONSPEC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_BYPASS_ROW_EARLY_SPEC 29:29 /* RWIVF */
|
|
#define NV_PFB_BYPASS_ROW_EARLY_SPEC_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PFB_BYPASS_ROW_EARLY_SPEC_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY 31:30 /* RWIUF */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY_MIN 0x00000000 /* RWIUV */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY_0 0x00000000 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY_1 0x00000001 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY_2 0x00000002 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY_3 0x00000003 /* RW-UV */
|
|
#define NV_PFB_BYPASS_RETIRE_DELAY_MAX 0x00000003 /* RW-UV */
|
|
/* dev_fb.ref */
|
|
#define NV_PFBM 0x3FFFFFFF:0x08000000 /* RW--M */
|
|
/* dev_fb.ref */
|
|
#define NV_PFBIN 0x007FFFFF:0x00700000 /* RW--M */
|
|
/* dev_ext_devices.ref */
|
|
#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */
|
|
#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_AD 0:0 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_AD_NORMAL 0x00000001 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_AD_REVERSED 0x00000000 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_RAMCFG 5:2 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_RAMCFG_0 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_4X 9:9 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_4X_ENABLED 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_4X_DISABLED 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_SBA 10:10 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_SBA_DISABLED 0x00000001 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_SBA_ENABLED 0x00000000 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_FASTWR 11:11 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_FASTWR_ENABLED 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_AGP_FASTWR_DISABLED 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_DEVID 13:12 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_DEVID_0 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_DEVID_1 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_DEVID_2 0x00000002 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_PCI_DEVID_3 0x00000003 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 14:14 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE 15:15 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_24BIT 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB 17:16 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_64M 0x00000000 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_128M 0x00000001 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_256M 0x00000002 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_512M 0x00000003 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_EMRS 19:18 /* RWXVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_EMRS_MICRON 0x00000000 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_EMRS_REDUCED_DRIVE 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_EMRS_RESERVED 0x00000002 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_EMRS_MATCHED 0x00000003 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_CPU 23:20 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_LDT_BIAS_EN 24:24 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_USER 28:25 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 31:31 /* RWIVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */
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#define NV_PEXTDEV_NEW_BOOT_0 0x00101000 /* RW-4R */
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#define NV_PEXTDEV_NEW_BOOT_0_STRAP_VALUE 30:0 /* RWIVF */
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#define NV_PEXTDEV_NEW_BOOT_0_STRAP_OVERWRITE 31:31 /* RWIVF */
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#define NV_PEXTDEV_NEW_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PEXTDEV_NEW_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB 17:16 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_64M 0x00000000 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_128M 0x00000001 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_256M 0x00000002 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_FB_512M 0x00000003 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR 18:18 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_DISABLED 0x00000000 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_ENABLED 0x00000001 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_REG_128M 19:19 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_REG_128M_ENABLED 0x00000000 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_REG_128M_DISABLED 0x00000001 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_AGP_DEV 20:20 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_AGP_DEV_DISABLED 0x00000000 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_AGP_DEV_ENABLED 0x00000001 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_IO_DEV 21:21 /* R-XVF */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_IO_DEV_DISABLED 0x00000000 /* R---V */
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#define NV_PEXTDEV_BOOT_0_STRAP_BR_IO_DEV_ENABLED 0x00000001 /* R---V */
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/* dev_ext_devices.ref */
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#define NV_PDAC 0x00680FFF:0x00680000 /* RW--D */
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#define NV_PDAC_DATA(i) (0x00680000+(i)*4) /* RW-4A */
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#define NV_PDAC_DATA__SIZE_1 16 /* */
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#define NV_PDAC_DATA_VALUE 7:0 /* RW-VF */
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/* dev_ext_devices.ref */
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/* dev_ext_devices.ref */
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#define NV_PROM 0x0030FFFF:0x00300000 /* RW--D */
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#define NV_PROM_DATA(i) (0x00300000+(i)) /* RW-1A */
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#define NV_PROM_DATA__SIZE_1 65536 /* */
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#define NV_PROM_DATA_VALUE 7:0 /* RW-VF */
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/* dev_fifo.ref */
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#define NV_USER 0x00BFFFFF:0x00800000 /* RW--D */
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#define NV_USER_OBJECT(i,j) (0x00800000+(i)*0x10000+(j)*0x2000) /* -W-4A */
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|
#define NV_USER_OBJECT__SIZE_1 32 /* */
|
|
#define NV_USER_OBJECT__SIZE_2 8 /* */
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|
#define NV_USER_OBJECT_HANDLE 31:0 /* -W-VF */
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#define NV_USER_FREE016(i,j) (0x00800010+(i)*65536+(j)*8192) /* R--2A */
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|
#define NV_USER_FREE016__SIZE_1 32 /* */
|
|
#define NV_USER_FREE016__SIZE_2 8 /* */
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|
#define NV_USER_FREE016_COUNT_LO 1:0 /* C--UF */
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|
#define NV_USER_FREE016_COUNT_LO_0 0x00000000 /* C---V */
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#define NV_USER_FREE016_COUNT 9:2 /* R--UF */
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#define NV_USER_FREE016_COUNT_HI 15:10 /* C--UF */
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#define NV_USER_FREE016_COUNT_HI_0 0x00000000 /* C---V */
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#define NV_USER_FREE032(i,j) (0x00800010+(i)*65536+(j)*8192) /* R--4A */
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#define NV_USER_FREE032__SIZE_1 32 /* */
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#define NV_USER_FREE032__SIZE_2 8 /* */
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#define NV_USER_FREE032_COUNT_LO 1:0 /* C--UF */
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#define NV_USER_FREE032_COUNT_LO_0 0x00000000 /* C---V */
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#define NV_USER_FREE032_COUNT 9:2 /* R--UF */
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#define NV_USER_FREE032_COUNT_HI 31:10 /* C--UF */
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#define NV_USER_FREE032_COUNT_HI_0 0x00000000 /* C---V */
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#define NV_USER_ZERO016(i,j,k) (0x0800012+(i)*65536+(j)*8192+(k)*2) /* R--2A */
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#define NV_USER_ZERO016__SIZE_1 32 /* */
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#define NV_USER_ZERO016__SIZE_2 8 /* */
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#define NV_USER_ZERO016__SIZE_3 7 /* */
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#define NV_USER_ZERO016_COUNT 15:0 /* C--UF */
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#define NV_USER_ZERO016_COUNT_0 0x00000000 /* C---V */
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#define NV_USER_ZERO032(i,j,k) (0x0800014+(i)*65536+(j)*8192+(k)*4) /* R--4A */
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#define NV_USER_ZERO032__SIZE_1 32 /* */
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#define NV_USER_ZERO032__SIZE_2 8 /* */
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#define NV_USER_ZERO032__SIZE_3 3 /* */
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#define NV_USER_ZERO032_COUNT 31:0 /* C--UF */
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#define NV_USER_ZERO032_COUNT_0 0x00000000 /* C---V */
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#define NV_USER_DMA_PUT(i,j) (0x00800040+(i)*0x10000+(j)*0x2000) /* -W-4A */
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#define NV_USER_DMA_PUT__SIZE_1 32 /* */
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#define NV_USER_DMA_PUT__SIZE_2 8 /* */
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#define NV_USER_DMA_PUT_OFFSET 31:2 /* -WXUF */
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#define NV_USER_DMA_GET(i,j) (0x00800044+(i)*0x10000+(j)*0x2000) /* R--4A */
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#define NV_USER_DMA_GET__SIZE_1 32 /* */
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#define NV_USER_DMA_GET__SIZE_2 8 /* */
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#define NV_USER_DMA_GET_OFFSET 31:2 /* R-XUF */
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#define NV_USER_REF(i,j) (0x00800048+(i)*0x10000+(j)*0x2000) /* R--4A */
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#define NV_USER_REF__SIZE_1 32 /* */
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#define NV_USER_REF__SIZE_2 8 /* */
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#define NV_USER_REF_CNT 31:0 /* R-XUF */
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/* dev_fifo.ref */
|
|
#define NV_UDMA_OBJECT(j) (0x00000000+(j)*0x2000) /* -W-4A */
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#define NV_UDMA_OBJECT__SIZE_1 32 /* */
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#define NV_UDMA_OBJECT__SIZE_2 8 /* */
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#define NV_UDMA_OBJECT_HANDLE 31:0 /* -W-VF */
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#define NV_UDMA_SET_REF(j) (0x00000050+(j)*0x2000) /* R--4A */
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#define NV_UDMA_SET_REF__SIZE_1 32 /* */
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#define NV_UDMA_SET_REF__SIZE_2 8 /* */
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#define NV_UDMA_SET_REF_CNT 31:0 /* R-XUF */
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#define NV_UDMA_SEM_CTXDMA(j) (0x00000060+(j)*0x2000) /* -W-4A */
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|
#define NV_UDMA_SEM_CTXDMA__SIZE_1 32 /* */
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|
#define NV_UDMA_SEM_CTXDMA__SIZE_2 8 /* */
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#define NV_UDMA_SEM_CTXDMA_HANDLE 31:0 /* -W-VF */
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#define NV_UDMA_SEM_OFFSET(j) (0x00000064+(j)*0x2000) /* -W-4A */
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#define NV_UDMA_SEM_OFFSET__SIZE_1 32 /* */
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#define NV_UDMA_SEM_OFFSET__SIZE_2 8 /* */
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|
#define NV_UDMA_SEM_OFFSET_ADDRESS 11:2 /* -W-VF */
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#define NV_UDMA_SEM_ACQUIRE(j) (0x00000068+(j)*0x2000) /* -W-4A */
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#define NV_UDMA_SEM_ACQUIRE__SIZE_1 32 /* */
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|
#define NV_UDMA_SEM_ACQUIRE__SIZE_2 8 /* */
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#define NV_UDMA_SEM_ACQUIRE_VALUE 31:0 /* -W-VF */
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#define NV_UDMA_SEM_RELEASE(j) (0x0000006C+(j)*0x2000) /* -W-4A */
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#define NV_UDMA_SEM_RELEASE__SIZE_1 32 /* */
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#define NV_UDMA_SEM_RELEASE__SIZE_2 8 /* */
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#define NV_UDMA_SEM_RELEASE_VALUE 31:0 /* -W-VF */
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/* dev_misc.ref */
|
|
#define NV_USER_ADR_CHID 22:16 /* */
|
|
#define NV_USER_ADR_SUBCHID 15:13 /* */
|
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#define NV_USER_ADR_METHOD 12:0 /* */
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#define NV_USER_DEVICE 22:16 /* */
|
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/* dev_timer.ref */
|
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#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */
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#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */
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#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */
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#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */
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|
#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */
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|
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */
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|
#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */
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#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */
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|
#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */
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#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */
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|
#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */
|
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#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */
|
|
#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */
|
|
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
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#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
|
|
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
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#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
|
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#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
|
|
#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */
|
|
/* dev_ram.ref */
|
|
#define NV_RAMHT__SIZE_0 0x00000FFF:0x00000000 /* RW--M */
|
|
#define NV_RAMHT__SIZE_1 0x00001FFF:0x00000000 /* RW--M */
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|
#define NV_RAMHT__SIZE_2 0x00003FFF:0x00000000 /* RW--M */
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|
#define NV_RAMHT__SIZE_3 0x00007FFF:0x00000000 /* RW--M */
|
|
#define NV_RAMHT_HANDLE ( 0*32+31):( 0*32+ 0) /* RWXVF */
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|
#define NV_RAMHT_INSTANCE ( 1*32+15):( 1*32+ 0) /* RWXUF */
|
|
#define NV_RAMHT_ENGINE ( 1*32+17):( 1*32+16) /* RWXVF */
|
|
#define NV_RAMHT_ENGINE_SW 0x00000000 /* RW--V */
|
|
#define NV_RAMHT_ENGINE_GRAPHICS 0x00000001 /* RW--V */
|
|
#define NV_RAMHT_ENGINE_DVD 0x00000002 /* RW--V */
|
|
#define NV_RAMHT_CHID ( 1*32+28):( 1*32+24) /* RWXUF */
|
|
#define NV_RAMHT_STATUS ( 1*32+31):( 1*32+31) /* RWXUF */
|
|
#define NV_RAMHT_STATUS_INVALID 0x00000000 /* RW--V */
|
|
#define NV_RAMHT_STATUS_VALID 0x00000001 /* RW--V */
|
|
/* dev_ram.ref */
|
|
#define NV_RAMRO__SIZE_0 0x000001FF:0x00000000 /* RW--M */
|
|
#define NV_RAMRO__SIZE_1 0x00001FFF:0x00000000 /* RW--M */
|
|
#define NV_RAMRO_METHOD ( 0*32+12):( 0*32+ 0) /* RWXUF */
|
|
#define NV_RAMRO_SUBCHANNEL ( 0*32+15):( 0*32+13) /* RWXUF */
|
|
#define NV_RAMRO_CHID ( 0*32+22):( 0*32+16) /* RWXUF */
|
|
#define NV_RAMRO_TYPE ( 0*32+23):( 0*32+23) /* RWXVF */
|
|
#define NV_RAMRO_TYPE_WRITE 0x00000000 /* RW--V */
|
|
#define NV_RAMRO_TYPE_READ 0x00000001 /* RW--V */
|
|
#define NV_RAMRO_BYTE_ENABLES ( 0*32+27):( 0*32+24) /* RWXUF */
|
|
#define NV_RAMRO_REASON ( 0*32+31):( 0*32+28) /* RWXVF */
|
|
#define NV_RAMRO_REASON_ILLEGAL_ACCESS 0x00000000 /* RW--V */
|
|
#define NV_RAMRO_REASON_NO_CACHE_AVAILABLE 0x00000001 /* RW--V */
|
|
#define NV_RAMRO_REASON_CACHE_RAN_OUT 0x00000002 /* RW--V */
|
|
#define NV_RAMRO_REASON_FREE_COUNT_OVERRUN 0x00000003 /* RW--V */
|
|
#define NV_RAMRO_REASON_CAUGHT_LYING 0x00000004 /* RW--V */
|
|
#define NV_RAMRO_REASON_RESERVED_ACCESS 0x00000005 /* RW--V */
|
|
#define NV_RAMRO_DATA ( 1*32+31):( 1*32+ 0) /* RWXUF */
|
|
/* dev_ram.ref */
|
|
#define NV_RAMFC__SIZE_0 0x000003FF:0x00000000 /* RW--M */
|
|
#define NV_RAMFC__SIZE_1 0x000007FF:0x00000000 /* RW--M */
|
|
#define NV_RAMFC_DMA_PUT ( 0*32+31):( 0*32+ 2) /* RWXUF */
|
|
#define NV_RAMFC_DMA_GET ( 1*32+31):( 1*32+ 2) /* RWXUF */
|
|
#define NV_RAMFC_REF_CNT ( 2*32+31):( 2*32+ 0) /* RWXUF */
|
|
#define NV_RAMFC_DMA_INST ( 3*32+15):( 3*32+ 0) /* RWXUF */
|
|
#define NV_RAMFC_DMA_COUNT ( 3*32+28):( 3*32+18) /* RWXUF */
|
|
#define NV_RAMFC_DMA_METHOD ( 4*32+12):( 4*32+ 2) /* RWXUF */
|
|
#define NV_RAMFC_DMA_SUBCHANNEL ( 4*32+15):( 4*32+13) /* RWXUF */
|
|
#define NV_RAMFC_DMA_METHOD_COUNT ( 4*32+28):( 4*32+18) /* RWXUF */
|
|
#define NV_RAMFC_DMA_METHOD_TYPE ( 4*32+ 0):( 4*32+ 0) /* RWXUF */
|
|
#define NV_RAMFC_DMA_FETCH_TRIG ( 5*32+ 7):( 5*32+ 3) /* RWXUF */
|
|
#define NV_RAMFC_DMA_FETCH_SIZE ( 5*32+15):( 5*32+13) /* RWXUF */
|
|
#define NV_RAMFC_DMA_FETCH_MAX_REQS ( 5*32+20):( 5*32+16) /* RWXUF */
|
|
#define NV_RAMFC_BIG_ENDIAN ( 5*32+31):( 5*32+31) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_0 ( 6*32+ 1):( 6*32+ 0) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_1 ( 6*32+ 5):( 6*32+ 4) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_2 ( 6*32+ 9):( 6*32+ 8) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_3 ( 6*32+13):( 6*32+12) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_4 ( 6*32+17):( 6*32+16) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_5 ( 6*32+21):( 6*32+20) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_6 ( 6*32+25):( 6*32+24) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SUB_7 ( 6*32+29):( 6*32+28) /* RWXUF */
|
|
#define NV_RAMFC_ENGINE_SW 0x00000000 /* RW--V */
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#define NV_RAMFC_ENGINE_GRAPHICS 0x00000001 /* RW--V */
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#define NV_RAMFC_ENGINE_DVD 0x00000002 /* RW--V */
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#define NV_RAMFC_PULL1_ENGINE ( 7*32+ 1):( 7*32+ 0) /* RWXUF */
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#define NV_RAMFC_PULL1_ENGINE_SW 0x00000000 /* RW--V */
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#define NV_RAMFC_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */
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#define NV_RAMFC_PULL1_ENGINE_DVD 0x00000002 /* RW--V */
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#define NV_RAMFC_PULL1_ACQ_STATE ( 7*32+ 4):( 7*32+ 4) /* RWXVF */
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#define NV_RAMFC_PULL1_ACQ_STATE_INACTIVE 0x00000000 /* RW--V */
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#define NV_RAMFC_PULL1_ACQ_STATE_ACTIVE 0x00000001 /* RW--V */
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#define NV_RAMFC_PULL1_SEM_TARGET_NODE ( 7*32+17):( 7*32+16) /* RWXUF */
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#define NV_RAMFC_PULL1_SEM_TARGET_NODE_NVM 0x00000000 /* RW--V */
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#define NV_RAMFC_PULL1_SEM_TARGET_NODE_PCI 0x00000002 /* RW--V */
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#define NV_RAMFC_PULL1_SEM_TARGET_NODE_AGP 0x00000003 /* RW--V */
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#define NV_RAMFC_ACQUIRE_VALUE ( 8*32+31):( 8*32+ 0) /* RWXUF */
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#define NV_RAMFC_ACQUIRE_TIMESTAMP ( 9*32+31):( 9*32+ 0) /* RWXUF */
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#define NV_RAMFC_ACQUIRE_TIMEOUT (10*32+30):(10*32+ 0) /* RWXUF */
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#define NV_RAMFC_SEMAPHORE_CTXDMA (11*32+ 0):(11*32+ 0) /* RWXVF */
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#define NV_RAMFC_SEMAPHORE_CTXDMA_INVALID 0x00000000 /* RW--V */
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#define NV_RAMFC_SEMAPHORE_CTXDMA_VALID 0x00000001 /* RW--V */
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#define NV_RAMFC_SEMAPHORE_OFFSET (11*32+11):(11*32+ 2) /* RWXUF */
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#define NV_RAMFC_SEMAPHORE_PAGE_ADDRESS (11*32+31):(11*32+12) /* RWXUF */
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#define NV_RAMFC_DMA_SUBROUTINE_STATE (12*32+ 0):(12*32+ 0) /* RWXVF */
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#define NV_RAMFC_DMA_SUBROUTINE_STATE_INACTIVE 0x00000000 /* RW--V */
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#define NV_RAMFC_DMA_SUBROUTINE_STATE_ACTIVE 0x00000001 /* RW--V */
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#define NV_RAMFC_DMA_SUBROUTINE_RETURN_OFFSET (12*32+31):(12*32+ 2) /* RWXUF */
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/* dev_ram.ref */
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/* dev_ram.ref */
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/* dev_ram.ref */
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#define NV_RAMDVD_CTX_TABLE (63*32+31):( 0*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT(c,s) (((c)*4+((s)/2))*32+((s)%2)*16+15):(((c)*4+((s)/2))*32+((s)%2)*16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_0 ( 0*32+15):( 0*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_1 ( 0*32+31):( 0*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_2 ( 1*32+15):( 1*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_3 ( 1*32+31):( 1*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_4 ( 2*32+15):( 2*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_5 ( 2*32+31):( 2*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_6 ( 3*32+15):( 3*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_0_7 ( 3*32+31):( 3*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_0 (60*32+15):(60*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_1 (60*32+31):(60*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_2 (61*32+15):(61*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_3 (61*32+31):(61*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_4 (62*32+15):(62*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_5 (62*32+31):(62*32+16) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_6 (63*32+15):(63*32+ 0) /* RWXUF */
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#define NV_RAMDVD_CTX_TABLE_OBJECT_15_7 (63*32+31):(63*32+16) /* RWXUF */
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/* dev_ram.ref */
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/* dev_ram.ref */
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#define NV_DMA_CLASS ( 0*32+11):( 0*32+ 0) /* RWXUF */
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#define NV_DMA_PAGE_TABLE ( 0*32+12):( 0*32+12) /* RWXVF */
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#define NV_DMA_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */
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#define NV_DMA_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */
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#define NV_DMA_PAGE_ENTRY ( 0*32+13):( 0*32+13) /* RWXVF */
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#define NV_DMA_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */
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#define NV_DMA_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */
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#define NV_DMA_FLAGS_ACCESS ( 0*32+14):( 0*32+14) /* RWXVF */
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#define NV_DMA_FLAGS_ACCESS_READ_WRITE 0x00000000 /* RW--V */
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#define NV_DMA_FLAGS_ACCESS_OTHER 0x00000001 /* RW--V */
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#define NV_DMA_FLAGS_MAPPING_COHERENCY ( 0*32+15):( 0*32+15) /* RWXVF */
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#define NV_DMA_FLAGS_MAPPING_COHERENCY_UNCACHED 0x00000000 /* RW--V */
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#define NV_DMA_FLAGS_MAPPING_COHERENCY_CACHED 0x00000001 /* RW--V */
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#define NV_DMA_TARGET_NODE ( 0*32+17):( 0*32+16) /* RWXVF */
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#define NV_DMA_TARGET_NODE_NVM 0x00000000 /* RW--V */
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#define NV_DMA_TARGET_NODE_NVM_TILED 0x00000001 /* RW--V */
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#define NV_DMA_TARGET_NODE_PCI 0x00000002 /* RW--V */
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#define NV_DMA_TARGET_NODE_AGP 0x00000003 /* RW--V */
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#define NV_DMA_MEMORY_CLASS ( 0*32+19):( 0*32+18) /* RWXVF */
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#define NV_DMA_MEMORY_CLASS_NV01_MEMORY_LOCAL_LINEAR 0x00000000 /* RW--V */
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#define NV_DMA_MEMORY_CLASS_NV01_MEMORY_LOCAL_BANKED 0x00000001 /* RW--V */
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#define NV_DMA_MEMORY_CLASS_NV01_MEMORY_SYSTEM 0x00000002 /* RW--V */
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#define NV_DMA_MEMORY_CLASS_OTHER 0x00000003 /* RW--V */
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#define NV_DMA_ADJUST ( 0*32+31):( 0*32+20) /* RWXUF */
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#define NV_DMA_LIMIT ( 1*32+31):( 1*32+ 0) /* RWXUF */
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#define NV_DMA_ACCESS ( 2*32+ 1):( 2*32+ 1) /* RWXVF */
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#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */
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#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */
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#define NV_DMA_FRAME_ADDRESS ( 2*32+31):( 2*32+12) /* RWXUF */
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/* dev_ram.ref */
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#define NV_SUBCHAN_CTX_SWITCH ( 0*32+31):( 0*32+ 0) /* RWXUF */
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#define NV_SUBCHAN_DMA_INSTANCE ( 1*32+15):( 1*32+ 0) /* RWXUF */
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#define NV_SUBCHAN_NOTIFY_INSTANCE ( 1*32+31):( 1*32+16) /* RWXUF */
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#define NV_SUBCHAN_MEMFMT_INSTANCE ( 2*32+15):( 2*32+ 0) /* RWXUF */
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#define NV_SUBCHAN_MEMFMT_LINEAR ( 2*32+16):( 2*32+16) /* RWXUF */
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#define NV_SUBCHAN_MEMFMT_LINEAR_OUT 0x00000000 /* RW--V */
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#define NV_SUBCHAN_MEMFMT_LINEAR_IN 0x00000001 /* RW--V */
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#endif /* _NV_REF_H_ */
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