723 lines
25 KiB
C
723 lines
25 KiB
C
#ifndef _DAC_H_
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#define _DAC_H_
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/***************************************************************************\
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|* *|
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|* Copyright (c) 1993-2000 NVIDIA, Corp. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|
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|* the copyright and as design patents pending on the design and *|
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|* interface of the NV chips. Users and possessors of this source *|
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|* code are hereby granted a nonexclusive, royalty-free copyright *|
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|* and design patent license to use this code in individual and *|
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|* commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright (c) 1993-2000 NVIDIA, Corp. NVIDIA design patents *|
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|* pending in the U.S. and foreign countries. *|
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|* *|
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|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *|
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|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *|
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|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *|
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|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *|
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|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|
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|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *|
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|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|
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|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *|
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|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *|
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|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *|
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|* PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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\***************************************************************************/
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/********************************* DAC Module ******************************\
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* *
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* Module: DAC.H *
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* DAC support routines. *
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* *
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\***************************************************************************/
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#include <nvmisc.h> // pick up I2C structures
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#include <nvcm.h> // ick ick ick ick
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//
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// Microport access macros.
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//
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#ifdef SOLARIS
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// 3-6-96 With updated model simulation requires DAC initialization, so
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// we place back the DAC macros.
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/*
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#define DAC_WR08(rr,dd)
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#define DAC_INDEX_WR08(ii,dd)
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#define DAC_RD08(rr) \
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(REG_RD32(rr)&0xFF)
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#define DAC_INDEX_RD08(ii,dd) \
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DAC_WR08(SGS_DAC_UPORT_INDEX_LO,(ii)); \
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DAC_WR08(SGS_DAC_UPORT_INDEX_HI,(ii)>>8);\
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(dd)=DAC_RD08(SGS_DAC_UPORT_INDEX_DATA)
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*/
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// Origional DAC Macros for RM.
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#define DAC_WR08(rr,dd) \
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REG_WR32((rr),(dd)&0xFF)
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#define DAC_INDEX_WR08(ii,dd) \
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DAC_WR08(SGS_DAC_UPORT_INDEX_LO,(ii)); \
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DAC_WR08(SGS_DAC_UPORT_INDEX_HI,(ii)>>8);\
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DAC_WR08(SGS_DAC_UPORT_INDEX_DATA,(dd))
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#define DAC_RD08(rr) \
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(REG_RD32(rr)&0xFF)
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#define DAC_INDEX_RD08(ii,dd) \
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DAC_WR08(SGS_DAC_UPORT_INDEX_LO,(ii)); \
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DAC_WR08(SGS_DAC_UPORT_INDEX_HI,(ii)>>8);\
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(dd)=DAC_RD08(SGS_DAC_UPORT_INDEX_DATA)
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#else // ifdef SOLARIS
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#if 0
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#define DAC_WR08(rr,dd) \
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REG_WR32((rr),(dd)&0xFF)
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#endif
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#define DAC_INDEX_WR08(ii,dd) \
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DAC_WR08(SGS_DAC_UPORT_INDEX_LO,(ii)); \
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DAC_WR08(SGS_DAC_UPORT_INDEX_HI,(ii)>>8);\
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DAC_WR08(SGS_DAC_UPORT_INDEX_DATA,(dd))
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#if 0
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#define DAC_RD08(rr) \
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(REG_RD32(rr)&0xFF)
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#endif
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#define DAC_INDEX_RD08(ii,dd) \
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DAC_WR08(SGS_DAC_UPORT_INDEX_LO,(ii)); \
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DAC_WR08(SGS_DAC_UPORT_INDEX_HI,(ii)>>8);\
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(dd)=DAC_RD08(SGS_DAC_UPORT_INDEX_DATA)
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#endif // ifdef SOLARIS
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/* XXX temporary until they appear in nv_def.h */
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#define NV_CIO_CRE_DDC0_STATUS__INDEX 0x00000036
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#define NV_CIO_CRE_DDC0_WR__INDEX 0x00000037
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#define CRTC2 1
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// These macros access the DAC (including PCRTC) for either of two heads
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#define DAC_REG_WR08(a,d,h) \
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REG_WR08(a + CurDacAdr(h), d)
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#define DAC_REG_WR32(a,d,h) \
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REG_WR32(a + CurDacAdr(h), d)
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#define DAC_REG_RD08(a,h) \
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REG_RD08(a + CurDacAdr(h))
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#define DAC_REG_RD32(a,h) \
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REG_RD32(a + CurDacAdr(h))
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// We need special versions of these macros for HAL use...
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#define HAL_DAC_REG_WR32(a,d,o) \
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REG_WR32(a + o, d)
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#define HAL_DAC_REG_RD32(a,o) \
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REG_RD32(a + o)
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#define DAC_FLD_WR_DRF_DEF(d,r,f,c,h) \
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REG_WR32(NV##d##r + CurDacAdr(h),(REG_RD32(NV##d##r + CurDacAdr(h))&~(DRF_MASK(NV##d##r##f)<<DRF_SHIFT(NV##d##r##f)))|DRF_DEF(d,r,f,c))
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// HAL Version
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#define HAL_DAC_FLD_WR_DRF_DEF(d,r,f,c,o) \
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REG_WR32(NV##d##r + o,(REG_RD32(NV##d##r + o)&~(DRF_MASK(NV##d##r##f)<<DRF_SHIFT(NV##d##r##f)))|DRF_DEF(d,r,f,c))
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#define DAC_FLD_WR_DRF_NUM(d,r,f,n,h) \
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REG_WR32(NV##d##r + CurDacAdr(h),(REG_RD32(NV##d##r + CurDacAdr(h))&~(DRF_MASK(NV##d##r##f)<<DRF_SHIFT(NV##d##r##f)))|DRF_NUM(d,r,f,n))
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#define DAC_REG_WR_DRF_DEF(d,r,f,c,h) \
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REG_WR32(NV ## d ## r + CurDacAdr(h), DRF_DEF(d,r,f,c))
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#define DAC_REG_RD_DRF(d,r,f,h) \
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((REG_RD32(NV##d##r + CurDacAdr(h))>>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f))
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// HAL Version
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#define HAL_DAC_REG_RD_DRF(d,r,f,o) \
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((REG_RD32(NV##d##r + o)>>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f))
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//---------------------------------------------------------------------------
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// Standard VGA Mode Table Structure
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typedef struct _seq_
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{
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U008 ClockMode;
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U008 MapMask;
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U008 FontAddr;
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U008 MemMode;
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} SEQ;
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typedef struct _crtc_
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{
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U008 HTotal;
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U008 HDispEnd;
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U008 HBlankS;
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U008 HBlankE;
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U008 HSyncS;
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U008 HSyncE;
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U008 VTotal;
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U008 Overflow;
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U008 PresetRowScan;
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U008 CellHeight;
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U008 CursorS;
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U008 CursorE;
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U008 RegenSHigh;
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U008 RegenSLow;
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U008 CursorPosHigh;
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U008 CursorPosLow;
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U008 VSyncS;
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U008 VSyncE;
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U008 VDispE;
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U008 RowOffset;
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U008 ULineRow;
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U008 VBlankS;
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U008 VBlandE;
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U008 Mode;
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U008 LineCompare;
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} CRTC;
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typedef struct _gr_
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{
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U008 SetReset;
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U008 EnableSetReset;
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U008 ColorCmp;
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U008 ROP;
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U008 ReadMap;
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U008 Mode;
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U008 Misc;
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U008 CDC;
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U008 BitMask;
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} GR;
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// Standard VGA Mode Table format.
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typedef struct _vga_mode_
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{
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U008 columns;
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U008 rows;
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U008 char_height;
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U016 RegenLenght;
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SEQ seq_regs; // SR1-4
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U008 PT_Misc; // Misc Register
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CRTC crtc_regs; // CR0-18
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U008 PT_ATC[20]; // Attribute Controller
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GR gr_regs; // GR0-8
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} VGATBL;
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// TVformat types
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#define NTSC 0
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#define PAL 1
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// TV encoders
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#define NO_ENCODER 0
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#define BROOKTREE 1
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#define CHRONTEL 2
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#define BROOKTREE_ID 0x8A
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#define CHRONTEL_ID 0xEA
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#define ERR_I2C_MODE 1
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#define ERR_I2C_COMM 2
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#define ERR_I2C_UNKNOWN 3
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// Timing parameters, defined by CRTC containing low order bits
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#define H_TOTAL 0
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#define H_DISPLAY_END 1
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#define H_BLANK_START 2
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#define H_BLANK_END 3
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#define H_RETRACE_START 4
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#define H_RETRACE_END 5
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#define V_TOTAL 6
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#define V_DISPLAY_END 0x12
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#define V_RETRACE_START 0x10
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#define V_RETRACE_END 0x11
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#define V_BLANK_START 0x15
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#define V_BLANK_END 0x16
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// Adjustments for TV
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typedef struct
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{
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U032 hRes;
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U032 vRes;
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U008 SR01;
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U008 CR00;
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U008 CR04;
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U008 CR06;
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U008 CR07;
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U008 CR08;
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U008 CR10;
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U008 CR12;
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U008 CR28;
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U008 *encoderString;
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} TV_ADJUST;
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//typedef struct _I2C_string_struct_
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typedef struct
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{
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U008 Dev;
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U008 reg0x00;
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U008 data0x00;
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U008 reg0x07;
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U008 data0x07;
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U008 reg0x0A;
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U008 data0x0A;
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U008 reg0x0B;
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U008 data0x0B;
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U008 reg0x13;
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U008 data0x13;
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U008 data0x14;
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U008 data0x15;
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U008 terminator;
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} CH_string, *PCH_string;
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// Brooktree values -- 1 byte device ID, 6 bytes centering info, 33 bytes resolution info
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typedef struct
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{
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U008 Dev;
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U008 btc1;
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U008 btc2;
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U008 btc3;
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U008 btc4;
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U008 btc5;
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U008 btc6;
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U008 bt1;
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U008 bt2;
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U008 bt3;
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U008 bt4;
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U008 bt5;
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U008 bt6;
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U008 bt7;
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U008 bt8;
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U008 bt9;
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U008 bt10;
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U008 bt11;
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U008 bt12;
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U008 bt13;
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U008 bt14;
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U008 bt15;
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U008 bt16;
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U008 bt17;
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U008 bt18;
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U008 bt19;
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U008 bt20;
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U008 bt21;
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U008 bt22;
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U008 bt23;
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U008 bt24;
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U008 bt25;
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U008 bt26;
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U008 bt27;
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U008 bt28;
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U008 bt29;
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U008 bt30;
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U008 bt31;
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U008 bt32;
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U008 bt33;
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U008 termination;
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} BT_string, *PBT_string;
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// DAC Flat Panel Timing struture
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// Corresponds to HW regs which must be programmed for flat panel.
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typedef struct DacFlatPanelTimings
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{
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U032 PixClk;
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U032 HActive;
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U032 HDispEnd;
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U032 HValidStart;
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U032 HValidEnd;
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U032 HSyncStart;
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U032 HSyncEnd;
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U032 HTotal;
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U032 VActive;
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U032 VDispEnd;
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U032 VValidStart;
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U032 VValidEnd;
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U032 VSyncStart;
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U032 VSyncEnd;
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U032 VTotal;
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U032 Flags;
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} DACFPTIMING, * PDACFPTIMING;
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#define NV10_VSCALAR_TV_ADJUST 0x00010004 // adjustment for video overlay on TV
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//
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// Monitor position state. Set during modeset and returned
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// to clients via cfg get interfaces.
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//
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typedef struct _dac_monitor_position {
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U032 Hbs;
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U032 Hbe;
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U032 Vbs;
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U032 Vbe;
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U032 Hrs;
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U032 Hre;
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U032 Vrs;
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U032 Vre;
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} DACMONITORPOSITION, *PDACMONITORPOSITION;
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//
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// Per-CRTC information.
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// There is one of these structures for each possible CRTC in
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// the system.
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//
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typedef struct _dac_crtc_info
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{
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// Number of VIDEO_LUT_CURSOR_DAC objects allocated for this head
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U032 RefCount;
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VOID_PTR pVidLutCurDac; //Head-specific pointer, null if head is disabled.
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#define DAC_CRTCINFO_VBLANK_ENABLED 0x0001
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U032 StateFlags;
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U032 UpdateFlags;
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// Panning/Buffer Flip data (used across LUT_CURSOR_DAC objects)
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U032 CurrentPanOffset;
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U032 CurrentImageOffset;
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// Display info
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U032 CurrentDisplay;
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U032 DisplayChanged;
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U032 CurrentVsyncState;
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U032 CurrentHsyncState;
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BOOL SyncStateIsSaved;
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U032 CurrentPowerState;
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// VBlank data
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BOOL IsVBlank;
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U032 VBlankToggle;
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U032 VBlankCounter;
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VOID_PTR VBlankCallbackList;
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// NvSysMoveCursor data
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S032 CursorPosX;
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S032 CursorPosY;
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// NvSysSetCursorImage data
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U032 CursorWidth;
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U032 CursorHeight;
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U032 CursorOffset;
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U032 CursorColorFormat;
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// NvSysSetCursor data
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U008 CursorImagePlane[2][32 * sizeof(U032)];
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U032 CursorType;
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// NvSysUpdateImageFormat data
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U032 ImageOffset;
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U032 ImageFormat;
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U032 ChID;
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U032 ObjectHandle;
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// Monitor position data
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DACMONITORPOSITION MonitorPosition;
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// EDID data
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U008 EdidVersion;
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U008 EdidDisplayType;
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U008 EDID[256];
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} DACCRTCINFO, *PDACCRTCINFO;
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// defines for the BIOS Display Config Block
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#define DCB_PTR_OFFSET 0x0036 // from VGA BIOS base
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// following offset are relative to the DCB base
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#define DCB_REVISION_OFFSET 0x0000
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#define DCB_SIZE_128B_OFFSET 0x0001 // size is in 128 bytes block
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#define DCB_ICB_OFFSET 0x0002 // I2C ports configuration block
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#define DCB_DEV_DESC_OFFSET 0x0004
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#define DCB_FIRST_REVISION 0x13 // revision in BCD format
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// 1st revision that supports DCB
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#define DCB_BLOCK_SIZE 128
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// each device descriptor consists of 2 32-bit words and a short pointer,
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// the first 32-bit word is the device type record, the second one is the data record.
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// TYPE field definitions
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#define DCB_DEV_REC_TYPE_CRT 0x0
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#define DCB_DEV_REC_TYPE_TV 0x1
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#define DCB_DEV_REC_TYPE_DD_SLINK 0x2
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#define DCB_DEV_REC_TYPE_DD_DLINK 0x3
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#define DCB_DEV_REC_TYPE_EOL 0xf // End of list
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#define DCB_DEV_REC_TYPE_UNUSED 0xf
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// SUBTYPE field definitions
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#define DCB_DEV_REC_SUBTYPE_UNUSED 0xf
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// CRT subtypes
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#define DCB_DEV_REC_SUBTYPE_CRT_DAC_INTERNAL 0x0
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#define DCB_DEV_REC_SUBTYPE_CRT_DAC_FAIRCHILD 0x1
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#define DCB_DEV_REC_SUBTYPE_CRT_UNUSED DCB_DEV_REC_SUBTYPE_UNUSED
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// TV subtypes
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#define DCB_DEV_REC_SUBTYPE_TV_BROOKTREE 0x0
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#define DCB_DEV_REC_SUBTYPE_TV_CHRONTEL 0x1
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#define DCB_DEV_REC_SUBTYPE_TV_PHILIPS 0x2
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#define DCB_DEV_REC_SUBTYPE_TV_UNUSED DCB_DEV_REC_SUBTYPE_UNUSED
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// digital display subtypes
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#define DCB_DEV_REC_SUBTYPE_DD_TMDS 0x0
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#define DCB_DEV_REC_SUBTYPE_DD_LVDS 0x1
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#define DCB_DEV_REC_SUBTYPE_DD_UNUSED DCB_DEV_REC_SUBTYPE_UNUSED
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// FORMAT field definitions
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#define DCB_DEV_REC_FMT_UNUSED 0x3f
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// CRT format definitions
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#define DCB_DEV_REC_FMT_CRT_UNUSED DCB_DEV_REC_FMT_UNUSED
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// TV format definitions
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#define DCB_DEV_REC_FMT_TV_NTSC_M 0x00
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#define DCB_DEV_REC_FMT_TV_NTSC_J 0x01
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#define DCB_DEV_REC_FMT_TV_PAL_M 0x02
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#define DCB_DEV_REC_FMT_TV_PAL_BDGHI 0x03
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#define DCB_DEV_REC_FMT_TV_PAL_N 0x04
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#define DCB_DEV_REC_FMT_TV_PAL_NC 0x05
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#define DCB_DEV_REC_FMT_TV_SECAM 0x06
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#define DCB_DEV_REC_FMT_TV_STRAPS 0x0f
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#define DCB_DEV_REC_FMT_TV_UNUSED DCB_DEV_REC_FMT_UNUSED
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// DFP format definitions
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#define DCB_DEV_REC_FMT_DD_FIXED_00 0x00
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#define DCB_DEV_REC_FMT_DD_FIXED_01 0x01
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#define DCB_DEV_REC_FMT_DD_FIXED_02 0x02
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#define DCB_DEV_REC_FMT_DD_FIXED_03 0x03
|
|
#define DCB_DEV_REC_FMT_DD_FIXED_04 0x04
|
|
#define DCB_DEV_REC_FMT_DD_FIXED_05 0x05
|
|
#define DCB_DEV_REC_FMT_DD_FIXED_06 0x06
|
|
#define DCB_DEV_REC_FMT_DD_FIXED_07 0x07
|
|
#define DCB_DEV_REC_FORMAT_DD_DDC 0x10
|
|
#define DCB_DEV_REC_FMT_DD_STRAPS 0x1f
|
|
#define DCB_DEV_REC_FMT_DD_UNUSED DCB_DEV_REC_FMT_UNUSED
|
|
|
|
// I2C_PORT field definitions
|
|
#define DCB_DEV_REC_LOGICAL_PORT_0 0x0
|
|
#define DCB_DEV_REC_LOGICAL_PORT_1 0x1
|
|
#define DCB_DEV_REC_LOGICAL_PORT_2 0x2
|
|
#define DCB_DEV_REC_LOGICAL_PORT_UNUSED 0xf
|
|
|
|
// HEAD field definitions
|
|
#define DCB_DEV_REC_HEAD_A 0x0
|
|
#define DCB_DEV_REC_HEAD_B 0x1
|
|
#define DCB_DEV_REC_HEAD_UNUSED 0x7
|
|
|
|
// LOCATION field definitions
|
|
#define DCB_DEV_REC_LOCATION_CHIP 0x0
|
|
#define DCB_DEV_REC_LOCATION_BOARD 0x1
|
|
#define DCB_DEV_REC_LOCATION_UNUSED 0xf
|
|
|
|
// BUS field definitions
|
|
#define DCB_DEV_REC_BUS_0 0x0
|
|
#define DCB_DEV_REC_BUS_1 0x1
|
|
#define DCB_DEV_REC_BUS_2 0x2
|
|
#define DCB_DEV_REC_BUS_3 0x3
|
|
#define DCB_DEV_REC_BUS_4 0x4
|
|
#define DCB_DEV_REC_BUS_5 0x5
|
|
#define DCB_DEV_REC_BUS_6 0x6
|
|
#define DCB_DEV_REC_BUS_UNUSED 0x7
|
|
|
|
// RSVD field definitions
|
|
#define DCB_DEV_REC_RSVD_UNUSED 0xf
|
|
|
|
#define DCB_MAX_NUM_DEVDESCS 16 // max # of device descriptors and I2C
|
|
#define DCB_MAX_NUM_I2C_RECORDS 16 // records supported by current DCB
|
|
|
|
typedef struct {
|
|
union {
|
|
struct {
|
|
U032 Type :4; // CRT, TV, DD
|
|
U032 Subtype :4;
|
|
U032 Fmt :6;
|
|
U032 IdxToICB :4; // index into I2C Config Block
|
|
U032 Head :3;
|
|
U032 Location :4; // chip, board
|
|
U032 Bus :3;
|
|
U032 Rsvd :4;
|
|
} DevRec;
|
|
|
|
U032 DevRec_U032;
|
|
} DCBDevRec;
|
|
|
|
U016 DataPtr;
|
|
|
|
union {
|
|
U032 DataReserved;
|
|
U008 DataByte;
|
|
U016 DataWord;
|
|
U032 DataDword;
|
|
} DCBDevData;
|
|
|
|
// this var tells device type and unit by the lone set bit
|
|
U032 DevTypeUnit; // bits 0..7 map to CRT0..CRT7
|
|
// bits 8..15 map to TV0..TV7
|
|
// bits 16..23 map to DD0..DD7
|
|
} DACDCBDEVDESC, *PDACDCBDEVDESC;
|
|
|
|
// shortcuts for accessing DCB device descriptor field
|
|
#define DCBRecType DCBDevRec.DevRec.Type
|
|
#define DCBRecSubtype DCBDevRec.DevRec.Subtype
|
|
#define DCBRecFmt DCBDevRec.DevRec.Fmt
|
|
#define DCBRecIdxToICB DCBDevRec.DevRec.IdxToICB
|
|
#define DCBRecHead DCBDevRec.DevRec.Head
|
|
#define DCBRecLocation DCBDevRec.DevRec.Location
|
|
#define DCBRecBus DCBDevRec.DevRec.Bus
|
|
|
|
#define I2C_PHYSICAL_PORT_A_STATUS 0x3E // CR3E
|
|
#define I2C_PHYSICAL_PORT_A_DATA 0x3F // CR3F
|
|
#define I2C_PHYSICAL_PORT_B_STATUS 0x36 // CR36
|
|
#define I2C_PHYSICAL_PORT_B_DATA 0x37 // CR37
|
|
#define I2C_PHYSICAL_PORT_C_STATUS 0x50 // CR50
|
|
#define I2C_PHYSICAL_PORT_C_DATA 0x51 // CR51
|
|
#define I2C_PHYSICAL_PORT_UNUSED 0xFF // Unused I2C Port
|
|
|
|
#define I2C_PORT_UNUSED 0xFF // Port is not used
|
|
|
|
// i2c_access field - Access methods for I2C Port
|
|
#define I2C_PORT_ACCESS_UNUSED 0x03 // No access method defined
|
|
#define I2C_PORT_ACCESS_CRTC_INDEXED 0x00 // Indexed IO at 3x4/3x5
|
|
#define I2C_PORT_ACCESS_DIRECT_IO 0x01 // Direct IO (not indexed)
|
|
|
|
// i2c_rsvd field
|
|
#define I2C_PORT_RSVD_UNUSED 0x3F // Unused
|
|
|
|
#define I2C_PORT_IOPORT_HI_UNUSED 0xFF // Unused
|
|
|
|
|
|
typedef struct {
|
|
U008 WritePort;
|
|
U008 ReadPort;
|
|
U016 IoPortHi :8;
|
|
U016 I2cAccess :2;
|
|
U016 Reserved :6;
|
|
|
|
} DACDCBI2CRECORD, *pDACDCBI2CRECORD;
|
|
|
|
//
|
|
// Function prototypes for Video DAC.
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
|
|
RM_STATUS initDac(PHWINFO);
|
|
RM_STATUS dacCreateObj(VOID *, PCLASSOBJECT, U032, POBJECT *, VOID*);
|
|
RM_STATUS dacDestroyObj(VOID *, POBJECT);
|
|
RM_STATUS dacSetDpmLevel(PHWINFO);
|
|
RM_STATUS dacLoadReg(U032, U032, U032);
|
|
RM_STATUS dacLoadWidthDepth(PHWINFO, U032);
|
|
RM_STATUS dacCalcPLL(PHWINFO);
|
|
U032 dacCalcMNP(PHWINFO, U032, U032, U032 *, U032 *, U032 *);
|
|
RM_STATUS dacLoadPClkVClkRatio(VOID);
|
|
RM_STATUS dacCalcPClkVClkRatio(VOID);
|
|
RM_STATUS dacGetDisplayInfo(PHWINFO, U032, U032 *, U032 *, U032 *, U032 *);
|
|
RM_STATUS dacProgramPClk(PHWINFO, U032, U032);
|
|
RM_STATUS dacProgramMClk(PHWINFO);
|
|
RM_STATUS dacProgramNVClk(PHWINFO);
|
|
RM_STATUS dacVBlank(PHWINFO);
|
|
RM_STATUS dacUpdateEmulatedCursor(VOID);
|
|
RM_STATUS dacHideEmulatedCursor(VOID);
|
|
VOID dacEnableCursor(PHWINFO, U032);
|
|
VOID dacDisableCursor(PHWINFO, U032);
|
|
VOID dacEnableDac(PHWINFO, U032);
|
|
VOID dacDisableDac(PHWINFO, U032);
|
|
VOID dacDisableImage(PHWINFO, U032);
|
|
VOID dacEnableImage(PHWINFO, U032);
|
|
VOID dacDisableTV(PHWINFO, U032);
|
|
VOID dacEnableTV(PHWINFO, U032);
|
|
RM_STATUS dacProgramCursorImage(PHWINFO, U032, U032, U032, U032, U032);
|
|
RM_STATUS dacProgramCursorPosition(PHWINFO, U032, U032, U032);
|
|
RM_STATUS dacProgramVideoStart(PHWINFO, U032, U032, U032);
|
|
RM_STATUS dacProgramLUT(PHWINFO, U032, U032*, U032);
|
|
RM_STATUS dacProgramScanRegion(PHWINFO, U032, U032, U032, U032);
|
|
RM_STATUS dacSetMonitorPosition(PHWINFO, U032, U032, U032, U032, U032);
|
|
VOID dacGetMonitorDefaultPosition(PHWINFO, U032, U032 *, U032 *, U032 *,
|
|
U032 *, U032 *, U032 *, U032 *, U032 *);
|
|
VOID dacSaveMonitorDefaultPosition(PHWINFO, U032);
|
|
VOID dacGetDefaultTVPosition(PHWINFO, U032, U032, U008, U032 *);
|
|
VOID dacSetTVPosition(PHWINFO, U032, U032 *);
|
|
RM_STATUS dacWriteDesktopPositionToRegistry(PHWINFO, U032, BOOL, U008 *, U032);
|
|
RM_STATUS dacReadDesktopPositionFromRegistry(PHWINFO, U032, BOOL, U008 *, U032 *);
|
|
RM_STATUS dacReadTVDesktopPositionFromRegistry(PHWINFO, U032, U008 *, U032 *);
|
|
RM_STATUS dacReadTVOutFromRegistry(PHWINFO, U032, U032 *);
|
|
RM_STATUS dacWriteTVOutToRegistry(PHWINFO, U032, U032);
|
|
RM_STATUS dacGetBiosDefaultTVType(PHWINFO, U032 *);
|
|
|
|
BOOL dacMonitorConnectStatus(PHWINFO, U032);
|
|
RM_STATUS dacGetFlatPanelInfo(PHWINFO, U032, U032 *, U032 *, U032 *, BOOL *, BOOL *, BOOL);
|
|
RM_STATUS dacSetFlatPanelMode(PHWINFO, U032, PVIDEO_LUT_CURSOR_DAC_OBJECT, U032, BOOL);
|
|
U032 dacGetFlatPanelConfig(PHWINFO, U032);
|
|
BOOL dacFlatPanelConnectStatus(PHWINFO pDev, U032);
|
|
RM_STATUS dacGetSyncState(PHWINFO, U032 Head, U032 *pHsync, U032 *pVsync);
|
|
RM_STATUS dacSetSyncState(PHWINFO, U032 Head, U032 Hsync, U032 Vsync);
|
|
RM_STATUS dacGetFlatPanelBrightness(PHWINFO, U032 Head, U032 * Brightness, BOOL * ControllerIsOn);
|
|
RM_STATUS dacSetFlatPanelBrightness(PHWINFO, U032 Head, U032 Brightness, U032 Frequency, U032 MaxPercent, U032 MinPercent,BOOL ControllerIsOn);
|
|
|
|
//housekeeping PWM functions, reduces large spread of reg-rds to 3 closely spaced spots
|
|
void dacZeroPWMController(PHWINFO);
|
|
void dacSetPWMController(PHWINFO);
|
|
void dacGetPWMController(PHWINFO);
|
|
|
|
//an abstraction of flat panel operations
|
|
BOOL dacIsFlatPanelOn(PHWINFO pDev,U032 Head);
|
|
|
|
//some directly associated routines for adjusting brightness
|
|
U032 GetTicksForFrequency(U032 Frequency);
|
|
U032 GetAbsoluteDifference(U032 value_a,U032 value_b);
|
|
U032 GetRequiredTickCount(U032 Frequency,U032 MaxPercent,U032 MinPercent,U032 BaseMultiplier);
|
|
U032 GetPortionOfTotalSizeBasedOnPercentage(U032 TotalSize,U032 Percentage);
|
|
//U032 GetPercentageofTotalSize(U032 TotalSize,U032 Portion);
|
|
//U032 DetermineMultiplierForCurrentPeriod(PHWINFO pDev,U032 ClockTicksTotal,U032 DutyCycle);
|
|
U032 DetermineFrequencyFromTickCount(U032 NumTicks);
|
|
|
|
U032 dacGetCRTC(PHWINFO, U032, U032);
|
|
VOID dacSetCRTC(PHWINFO, U032, U032, U032);
|
|
RM_STATUS dacGetCRTCTiming(PHWINFO, U032, NV_CFGEX_CRTC_TIMING_PARAMS *);
|
|
RM_STATUS dacSetCRTCTiming(PHWINFO, U032, NV_CFGEX_CRTC_TIMING_PARAMS *);
|
|
RM_STATUS dacSetMode(PHWINFO, U032);
|
|
RM_STATUS dacSetModeMulti(PHWINFO, PVIDEO_LUT_CURSOR_DAC_OBJECT);
|
|
RM_STATUS dacSetupTVEncoder(PHWINFO, U032);
|
|
RM_STATUS dacAdjustCRTCForTV(PHWINFO, U032);
|
|
RM_STATUS dacAdjustCRTCForFlatPanel(PHWINFO, U032, PVIDEO_LUT_CURSOR_DAC_OBJECT);
|
|
|
|
U032 dacGetBiosDisplayType(PHWINFO, U032);
|
|
BOOL dacIsPAL(VOID);
|
|
U008 ReadCRTCLock(PHWINFO, U032);
|
|
|
|
RM_STATUS dacGetMonitorInfo(PHWINFO, U032, U032*);
|
|
VOID dacSetCursorBlink(PHWINFO, U032, U008);
|
|
VOID dacSetFan(PHWINFO, U008);
|
|
RM_STATUS dacGetColorSaturationBoost(PHWINFO, U032, U008*);
|
|
RM_STATUS dacSetColorSaturationBoost(PHWINFO, U032, U008);
|
|
BOOL dacTVConnectStatus(PHWINFO, U032);
|
|
U008 dacTVReadModifyWrite(PHWINFO, U032, U008, U008, U008);
|
|
//RM_STATUS IsMonitorDDC(PHWINFO, U032, U032, U008 *);
|
|
RM_STATUS dacReadBIOSI2CSettings(PHWINFO pDev);
|
|
VOID dacDetectEncoder(PHWINFO, U032);
|
|
BOOL dacVGAConnectStatus(PHWINFO, U032);
|
|
RM_STATUS dacPowerOnMobilePanel(PHWINFO, U032);
|
|
RM_STATUS dacPowerOffMobilePanel(PHWINFO, U032);
|
|
// EXPER:
|
|
BOOL dacIsNV5orBetter(PHWINFO pDev);
|
|
RM_STATUS i2cAccess(PHWINFO, U032, NVRM_I2C_ACCESS_CONTROL *);
|
|
VOID RestoreLock(PHWINFO, U032, U008);
|
|
VOID SeqWr(PHWINFO, U032, U008, U008);
|
|
U008 SeqRd(PHWINFO, U032, U008);
|
|
VOID EnableSeq(PHWINFO, U032);
|
|
U008 UnlockCRTC();
|
|
VOID RestoreCRTC(U008);
|
|
VOID AssocDDC(PHWINFO, U032);
|
|
VOID AssocTV(PHWINFO, U032);
|
|
VOID AssocVideoScalar(PHWINFO, U032);
|
|
VOID EnableHead(PHWINFO, U032);
|
|
VOID EnableMobileHotkeyHandling(PHWINFO pDev);
|
|
VOID DisableMobileHotkeyHandling(PHWINFO pDev);
|
|
V032 dacService(PHWINFO);
|
|
RM_STATUS dacParseDCBFromBIOS(PHWINFO);
|
|
VOID dacDevicesConnectStatus(PHWINFO, U032 *);
|
|
RM_STATUS dacFindDevicesConfiguration(PHWINFO, U032, U032 *, U032, U032);
|
|
void RmProperClockPdivProgrammer(PHWINFO pDev,U032 ClockAddress,U032 NewValue);
|
|
|
|
#endif // _DAC_H_
|