154 lines
7.6 KiB
C
154 lines
7.6 KiB
C
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/***************************************************************************\
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|* *|
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|* Copyright (c) 1993-1997 NVIDIA, Corp. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|
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|* the copyright and as design patents pending on the design and *|
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|* interface of the NV chips. Users and possessors of this source *|
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|* code are hereby granted a nonexclusive, royalty-free copyright *|
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|* and design patent license to use this code in individual and *|
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|* commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright (c) 1993-1997 NVIDIA, Corp. NVIDIA design patents *|
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|* pending in the U.S. and foreign countries. *|
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|* *|
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|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *|
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|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *|
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|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *|
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|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *|
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|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|
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|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *|
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|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|
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|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *|
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|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *|
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|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *|
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|* PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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\***************************************************************************/
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/***************************** EDID includes *******************************\
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* *
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* Module: EDID.H *
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* This module contains structure and prototype definitions used in the *
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* EDID utility functions. *
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* *
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*****************************************************************************
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* *
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* History: *
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* *
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\***************************************************************************/
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#ifndef _EDID_H_
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#define _EDID_H_
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RM_STATUS StopDDC1(PHWINFO, U032, U032);
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RM_STATUS IsMonitorDDC(PHWINFO, U032, U032, U008 *);
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RM_STATUS edidReadDevEDID(PHWINFO, U032, U008 *);
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BOOL edidLogicalEDIDIsValid(U008 **, U032 *, U032 *);
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RM_STATUS EDIDRead(PHWINFO, U032, U032);
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RM_STATUS EDIDGetMaxRefreshRate(PHWINFO, U032, U032, U032 *);
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RM_STATUS EDIDIsMonitorGTF (PHWINFO, BOOL *);
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RM_STATUS ReadVDIF(PHWINFO, U032, U032, U008 *, U008, U008);
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RM_STATUS EDIDCopy(PHWINFO, U008 *, U032 *, U032);
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RM_STATUS ParseEDID2(PHWINFO, U032);
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RM_STATUS ParseEDID12(PHWINFO, U032);
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RM_STATUS ParseEDID11(PHWINFO, U032);
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RM_STATUS fpParseEDID(PHWINFO, U032);
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U032 edidParseDetailedTimingBlock(PHWINFO, U008, PDACFPTIMING, U032);
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U032 edidParseDetailed1(PHWINFO, U008, PDACFPTIMING, U032);
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U032 edidParseDetailed2(PHWINFO, U008, PDACFPTIMING, U032);
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U032 edidGetVersion(PHWINFO, U032);
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BOOL edidIsAnalogDisplay(PHWINFO, U032);
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BOOL edidIsDigitalDisplay(PHWINFO, U032);
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RM_STATUS EDIDDetect(PHWINFO, U032, U032);
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RM_STATUS edidConstructMobileInfo(PHWINFO, U032, U008 *);
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U032 getI2CPort(PHWINFO, U032, U032 );
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U032 edidGetDDCCaps(PHWINFO);
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#define DDC_RETRIES 3
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#define NUM_DET_TIM 4
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// DDC device address
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#define DDC_CRT_ADR1 0x50
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#define DDC_CRT_ADR2 0x51
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#define DDC_CRT_ADR3 0x53
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// EDID versions
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#define EDID_VERSION_10 0x10
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#define EDID_VERSION_11 0x11
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#define EDID_VERSION_12 0x12
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#define EDID_VERSION_13 0x13
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#define EDID_VERSION_20 0x20
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#define EDID_VERSION_14 0x14 // non-existant, but we should work if this gets added
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// Flags byte, sync polarities (bits 2,1)
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#define VSYNC_POS 1<<2
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#define VSYNC_NEG 0
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#define HSYNC_POS 1<<1
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#define HSYNC_NEG 0
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// EDID Version 1 header defines.
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#define EDID_V1_SIZE 128
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#define EDID_V1_VENDOR_ID_INDEX 0x08
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#define EDID_V1_VERSION_NUMBER_INDEX 0x12
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#define EDID_V1_REVISION_NUMBER_INDEX 0x13
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#define EDID_V1_VIDEO_INPUT_DEF_INDEX 0x14
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#define EDID_V1_FEATURE_SUPPORT_INDEX 0x18
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#define EDID_V1_ESTABLISHED_TIMING_1_INDEX 0x23
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#define EDID_V1_ESTABLISHED_TIMING_2_INDEX 0x24
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#define EDID_V1_ESTABLISHED_TIMING_3_INDEX 0x25
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#define EDID_V1_STANDARD_TIMING_1_INDEX 0x26
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#define EDID_V1_NUM_STANDARD_TIMINGS 0x36-0x26
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#define EDID_ESTABLISHED_TIMING_640x480_ANY 0x38
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#define EDID_ESTABLISHED_TIMING_640x480_60 0x20
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#define EDID_ESTABLISHED_TIMING_640x480_67 0x10
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#define EDID_ESTABLISHED_TIMING_640x480_72 0x08
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#define EDID_ESTABLISHED_TIMING_640x480_75 0x04
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#define EDID_ESTABLISHED_TIMING_800x600_ANY 0xC0
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#define EDID_ESTABLISHED_TIMING_800x600_56 0x02
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#define EDID_ESTABLISHED_TIMING_800x600_60 0x01
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#define EDID_ESTABLISHED_TIMING_800x600_72 0x80
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#define EDID_ESTABLISHED_TIMING_800x600_75 0x40
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#define EDID_ESTABLISHED_TIMING_1024x768_ANY 0x1E
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#define EDID_ESTABLISHED_TIMING_1024x768_87 0x10
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#define EDID_ESTABLISHED_TIMING_1024x768_60 0x08
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#define EDID_ESTABLISHED_TIMING_1024x768_70 0x04
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#define EDID_ESTABLISHED_TIMING_1024x768_75 0x02
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#define EDID_ESTABLISHED_TIMING_1280x1024_75 0x01
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// Standard timings start at bytes index 0x26. Each standard timing is 2 bytes.
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// There are 8 standard timings entries.
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#define EDID_V1_STANDARD_TIMINGS_START_INDEX 0x26
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// Detailed timing section start at index 0x36. Each entry is 18 bytes.
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// There are 4 detailed timing entries.
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#define EDID_V1_DETAILED_TIMINGS_START_INDEX 0x36
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#define EDID_V1_DETAILED_TIMINGS_SIZE 18
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// EDID Version 2 header defines.
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#define EDID_V2_SIZE 256
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#define EDID_V2_VERSION_NUMBER_INDEX 0x0
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#define EDID_V2_DISPLAY_TECHNOLOGY_INDEX 0x4f
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#define DISPLAY_TECHNOLOGY_TYPE_MASK 0xf0
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#define EDID_V2_GTF_SUPPORT_INDEX 0x7d
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#define EDID_V2_TIMING_MAP1_INDEX 0x7e // map of timing info
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#define EDID_V2_TIMING_MAP2_INDEX 0x7f
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#define EDID_V2_TIMING_SECTION_START_INDEX 0x80 // offset 80: start of timing info
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#define EDID_V2_LUM_TABLE_EXIST 0x20 // map bit 5
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#define TRIPLE_LUM_ENTRIES 0x80 // offset 80 bit 7: lum table white (x1) or RGB (x3)
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#define NUM_LUM_ENTRIES 0x1f // size of lum table (x1 or x3)
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#define EDID_V2_FREQ_RANGES 0x1c
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#define EDID_V2_FREQ_RANGE_SHIFT 0x02
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#define EDID_V2_DETAILED_RANGE_LIMITS 0x03
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#define EDID_V2_TIMING_CODES 0xf8
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#define EDID_V2_TIMING_CODES_SHIFT 0x03
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#define EDID_V2_DETAILED_TIMINGS 0x07
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#endif // _EDID_H_
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