146 lines
6.3 KiB
C
146 lines
6.3 KiB
C
#ifndef _MC_H_
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#define _MC_H_
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/***************************************************************************\
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|* *|
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|* Copyright (c) 1993-2000 NVIDIA, Corp. All rights reserved. *|
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|* *|
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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|* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|
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|* the copyright and as design patents pending on the design and *|
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|* interface of the NV chips. Users and possessors of this source *|
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|* code are hereby granted a nonexclusive, royalty-free copyright *|
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|* and design patent license to use this code in individual and *|
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|* commercial software. *|
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|* *|
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|* Any use of this source code must include, in the user documenta- *|
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|* tion and internal comments to the code, notices to the end user *|
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|* as follows: *|
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|* *|
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|* Copyright (c) 1993-2000 NVIDIA, Corp. NVIDIA design patents *|
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|* pending in the U.S. and foreign countries. *|
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|* *|
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|* NVIDIA, CORP. MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF *|
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|* THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT *|
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|* EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORP. DISCLAIMS *|
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|* ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUDING ALL *|
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|* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|
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|* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORP. BE LIABLE *|
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|* FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|
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|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR *|
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|* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER *|
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|* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR *|
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|* PERFORMANCE OF THIS SOURCE CODE. *|
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|* *|
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\***************************************************************************/
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/****************************** Master Control *****************************\
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* *
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* Module: MC.H *
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* Master Exception dispatcher. *
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* *
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*****************************************************************************
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* *
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* History: *
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* *
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\***************************************************************************/
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//---------------------------------------------------------------------------
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//
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// Macros.
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//
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//---------------------------------------------------------------------------
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//
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// Since the hardware ref manuals don't give us macros to decode
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// the PMC_BOOT_0 register, we provide a few here.
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//
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#define MC_GET_MASKREVISION(b0) (b0 & 0x000000FF)
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#define MC_GET_REVISION(b0) ((b0 & 0x000F0000) >> 16)
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#define MC_GET_IMPLEMENTATION(b0) ((b0 & 0x00F00000) >> 20)
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#define MC_GET_ARCHITECTURE(b0) ((b0 & 0xFF000000) >> 20)
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//
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// Architecture constants.
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//
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#define MC_ARCHITECTURE_NV04 0x04
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#define MC_ARCHITECTURE_NV10 0x10
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#define MC_ARCHITECTURE_NV20 0x20
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//
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// Implementation constants.
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// These must be unique within a single architecture.
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//
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#define MC_IMPLEMENTATION_NV04 0x00
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#define MC_IMPLEMENTATION_NV05 0x01
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#define MC_IMPLEMENTATION_NV0A 0x02
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#define MC_IMPLEMENTATION_NV10 0x00
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#define MC_IMPLEMENTATION_NV11 0x01
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#define MC_IMPLEMENTATION_NV15 0x05
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#define MC_IMPLEMENTATION_NV20 0x00
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//
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// MaskRevision constants.
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//
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#define MC_MASK_REVISION_A1 0xA1
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#define MC_MASK_REVISION_A2 0xA2
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#define MC_MASK_REVISION_A3 0xA3
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#define MC_MASK_REVISION_A6 0xA6
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#define MC_MASK_REVISION_B1 0xB1
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#define MC_MASK_REVISION_B2 0xB2
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//
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// Revision constants.
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//
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#define MC_REVISION_0 0x00
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#define MC_REVISION_1 0x01
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#define MC_REVISION_2 0x02
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#define MC_REVISION_3 0x03
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// Return from D3 ACPI state requires a delay before strap register is stable
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#define D0_DELAY_RETRIES 10
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//---------------------------------------------------------------------------
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//
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// Chip ID objects.
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//
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//---------------------------------------------------------------------------
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typedef struct _def_chip_id_object
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{
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OBJECT Base;
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PDMAOBJECT ChipTokenXlate;
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} CHIPIDOBJECT, *PCHIPIDOBJECT;
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//---------------------------------------------------------------------------
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//
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// Function prototypes.
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//
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//---------------------------------------------------------------------------
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RM_STATUS initMc(PHWINFO);
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VOID mcService(PHWINFO);
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RM_STATUS mcPowerStateTrigger(PHWINFO);
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RM_STATUS chpCreateChipID(PCLASSOBJECT, U032, POBJECT *);
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RM_STATUS chpDeleteChipID(POBJECT);
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RM_STATUS mcPowerState(PHWINFO, U032);
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BOOL IsNV4(PHWINFO);
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BOOL IsNV5(PHWINFO);
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BOOL IsNV0A(PHWINFO);
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BOOL IsNV10(PHWINFO);
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BOOL IsNV11(PHWINFO);
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BOOL IsNV15(PHWINFO);
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BOOL IsNV20(PHWINFO);
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BOOL IsNV5orBetter(PHWINFO);
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BOOL IsNV10orBetter(PHWINFO);
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BOOL IsNV10MaskRevA03orBetter(PHWINFO);
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BOOL IsNV15orBetter(PHWINFO);
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BOOL IsNV15MaskRevA01(PHWINFO);
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BOOL IsNV15MaskRevA02(PHWINFO);
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BOOL IsNV15MaskRevA03(PHWINFO);
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BOOL IsNV11orBetter(PHWINFO);
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BOOL IsNV20orBetter(PHWINFO);
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RM_STATUS mcSetBiosRevision(PHWINFO);
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#endif // _MC_H_
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