217 lines
5.7 KiB
C
217 lines
5.7 KiB
C
#ifndef _TV_H_
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#define _TV_H_
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//
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// (C) Copyright NVIDIA Corporation Inc., 1995,1996. All rights reserved.
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//
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/***************************************************************************\
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* *
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* Module: TV.H *
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* The TV flicker filter constants are defined in this module. *
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* *
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*****************************************************************************
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*/
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//---------------------------------------------------------------------------
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//
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// Defines.
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//
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//---------------------------------------------------------------------------
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#define MY_SCALED_IMAGE_CTX 0x97100200
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#define X_RES (640) // source x
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#define Y_RES (480) // source y
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//#define DST_X_RES (640) // destination x
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//#define DST_Y_RES (480) // destination y
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#define DST_X_RES (620) // destination x
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#define DST_Y_RES (420) // destination y
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#define I2C_AUTOINC 0x40 //OR this in to a register to set auto-increment mode.
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// TV mode numbers
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#define TV_MODE_320x200 0
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#define TV_MODE_320x240 1
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#define TV_MODE_320x400 2
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#define TV_MODE_400x300 3
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#define TV_MODE_480x360 4
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#define TV_MODE_512x384 5
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#define TV_MODE_640x400 6
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#define TV_MODE_640x480 7
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#define TV_MODE_800x600 8
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#define TV_MODE_DVD 9 // in NTSC this is 720x480, for PAL this is 704x576 or 720x576
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#define TV_MODE_1024x768 10
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// Brooktree register defs
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// Reg CE = output modes. DAC A = bits 0,1, DAC B = 2,3, etc.
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// Mode 0: Composite
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// Mode 1: Luma delayed composite, Luma, Chroma, Delayed Luma (composite on S-Video connector)
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// Mode 2: S-video (component YUV and delayed LUMA)
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// Mode 3: RGB
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// We use modes 0, 1, and 2
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#define BT_OUT_MUX 0xce // register #
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#define BT_OUT_MUX_A_COMP 0 // values
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#define BT_OUT_MUX_A_ALL 1
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#define BT_OUT_MUX_A_SVID 2
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#define BT_OUT_MUX_B_COMP 0
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#define BT_OUT_MUX_B_ALL 1<<2
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#define BT_OUT_MUX_B_SVID 2<<2
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#define BT_OUT_MUX_C_COMP 0
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#define BT_OUT_MUX_C_ALL 1<<4
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#define BT_OUT_MUX_C_SVID 2<<4
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// Brooktree registers
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#define BT_HS0 0x6E
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#define BT_HS1 0x70
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#define BT_CA0 0xCA
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#define BT_CA1 0xCC
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#define BT_VAL 0x96
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#define BT_FF0 0xC8
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#define BT_FF1 0x34
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#define BT_FF2 0x36
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// Monitor Connection Status
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#define BT_MONSTAT 0xe0
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#define BT_MONSTAT_A 0x80
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#define BT_MONSTAT_B 0x40
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#define BT_MONSTAT_C 0x20
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// DAC enable/check status reg
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#define BT_DAC_CTL 0xBA
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#define BT_DAC_OFF 0x10
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#define BT_DAC_ON 0x00 // normal setting
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#define BT_CHK_STAT 0x40
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#define BT_CHK_OFF 0x00
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#define BT_CONFIG 0xB8
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// Chrontel registers
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#define CH_FF 0x29 // 5:4 = chroma, 3:2 = text, 1:0 = luma
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#define CH_BL 0x7f // 7:0, 90 < x < 208
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#define CH_CE 0x03 // 2:0
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// Init regs struct
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typedef struct
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{
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U008 subaddr; // register address of 1st register in this string
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U008 reg0xC4;
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U008 reg0xC6;
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U008 reg0xC8;
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U008 reg0xCA;
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U008 reg0xCC;
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U008 reg0xCE;
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} BT_INIT_REGS;
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// Modeset regs
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typedef struct
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{
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U008 subaddr; // register address of 1st register in this string
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U008 reg0x76;
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U008 reg0x78;
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U008 reg0x7A;
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U008 reg0x7C;
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U008 reg0x7E;
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U008 reg0x80; // HBLANKO
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U008 reg0x82; // VBLANKO
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U008 reg0x84;
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U008 reg0x86;
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U008 reg0x88;
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U008 reg0x8A;
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U008 reg0x8C;
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U008 reg0x8E;
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U008 reg0x90;
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U008 reg0x92; // VBLANKI
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U008 reg0x94;
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U008 reg0x96;
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U008 reg0x98; // VSCALE
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U008 reg0x9A; // HBLANKO
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U008 reg0x9C;
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U008 reg0x9E;
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U008 reg0xA0;
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U008 reg0xA2;
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U008 reg0xA4;
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U008 reg0xA6;
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U008 reg0xA8;
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U008 reg0xAA;
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U008 reg0xAC;
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U008 reg0xAE;
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U008 reg0xB0;
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U008 reg0xB2;
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U008 reg0xB4;
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U008 reg0xB6;
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} BT_MODE_REGS;
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// Position regs
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typedef struct
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{
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U008 reg0x6E;
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U008 reg0x70;
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U008 reg0x72;
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U008 reg0x74;
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} BT_POS_REGS;
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// Chrontel encoder mode set struct
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typedef struct
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{
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U008 reg0x00;
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U008 reg0x07;
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U008 reg0x0a;
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U008 reg0x0b;
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U008 reg0x13;
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U008 reg0x14;
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U008 reg0x15;
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} CH_MODE_REGS;
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// Chrontel mode registers - bit 7 should always be set
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#define CH_REG_00 0x00 | 0x80
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#define CH_REG_01 0x01 | 0x80
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#define CH_REG_03 0x03 | 0x80
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#define CH_REG_04 0x04 | 0x80
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#define CH_REG_06 0x06 | 0x80
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#define CH_REG_07 0x07 | 0x80
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#define CH_REG_08 0x08 | 0x80
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#define CH_REG_09 0x09 | 0x80
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#define CH_REG_0A 0x0A | 0x80
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#define CH_REG_0B 0x0B | 0x80
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#define CH_REG_0D 0x0D | 0x80
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#define CH_REG_0E 0x0E | 0x80
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#define CH_REG_10 0x10 | 0x80
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#define CH_REG_11 0x11 | 0x80
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#define CH_REG_13 0x13 | 0x80
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#define CH_REG_18 0x18 | 0x80
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#define CH_REG_19 0x19 | 0x80
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#define CH_REG_1A 0x1A | 0x80
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#define CH_REG_1B 0x1B | 0x80
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#define CH_REG_1C 0x1C | 0x80
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#define CH_REG_1D 0x1D | 0x80
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#define CH_REG_1E 0x1E | 0x80
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#define CH_REG_1F 0x1F | 0x80
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#define CH_REG_21 0x21 | 0x80
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#define CH_REG_3D 0x3D | 0x80
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// DAC PM control
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#define CH_ON 0x0B
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#define CH_OFF 0x09
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// TV standard specified in reg 0 bits 4:3
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#define CH_NTSC_M 0x00
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#define CH_NTSC_J 0x18
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#define CH_PAL_M 0x10
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#define CH_PAL_OTHER 0x08
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// NTSC-J wants different blackness level
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// Range is 0x5A - 0xD0. Default is 7F.
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// Recommended: NTSC-M & PAL-M 7F, NTSC-J 0x64, PAL 0x69
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#define CH_BL_J 0x64
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#define CH_BL_M 0x7f
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#define CH_REG_06_DEF 0x10 // MCP set: latch data on positive edge
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#define CH_CFR 0x80
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#define CH_GAIN 0xBF // mask gain bit
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#define CH_GAIN_NTSC 0x00 // NTSC-M & PAL-M
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#define CH_GAIN_PAL 0x40 // PAL & NTSC-J
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#define PH_CHIP_ID 0x1C
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#define PH_STDCTL 0x61
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#define PH_DAC_POWER 0x40
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#define PH_DAC_OFF 0x40
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#define PH_DAC_ON 0x00
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#endif // _TV_H#
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