83 lines
1.6 KiB
PHP
83 lines
1.6 KiB
PHP
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; initialize DRAM using SDRAM Control Register
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;
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; setup PCI cycle to 76h
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mov eax, 080000074h
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mov dx, 0CFEh
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; NOP Command Enable
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mov al, 20h
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out dx, al
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mov cx, -1
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@@: loop @B
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; All Banks Precharge Enable
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mov al, 40h
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out dx, al
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mov ebx, ds:[0]
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mov cx, 1000h
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@@: loop @B
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; CBR Enable Command
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mov al, 80h
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out dx, al
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mov cx, 8
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CBRLoop:
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mov ebx, ds:[0]
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loop CBRLoop
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; Mode Register Set Enable Command
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mov al, 60h
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out dx, al
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;mov di, 01F0h ;MKF_CL2_ADDRESS_FOR_MAA;CL2 address for Rows 3:0
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;mov di, 0FEA8h ; MKF_CL2_ADDRESS_FOR_MAB; No, get correct address
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;mov di, 01D0h ; CL3
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mov di, 0DE28h
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mov ebx, ds:[di]
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; Normal SDRAM Operation
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mov al, 0h
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out dx, al
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mov ebx, ds:[0]
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;
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; initialize chipset registers
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;
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xor si, si
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xor bx, bx
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RAMInitLoop:
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mov bl, cs:BYTE PTR RAMInitData[si]
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cmp bl, 0
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je RAMInitDone
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mov eax, 080000000h
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mov al, bl
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mov dx, 0CF8h
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inc si
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out dx, eax
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mov dx, 0CFCh
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mov ax, bx
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mov eax, cs:DWORD PTR RAMInitData[si]
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out dx, eax
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add si, 4
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jmp RAMInitLoop
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RAMInitDone:
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