502 lines
18 KiB
PHP
502 lines
18 KiB
PHP
;++
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;
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; Copyright (c) Microsoft Corporation. All rights reserved
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;
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; Module Name:
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;
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; cr11init.inc
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;
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; Abstract:
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;
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; Crush11 initialization table
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;
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; This module contains table of commands used by South Bridge to initialize
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; hardware and test memory during boot startup. For definition of each
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; command, please see initcode.inc and command.inc
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;--
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page 84,132
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.MODEL compact
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.486p
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DATA_TABLE_OFFSET EQU 0FFFFFE00h
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INCLUDE command.inc
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CODE SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:CODE, ES:NOTHING, SS:NOTHING
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ORG 0000H
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IFDEF OLDNBDATA
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;
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; NB data for Crush 11 on the emulator
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;
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dd 2B16D065h
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dd (1 + (1 SHL 2)) ; Intel
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dd 0
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dd 7 SHL 28
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dd 11 SHL 28
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dd 0
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dd 0
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dd 0
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dd 0
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dd 0FFFFFF7Fh
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dd 0FFFFFFFFh
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dd (28-11) dup (0h)
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dd 0Fh
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dd 00000000h ; Intel
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dd 0
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dd 0
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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dd 19234121h, 25268001h, 19234121h, 25268001h
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ELSE
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IFDEF FIRST_TRY
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;
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; NB data for Crush 11 on the EVT boards
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;
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db 065h, 0D0h, 016h, 02Bh ; 2B16D065
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db 04Dh, 043h, 046h, 033h ; 3346434D
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db 003h, 003h, 003h, 003h ; 03030303
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db 00Eh, 015h, 01Ch, 01Ch ; 1C1C150E
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db 003h, 015h, 000h, 000h ; 00001503
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db 08Ah, 070h, 0E4h, 0A8h ; A8E4708A
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db 030h, 002h, 0FDh, 045h ; 45FD0230
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db 001h, 000h, 0E2h, 010h ; 10E20001
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db 000h, 000h, 000h, 0F0h ; F0000000
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dd (55) dup (0FFFFFFFFh) ; FFFFFFFF, ETC
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ELSE
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;
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; NB data for Crush 11 on the EVT boards
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;
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dd 2B16D065h
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dd 4444444Dh ; Intel
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dd 03030303h
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dd 15151515h
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dd 1503h
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dd 0A8E4708Ah
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dd 45FD0230h
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dd 10E20001h
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dd 0F0000000h
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dd 0FFFFFFFFh
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dd 0FFFFFFFFh
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dd (28-11) dup (0h) ; 4 DWORD follow to fill up to 128 bytes
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;
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; SB data for MCP1 on the EVT boards
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;
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dd 0Fh
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dd 00000000h ; Intel
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dd 0 ; pad for DWORD 30
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dd 0 ; pad for DWORD 31 (32*4 = byte location 128)
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;
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; Force 256 byte alignment.
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;
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db (080h) dup (0) ; dup 0's into remaining 0x80/128 bytes
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ENDIF ; FIRST_TRY
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ENDIF ; OLDNBDATA
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ORG 0100h
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data_table_test LABEL BYTE
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;c00 nv_command_struct <COMMAND_TIMING_DELAY , 5 , DONT_CARE >
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;c01 nv_command_struct <COMMAND_READ_MEM, 050000000h, DONT_CARE >
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;c02 nv_command_struct <COMMAND_WRITE_MEM, 050000000h, 55aa55aah >
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;c04 nv_command_struct <COMMAND_PCI_CFG_WRITE, 80000004h, 7 >
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;c05 nv_command_struct <COMMAND_PCI_CFG_READ, 80000004h, DONT_CARE >
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;c06 nv_command_struct <COMMAND_RMW_RESULT, 5, 00007700h >
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;c07 nv_command_struct <COMMAND_USE_RESULT_AS_DATA, COMMAND_PCI_CFG_WRITE, 80000004h >
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;
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; Crush11 init sequence.
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;
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 8000017Ch, 170F17C0h > ; CR_CMC_CFG0, 0x170f17c0 | CR_CMC_CFG0_PART_INTLV_32B = 0
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000164h, 00000001h > ; CR_CMC_NVM, 0x1
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000240h, 00110401h > ; CR_XL_DIMM_CFG_0, 0x1 | 0x10000 | 0x100000 | 0x0 | 0x400 = 0x110401
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000170h, 00000038h > ; CR_CMC_MEMIO_CFG0, 0x38
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000190h, 22228807h > ; CR_CMC_TIMING0, 0x22228807
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000194h, 22452250h > ; CR_CMC_TIMING1, 0x22452250
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000198h, 036900FFh > ; CR_CMC_TIMING2, 0x032100FF / 0x036900FF
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000178h, 0100021Fh > ; CR_CMC_MEMIO_CFG2, 0x0100021F
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 8000019Ch, 00000020h > ; CR_CMC_ARB_PREDIVIDER, 0x20
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001C0h, 00000013h > ; CR_CMC_ARB, 0x13
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001CCh, 00028880h > ; CR_CMC_ARB_TIMEOUT, 0x28880
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001D0h, 00004C40h > ; CR_CMC_ARB_XFER_SZ, 0x4C40
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001D4h, 00002220h > ; CR_CMC_ARB_XFER_REM, 0x2220
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001D8h, 0000000Ch > ; CR_CMC_ARB_DIFF_BANK, 0xC
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001DCh, 0000000Fh > ; CR_CMC_CLOSE_PAGE0, 0xF
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001E0h, 0000000Bh > ; CR_CMC_CLOSE_PAGE1, 0xB
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001E4h, 000001CFh > ; CR_CMC_CLOSE_PAGE2, 0x1CF
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001ECh, 00000F31h > ; CR_CMC_AUTOCLOSE, 0xF31
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001F0h, 11001018h > ; CR_CMC_WBC, 0x11001018
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001F8h, 00000401h > ; CR_CMC_CPU_RRQ, 0x401
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001FCh, 02750031h > ; CR_CMC_BYPASS, 0x2750031
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000168h, 00000001h > ; CR_CMC_PIN, 0x1
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 8000016Ch, 00000001h > ; CR_CMC_PAD, 0x1
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001E8h, 24924488h > ; CR_CMC_CMDQ, 0x24924488
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001F4h, 00001008h > ; CR_CMC_CMDQ_PRT, 0x1008
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001c8h, 00000001h > ; CR_CMC_PRE, 0x1
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;.repeat
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; in eax,dx
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; not eax
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;.until eax & 1
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001a0h, 8000002Ah > ; CR_CMC_MRS_DIMM0, 0x8000002A
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;.repeat
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; in eax,dx
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; not eax
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;.until eax & 80000000h
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001a4h, 80200001h > ; CR_CMC_EMRS_DIMM0, 0x80200001
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;.repeat
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; in eax,dx
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; not eax
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;.until eax & 80000000h
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001c8h, 00000001h > ; CR_CMC_PRE, 0x1
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;.repeat
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; in eax,dx
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; not eax
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;.until eax & 1
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; do 8 memory refresh cycles:
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 800001c4h, 00000001h > ; CR_CMC_REF, 0x1
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;.repeat
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; in eax,dx
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; not eax
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;.until eax & 1
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000168h, 00000001h > ; CR_CMC_PIN, 0x1
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000160h, 80000000h > ; CR_CMC_REFCTRL, 0x80000000
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nv_command_struct< COMMAND_PCI_CFG_WRITE, 80000084h, 03000000h > ; CR_CPU_MEMTOP, 0x3000000 = 64MB limit (as a RMW, reads as 0x3FFFFFF)
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IFDEF MEMTEST
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;
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; Memory test
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;
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nv_command_struct< COMMAND_RMW_ACCUM, 0, 0 > ; clear accumulator
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;
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; dram0 chip
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;
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dram0_begin:
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MemBase = 0
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MemChip = 0
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram0_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram0_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram0_2MB-$-4) > ; if edi != val, jump
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dram0_4mb:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram0_end-$-4) >
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dram0_2mb:
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram0_end-$-4) >
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dram0_err:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
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dram0_end:
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;
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; dram1 chip
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;
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dram1_begin:
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MemBase = 010h
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MemChip = 1
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram1_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE> ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram1_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram1_2MB-$-4) > ; if edi != val, jump
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dram1_4mb:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram1_end-$-4) >
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dram1_2mb:
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram1_end-$-4) >
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dram1_err:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
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dram1_end:
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;
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; dram2 chip
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;
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dram2_begin:
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MemBase = 020h
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MemChip = 2
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram2_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram2_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram2_2MB-$-4)> ; if edi != val, jump
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dram2_4mb:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram2_end-$-4) >
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dram2_2mb:
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram2_end-$-4) >
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dram2_err:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
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dram2_end:
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;
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; dram3 chip
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;
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dram3_begin:
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MemBase = 030h
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MemChip = 3
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram3_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram3_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram3_2MB-$-4) > ; if edi != val, jump
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dram3_4mb:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram3_end-$-4) >
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dram3_2mb:
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram3_end-$-4) >
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dram3_err:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
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dram3_end:
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;
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; dram4 chip
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;
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dram4_begin:
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MemBase = 04000000h
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MemChip = 4
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram4_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram4_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram4_2MB-$-4) > ; if edi != val, jump
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dram4_4mb:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram4_end-$-4) >
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dram4_2mb:
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nv_command_struct< COMMAND_JMP, DONT_CARE, (dram4_end-$-4) >
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dram4_err:
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nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
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dram4_end:
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;
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; dram5 chip
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;
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dram5_begin:
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MemBase = 04000010h
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MemChip = 5
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
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nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram5_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
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nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram5_err-$-4) > ; if edi != val, jump
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nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram5_2MB-$-4) > ; if edi != val, jump
|
|
|
|
dram5_4mb:
|
|
nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
|
|
nv_command_struct< COMMAND_JMP, DONT_CARE, (dram5_end-$-4) >
|
|
|
|
dram5_2mb:
|
|
nv_command_struct< COMMAND_JMP, DONT_CARE, (dram5_end-$-4) >
|
|
|
|
dram5_err:
|
|
nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
|
|
|
|
dram5_end:
|
|
|
|
;
|
|
; dram6 chip
|
|
;
|
|
|
|
dram6_begin:
|
|
|
|
MemBase = 04000020h
|
|
MemChip = 6
|
|
|
|
nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
|
|
nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
|
|
nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
|
|
|
|
nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram6_err-$-4) > ; if edi != val, jump
|
|
|
|
nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram6_err-$-4) > ; if edi != val, jump
|
|
|
|
nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram6_2MB-$-4) > ; if edi != val, jump
|
|
|
|
dram6_4mb:
|
|
nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
|
|
nv_command_struct< COMMAND_JMP, DONT_CARE, (dram6_end-$-4) >
|
|
|
|
dram6_2mb:
|
|
nv_command_struct< COMMAND_JMP, DONT_CARE, (dram6_end-$-4) >
|
|
|
|
dram6_err:
|
|
nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
|
|
|
|
dram6_end:
|
|
|
|
;
|
|
; dram7 chip
|
|
;
|
|
|
|
dram7_begin:
|
|
|
|
MemBase = 04000030h
|
|
MemChip = 7
|
|
|
|
nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 002555558h), 05A5A5A5Ah >
|
|
nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 000555554h), 0FFFFFFFFh >
|
|
nv_command_struct< COMMAND_WRITE_MEM, (MemBase + 00055555Ch), 0FFFFFFFFh >
|
|
|
|
nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 05A5A5A5Ah, (dram7_err-$-4) > ; if edi != val, jump
|
|
|
|
nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555554h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0FFFFFFFFh, (dram7_err-$-4) > ; if edi != val, jump
|
|
|
|
nv_command_struct< COMMAND_READ_MEM, (MemBase + 002555558h), DONT_CARE > ; read mem in edi
|
|
nv_command_struct< COMMAND_COMPARE_RESULT_JNE, 0A5A5A5A5h, (dram7_2MB-$-4) > ; if edi != val, jump
|
|
|
|
dram7_4mb:
|
|
nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) > ; indicate 4mb for this chip
|
|
nv_command_struct< COMMAND_JMP, DONT_CARE, (dram7_end-$-4) >
|
|
|
|
dram7_2mb:
|
|
nv_command_struct< COMMAND_JMP, DONT_CARE, (dram7_end-$-4) >
|
|
|
|
dram7_err:
|
|
nv_command_struct< COMMAND_RMW_ACCUM, 0FFFFFFFFh, (1 shl MemChip) shl 8 > ; indicate error for this chip
|
|
|
|
dram7_end:
|
|
|
|
ENDIF
|
|
|
|
;
|
|
; End of table
|
|
;
|
|
|
|
nv_command_struct < COMMAND_QUIT, DONT_CARE, DONT_CARE >
|
|
|
|
ORG 07FFh ; 0FFFFh
|
|
|
|
db 00h
|
|
|
|
CODE ENDS
|
|
|
|
|