669 lines
19 KiB
C
669 lines
19 KiB
C
/*++
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Copyright (c) 2000-2002 Microsoft Corporation
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Module Name:
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idex.h
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Abstract:
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This module contains the private data structures and procedure prototypes
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for the IDE port driver.
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--*/
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#ifndef _IDEX_
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#define _IDEX_
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#include <ntos.h>
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#include <pci.h>
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#include <ldr.h>
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#include <scsi.h>
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#include <ntddcdrm.h>
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#include <ntddcdvd.h>
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#include <ntdddisk.h>
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#include <ntddscsi.h>
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#include <idexchan.h>
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#include <xcrypt.h>
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#include <dvdx2.h>
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#include <xdisk.h>
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#include <smcdef.h>
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#include <xconfig.h>
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#include <segalpc.h>
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#include <stdio.h>
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#include <conio.h>
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#include <limits.h>
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#include <pshpack4.h>
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//
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// Enforce a hard limit of XDISK_FIXED_SECTOR_COUNT hard disk sectors when the
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// following is defined.
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//
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#define IDEX_DISK_FIXED_SECTOR_COUNT
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//
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// DBG sensitive DbgPrint and DbgBreakPoint wrappers.
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//
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#if DBG
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#define IdexDbgPrint(x) DbgPrint x
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#define IdexDbgBreakPoint() DbgBreakPoint()
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#else
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#define IdexDbgPrint(x)
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#define IdexDbgBreakPoint()
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#endif
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//
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// Bit flag macros.
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//
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#define IdexIsFlagSet(flagset, flag) (((flagset) & (flag)) != 0)
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#define IdexIsFlagClear(flagset, flag) (((flagset) & (flag)) == 0)
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//
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// Bug check module codes.
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//
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#define IDE_BUG_CHECK_CDROM (0x00010000)
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#define IDE_BUG_CHECK_CHANNEL (0x00020000)
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#define IDE_BUG_CHECK_DISK (0x00030000)
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#define IDE_BUG_CHECK_DRIVER (0x00040000)
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#define IDE_BUG_CHECK_MEDIA_BOARD (0x00050000)
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//
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// Define the number of times that an operation will be retried after a device
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// error is detected or after a timeout occurs. For all of the above IRP codes,
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// the retry count is placed in Argument4 of the IRP stack.
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//
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#define IDE_NO_RETRY_COUNT 0
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#define IDE_NORMAL_RETRY_COUNT 4
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//
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// Define the timeouts in seconds for various IDE operations.
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//
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#define IDE_ATA_DEFAULT_TIMEOUT 10
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#define IDE_ATA_FLUSH_TIMEOUT 30
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#define IDE_ATAPI_DEFAULT_TIMEOUT 12
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//
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// Define the timer periods in milliseconds for various states of IRP handling.
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//
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#define IDE_SLOW_TIMER_PERIOD 1000
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#define IDE_FAST_TIMER_PERIOD 100
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//
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// Macros to synchronize execution with the interrupt service routine. The
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// proper way to handle this is via KeSynchronizeExecution, but we can generate
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// smaller code by raising and lowering the interrupt IRQL ourselves.
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//
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#define IdexRaiseIrqlToChannelDIRQL(oldirql) \
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KeRaiseIrql(IdexChannelObject.InterruptIrql, (oldirql))
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#define IdexRaiseIrqlToChannelDIRQLFromDPCLevel() { \
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ASSERT(KeGetCurrentIrql() == DISPATCH_LEVEL); \
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KfRaiseIrql(IdexChannelObject.InterruptIrql); \
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}
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#define IdexLowerIrqlFromChannelDIRQL(oldirql) \
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KeLowerIrql(oldirql);
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#define IdexAssertIrqlAtChannelDIRQL() \
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ASSERT(KeGetCurrentIrql() == IdexChannelObject.InterruptIrql)
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//
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// Macros to wrap the indirection of routines through the channel object.
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//
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#define IdexChannelStartPacket(device, irp) \
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IdexChannelObject.StartPacketRoutine(device, irp)
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#define IdexChannelStartNextPacket() \
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IdexChannelObject.StartNextPacketRoutine()
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//
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// Disk device extension data.
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//
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typedef struct _IDE_DISK_EXTENSION {
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PDEVICE_OBJECT DeviceObject;
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PARTITION_INFORMATION PartitionInformation;
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} IDE_DISK_EXTENSION, *PIDE_DISK_EXTENSION;
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//
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// Media board device extension data.
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//
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typedef struct _IDE_MEDIA_BOARD_EXTENSION {
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PDEVICE_OBJECT DeviceObject;
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PARTITION_INFORMATION PartitionInformation;
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} IDE_MEDIA_BOARD_EXTENSION, *PIDE_MEDIA_BOARD_EXTENSION;
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//
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// Define the default device numbers for the various IDE devices.
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//
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#define IDE_DISK_DEVICE_NUMBER 0
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#define IDE_CDROM_DEVICE_NUMBER 1
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#define IDE_MEDIA_BOARD_DEVICE_NUMBER 1
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//
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// Define the PCI resource for the bus master interface.
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//
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#define IDE_PCI_BUS_MASTER_BASE XPCICFG_IDE_IO_REGISTER_BASE_4
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#define IDE_PCI_BUS_MASTER_BMICP (IDE_PCI_BUS_MASTER_BASE + 0x0)
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#define IDE_PCI_BUS_MASTER_BMISP (IDE_PCI_BUS_MASTER_BASE + 0x2)
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#define IDE_PCI_BUS_MASTER_BMIDP (IDE_PCI_BUS_MASTER_BASE + 0x4)
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#define IDE_PCI_BUS_MASTER_BMICS (IDE_PCI_BUS_MASTER_BASE + 0x8)
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#define IDE_PCI_BUS_MASTER_BMISS (IDE_PCI_BUS_MASTER_BASE + 0xA)
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#define IDE_PCI_BUS_MASTER_BMIDS (IDE_PCI_BUS_MASTER_BASE + 0xC)
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//
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// Define the legacy ISA resources for single IDE channel support.
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//
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#define IDE_CHANNEL_COMMAND_BASE 0x01F0
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#define IDE_CHANNEL_CONTROL_BASE 0x03F4
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#define IDE_CHANNEL_IRQ_RESOURCE 14
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//
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// Macros to compute the IDE registers for an IDE channel. These macros allow
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// us to expand to multiple channels in the future.
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//
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#define IDE_DATA_REGISTER (IDE_CHANNEL_COMMAND_BASE + 0)
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#define IDE_ERROR_REGISTER (IDE_CHANNEL_COMMAND_BASE + 1)
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#define IDE_SECTOR_COUNT_REGISTER (IDE_CHANNEL_COMMAND_BASE + 2)
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#define IDE_SECTOR_NUMBER_REGISTER (IDE_CHANNEL_COMMAND_BASE + 3)
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#define IDE_CYLINDER_LOW_REGISTER (IDE_CHANNEL_COMMAND_BASE + 4)
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#define IDE_CYLINDER_HIGH_REGISTER (IDE_CHANNEL_COMMAND_BASE + 5)
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#define IDE_DEVICE_SELECT_REGISTER (IDE_CHANNEL_COMMAND_BASE + 6)
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#define IDE_STATUS_REGISTER (IDE_CHANNEL_COMMAND_BASE + 7)
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#define IDE_COMMAND_REGISTER (IDE_CHANNEL_COMMAND_BASE + 7)
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#define IDE_ALTERNATE_STATUS_REGISTER (IDE_CHANNEL_CONTROL_BASE + 2)
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#define IDE_DEVICE_CONTROL_REGISTER (IDE_CHANNEL_CONTROL_BASE + 2)
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//
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// Macros to read and write from the IDE registers. These macros allow us to
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// hook the reads and writes to the registers on an individual basis.
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//
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#define IdexReadDataPortUchar() \
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IdexReadPortUchar(IDE_DATA_REGISTER)
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#define IdexWriteDataPortUchar(data) \
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IdexWritePortUchar(IDE_DATA_REGISTER, (data))
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#define IdexReadDataPortUshort() \
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IdexReadPortUshort(IDE_DATA_REGISTER)
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#define IdexReadDataPortBufferUshort(buffer, count) \
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IdexReadPortBufferUshort(IDE_DATA_REGISTER, (buffer), (count))
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#define IdexWriteDataPortBufferUshort(buffer, count) \
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IdexWritePortBufferUshort(IDE_DATA_REGISTER, (buffer), (count))
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#define IdexReadDataPortBufferUlong(buffer, count) \
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IdexReadPortBufferUlong(IDE_DATA_REGISTER, (buffer), (count))
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#define IdexWriteDataPortBufferUlong(buffer, count) \
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IdexWritePortBufferUlong(IDE_DATA_REGISTER, (buffer), (count))
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#define IdexReadErrorPort() \
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IdexReadPortUchar(IDE_ERROR_REGISTER)
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#define IdexReadSectorCountPort() \
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IdexReadPortUchar(IDE_SECTOR_COUNT_REGISTER)
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#define IdexWriteSectorCountPort(data) \
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IdexWritePortUchar(IDE_SECTOR_COUNT_REGISTER, (data))
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#define IdexReadSectorNumberPort() \
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IdexReadPortUchar(IDE_SECTOR_NUMBER_REGISTER)
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#define IdexWriteSectorNumberPort(data) \
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IdexWritePortUchar(IDE_SECTOR_NUMBER_REGISTER, (data))
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#define IdexReadCylinderLowPort() \
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IdexReadPortUchar(IDE_CYLINDER_LOW_REGISTER)
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#define IdexWriteCylinderLowPort(data) \
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IdexWritePortUchar(IDE_CYLINDER_LOW_REGISTER, (data))
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#define IdexReadCylinderHighPort() \
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IdexReadPortUchar(IDE_CYLINDER_HIGH_REGISTER)
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#define IdexWriteCylinderHighPort(data) \
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IdexWritePortUchar(IDE_CYLINDER_HIGH_REGISTER, (data))
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#define IdexReadDeviceSelectPort() \
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IdexReadPortUchar(IDE_DEVICE_SELECT_REGISTER)
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#define IdexWriteDeviceSelectPort(data) \
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IdexWritePortUchar(IDE_DEVICE_SELECT_REGISTER, (data))
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#define IdexReadStatusPort() \
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IdexReadPortUchar(IDE_STATUS_REGISTER)
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#define IdexWriteCommandPort(data) \
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IdexWritePortUchar(IDE_COMMAND_REGISTER, (data))
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#define IdexReadAlternateStatusPort() \
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IdexReadPortUchar(IDE_ALTERNATE_STATUS_REGISTER)
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#define IdexWriteDeviceControlPort(data) \
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IdexWritePortUchar(IDE_DEVICE_CONTROL_REGISTER, (data))
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//
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// Macros to access the IDE registers using the ATAPI register names.
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//
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#define IdexWriteFeaturesPort(data) \
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IdexWritePortUchar(IDE_ERROR_REGISTER, (data))
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#define IdexReadInterruptReasonPort IdexReadSectorCountPort
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#define IdexReadByteCountLowPort IdexReadCylinderLowPort
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#define IdexWriteByteCountLowPort IdexWriteCylinderLowPort
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#define IdexReadByteCountHighPort IdexReadCylinderHighPort
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#define IdexWriteByteCountHighPort IdexWriteCylinderHighPort
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//
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// Macros to access the IDE registers from a more abstract level.
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//
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#define IdexProgramTargetDevice(device) \
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IdexWriteDeviceSelectPort((UCHAR)(0xA0 | ((device) << 4)))
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#define IdexProgramTargetDeviceWithData(device, data) \
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IdexWriteDeviceSelectPort((UCHAR)(0xA0 | ((device) << 4) | ((data) & 0xF)))
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#define IdexProgramLBATransfer(device, sector, count) { \
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IdexWriteDeviceSelectPort((UCHAR)(0xE0 | ((device) << 4) | \
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(((sector) & 0xF000000) >> 24))); \
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IdexWriteSectorNumberPort((UCHAR)(((sector) & 0xFF) >> 0)); \
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IdexWriteCylinderLowPort((UCHAR)(((sector) & 0xFF00) >> 8)); \
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IdexWriteCylinderHighPort((UCHAR)(((sector) & 0xFF0000) >> 16)); \
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IdexWriteSectorCountPort((UCHAR)(count)); \
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}
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#define IdexWriteDataPortCdb(cdb) \
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IdexWriteDataPortBufferUlong((PULONG)(cdb), 3);
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//
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// Define the IDE status register flags.
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//
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#define IDE_STATUS_ERR ((UCHAR)0x01)
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#define IDE_STATUS_DRQ ((UCHAR)0x08)
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#define IDE_STATUS_DRDY ((UCHAR)0x40)
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#define IDE_STATUS_BSY ((UCHAR)0x80)
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//
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// Define the IDE device control register flags.
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//
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#define IDE_DEVICE_CONTROL_NIEN ((UCHAR)0x02)
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#define IDE_DEVICE_CONTROL_SRST ((UCHAR)0x04)
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//
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// Define the IDE command values.
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//
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#define IDE_COMMAND_DEVICE_RESET ((UCHAR)0x08)
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#define IDE_COMMAND_READ_SECTORS ((UCHAR)0x20)
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#define IDE_COMMAND_WRITE_SECTORS ((UCHAR)0x30)
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#define IDE_COMMAND_VERIFY ((UCHAR)0x40)
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#define IDE_COMMAND_SET_DEVICE_PARAMETERS ((UCHAR)0x91)
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#define IDE_COMMAND_PACKET ((UCHAR)0xA0)
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#define IDE_COMMAND_IDENTIFY_PACKET_DEVICE ((UCHAR)0xA1)
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#define IDE_COMMAND_READ_MULTIPLE ((UCHAR)0xC4)
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#define IDE_COMMAND_WRITE_MULTIPLE ((UCHAR)0xC5)
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#define IDE_COMMAND_SET_MULTIPLE_MODE ((UCHAR)0xC6)
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#define IDE_COMMAND_READ_DMA ((UCHAR)0xC8)
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#define IDE_COMMAND_WRITE_DMA ((UCHAR)0xCA)
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#define IDE_COMMAND_STANDBY_IMMEDIATE ((UCHAR)0xE0)
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#define IDE_COMMAND_FLUSH_CACHE ((UCHAR)0xE7)
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#define IDE_COMMAND_IDENTIFY_DEVICE ((UCHAR)0xEC)
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#define IDE_COMMAND_SET_FEATURES ((UCHAR)0xEF)
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#define IDE_COMMAND_SECURITY_SET_PASSWORD ((UCHAR)0xF1)
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#define IDE_COMMAND_SECURITY_UNLOCK ((UCHAR)0xF2)
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#define IDE_COMMAND_SECURITY_DISABLE_PASSWORD ((UCHAR)0xF6)
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//
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// Define the IDE feature values for an ATA device.
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//
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#define IDE_FEATURE_SET_TRANSFER_MODE ((UCHAR)0x03)
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//
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// Define the IDE feature flags for an ATAPI device.
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//
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#define IDE_FEATURE_DMA ((UCHAR)0x01)
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#define IDE_FEATURE_OVL ((UCHAR)0x02)
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//
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// Define the IDE interrupt reason flags for an ATAPI device.
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//
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#define IDE_INTERRUPT_REASON_CD ((UCHAR)0x01)
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#define IDE_INTERRUPT_REASON_IO ((UCHAR)0x02)
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//
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// Define the data transfer values for an ATA device.
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//
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#define IDE_ATA_SECTOR_SHIFT 9
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#define IDE_ATA_SECTOR_SIZE (1 << IDE_ATA_SECTOR_SHIFT)
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#define IDE_ATA_SECTOR_MASK (IDE_ATA_SECTOR_SIZE - 1)
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#define IDE_ATA_MAXIMUM_TRANSFER_SECTORS 256
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#define IDE_ATA_MAXIMUM_TRANSFER_BYTES (IDE_ATA_MAXIMUM_TRANSFER_SECTORS * IDE_ATA_SECTOR_SIZE)
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#define IDE_ATA_MAXIMUM_TRANSFER_PAGES (IDE_ATA_MAXIMUM_TRANSFER_BYTES >> PAGE_SHIFT)
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//
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// Define the data transfer values for an ATAPI device.
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//
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#define IDE_ATAPI_CD_SECTOR_SHIFT 11
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#define IDE_ATAPI_CD_SECTOR_SIZE (1 << IDE_ATAPI_CD_SECTOR_SHIFT)
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#define IDE_ATAPI_CD_SECTOR_MASK (IDE_ATAPI_CD_SECTOR_SIZE - 1)
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#define IDE_ATAPI_CD_MAXIMUM_TRANSFER_SECTORS 64
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#define IDE_ATAPI_RAW_CD_SECTOR_SIZE 2352
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#define IDE_ATAPI_MAXIMUM_TRANSFER_BYTES (IDE_ATAPI_CD_MAXIMUM_TRANSFER_SECTORS * IDE_ATAPI_CD_SECTOR_SIZE)
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#define IDE_ATAPI_MAXIMUM_TRANSFER_PAGES (IDE_ATAPI_MAXIMUM_TRANSFER_BYTES >> PAGE_SHIFT)
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//
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// Define the transfer modes for the set transfer mode feature.
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//
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#define IDE_TRANSFER_MODE_PIO ((UCHAR)0x00)
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#define IDE_TRANSFER_MODE_PIO_NO_IORDY ((UCHAR)0x01)
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#define IDE_TRANSFER_MODE_PIO_MODE_3 ((UCHAR)0x0B)
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#define IDE_TRANSFER_MODE_PIO_MODE_4 ((UCHAR)0x0C)
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#define IDE_TRANSFER_MODE_MWDMA_MODE_0 ((UCHAR)0x20)
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#define IDE_TRANSFER_MODE_MWDMA_MODE_1 ((UCHAR)0x21)
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#define IDE_TRANSFER_MODE_MWDMA_MODE_2 ((UCHAR)0x22)
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#define IDE_TRANSFER_MODE_UDMA_MODE_0 ((UCHAR)0x40)
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#define IDE_TRANSFER_MODE_UDMA_MODE_1 ((UCHAR)0x41)
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#define IDE_TRANSFER_MODE_UDMA_MODE_2 ((UCHAR)0x42)
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#define IDE_TRANSFER_MODE_UDMA_MODE_3 ((UCHAR)0x43)
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#define IDE_TRANSFER_MODE_UDMA_MODE_4 ((UCHAR)0x44)
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#define IDE_TRANSFER_MODE_UDMA_MODE_5 ((UCHAR)0x45)
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//
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// Define the number of bytes in a password buffer for an ATA device.
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//
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#define IDE_ATA_PASSWORD_LENGTH 32
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//
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// Define the data buffer alignment requirements for a DMA bus master operation.
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//
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#define IDE_ALIGNMENT_REQUIREMENT FILE_WORD_ALIGNMENT
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//
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// Macros to read and write from the PCI bus master interface.
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//
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#define IdexReadBusMasterCommandPort(channel) \
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IdexReadPortUchar(IDE_PCI_BUS_MASTER_BMICP)
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#define IdexWriteBusMasterCommandPort(data) \
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IdexWritePortUchar(IDE_PCI_BUS_MASTER_BMICP, (data))
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#define IdexReadBusMasterStatusPort() \
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IdexReadPortUchar(IDE_PCI_BUS_MASTER_BMISP)
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#define IdexWriteBusMasterStatusPort(data) \
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IdexWritePortUchar(IDE_PCI_BUS_MASTER_BMISP, (data))
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#define IdexReadBusMasterDescriptorTablePort() \
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IdexReadPortUlong(IDE_PCI_BUS_MASTER_BMIDP)
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#define IdexWriteBusMasterDescriptorTablePort(data) \
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IdexWritePortUlong(IDE_PCI_BUS_MASTER_BMIDP, (data))
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//
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// Define the bus master interface command register flags.
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//
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#define IDE_BUS_MASTER_COMMAND_START 0x01
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#define IDE_BUS_MASTER_COMMAND_READ 0x08
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//
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// Define the bus master interface status register flags.
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//
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#define IDE_BUS_MASTER_STATUS_ACTIVE 0x01
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#define IDE_BUS_MASTER_STATUS_ERROR 0x02
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#define IDE_BUS_MASTER_STATUS_INTERRUPT 0x04
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//
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// Structure that's passed to the bus master interface to indicate the location
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// of the data buffer's pages.
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//
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typedef struct _IDE_PCI_PHYSICAL_REGION_DESCRIPTOR {
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ULONG PhysicalAddress;
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union {
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ULONG AsULong;
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struct {
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ULONG AsUShort : 16;
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ULONG Reserved : 15;
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ULONG EndOfTable : 1;
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} b;
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} ByteCount;
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} IDE_PCI_PHYSICAL_REGION_DESCRIPTOR, *PIDE_PCI_PHYSICAL_REGION_DESCRIPTOR;
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//
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// Routines that act on the driver device.
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//
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NTSTATUS
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IdexDriverIrpReturnSuccess(
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IN PDEVICE_OBJECT DeviceObject,
|
|
IN PIRP Irp
|
|
);
|
|
|
|
//
|
|
// Routines that act on the channel device.
|
|
//
|
|
|
|
BOOLEAN
|
|
FASTCALL
|
|
IdexChannelSpinWhileBusy(
|
|
OUT PUCHAR IdeStatus
|
|
);
|
|
|
|
BOOLEAN
|
|
FASTCALL
|
|
IdexChannelSpinWhileBusyAndNotDrq(
|
|
OUT PUCHAR IdeStatus
|
|
);
|
|
|
|
VOID
|
|
IdexChannelSetTimerPeriod(
|
|
IN LONG Period
|
|
);
|
|
|
|
VOID
|
|
FASTCALL
|
|
IdexChannelPrepareBufferTransfer(
|
|
IN PUCHAR Buffer,
|
|
IN ULONG ByteCount
|
|
);
|
|
|
|
VOID
|
|
IdexChannelPrepareScatterGatherTransfer(
|
|
IN PFILE_SEGMENT_ELEMENT SegmentArray,
|
|
IN ULONG SegmentByteOffset,
|
|
IN ULONG ByteCount
|
|
);
|
|
|
|
VOID
|
|
IdexChannelRestartCurrentPacket(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
IdexChannelAbortCurrentPacket(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
FASTCALL
|
|
IdexChannelInvalidParameterRequest(
|
|
IN PIRP Irp
|
|
);
|
|
|
|
VOID
|
|
IdexChannelStartIdePassThrough(
|
|
IN PIRP Irp,
|
|
IN UCHAR TargetDevice,
|
|
IN PIDE_RESET_DEVICE_ROUTINE ResetDeviceRoutine
|
|
);
|
|
|
|
NTSTATUS
|
|
IdexChannelIdentifyDevice(
|
|
IN UCHAR TargetDevice,
|
|
IN UCHAR IdentifyCommand,
|
|
OUT PIDE_IDENTIFY_DATA IdentifyData
|
|
);
|
|
|
|
NTSTATUS
|
|
IdexChannelSetTransferMode(
|
|
IN UCHAR TargetDevice,
|
|
IN UCHAR TransferMode
|
|
);
|
|
|
|
NTSTATUS
|
|
IdexChannelIssueImmediateCommand(
|
|
IN UCHAR TargetDevice,
|
|
IN UCHAR IdeCommand
|
|
);
|
|
|
|
VOID
|
|
IdexChannelCreate(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// Routines that act on the disk device.
|
|
//
|
|
|
|
VOID
|
|
IdexDiskCreateQuick(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
IdexDiskCreate(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// Routines that act on the CD-ROM device.
|
|
//
|
|
|
|
BOOLEAN
|
|
IdexCdRomPollResetComplete(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
IdexCdRomCreateQuick(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
IdexCdRomCreate(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// Routines that act on the media board device.
|
|
//
|
|
|
|
DECLSPEC_NORETURN
|
|
VOID
|
|
IdexMediaBoardFatalError(
|
|
IN ULONG ErrorCode
|
|
);
|
|
|
|
VOID
|
|
IdexMediaBoardCreateQuick(
|
|
VOID
|
|
);
|
|
|
|
VOID
|
|
IdexMediaBoardCreate(
|
|
VOID
|
|
);
|
|
|
|
//
|
|
// Routines that perform I/O port operations.
|
|
//
|
|
|
|
#pragma intrinsic(_inp,_inpw,_inpd,_outp,_outpw,_outpd)
|
|
|
|
#define IdexReadPortUchar(port) ((UCHAR)_inp((USHORT)(port)))
|
|
#define IdexReadPortUshort(port) ((USHORT)_inpw((USHORT)(port)))
|
|
#define IdexReadPortUlong(port) ((ULONG)_inpd((USHORT)(port)))
|
|
#define IdexWritePortUchar(port, data) (_outp((USHORT)(port),(UCHAR)(data)))
|
|
#define IdexWritePortUshort(port, data) (_outpw((USHORT)(port),(USHORT)(data)))
|
|
#define IdexWritePortUlong(port, data) (_outpd((USHORT)(port),(ULONG)(data)))
|
|
|
|
#define IdexReadPortBufferUshort(port, buffer, count) \
|
|
READ_PORT_BUFFER_USHORT((PUSHORT)(port), buffer, count)
|
|
#define IdexWritePortBufferUshort(port, buffer, count) \
|
|
WRITE_PORT_BUFFER_USHORT((PUSHORT)(port), buffer, count)
|
|
#define IdexReadPortBufferUlong(port, buffer, count) \
|
|
READ_PORT_BUFFER_ULONG((PULONG)(port), buffer, count)
|
|
#define IdexWritePortBufferUlong(port, buffer, count) \
|
|
WRITE_PORT_BUFFER_ULONG((PULONG)(port), buffer, count)
|
|
|
|
//
|
|
// Macros to swap the byte order of a USHORT or ULONG at compile time.
|
|
//
|
|
|
|
#define IdexConstantUshortByteSwap(ushort) \
|
|
((((USHORT)ushort) >> 8) + ((((USHORT)ushort) & 0x00FF) << 8))
|
|
|
|
#define IdexConstantUlongByteSwap(ulong) \
|
|
((((ULONG)ulong) >> 24) + ((((ULONG)ulong) & 0x00FF0000) >> 8) + \
|
|
((((ULONG)ulong) & 0x0000FF00) << 8) + ((((ULONG)ulong) & 0x000000FF) << 24))
|
|
|
|
//
|
|
// Miscellaneous routines.
|
|
//
|
|
|
|
DECLSPEC_NORETURN
|
|
VOID
|
|
IdexBugCheckWorker(
|
|
IN ULONG FileAndLineCode,
|
|
IN ULONG_PTR BugCheckParameter1
|
|
);
|
|
|
|
#define IdexBugCheck(fileid, parameter1) \
|
|
IdexBugCheckWorker((((ULONG)fileid) | __LINE__), ((ULONG_PTR)parameter1))
|
|
|
|
//
|
|
// External symbols.
|
|
//
|
|
|
|
extern DRIVER_OBJECT IdexDiskDriverObject;
|
|
extern OBJECT_TYPE IdexDiskDirectoryObjectType;
|
|
extern DRIVER_OBJECT IdexCdRomDriverObject;
|
|
extern DRIVER_OBJECT IdexMediaBoardDriverObject;
|
|
|
|
#include <poppack.h>
|
|
|
|
#endif // IDEX
|